CN103715956B - A kind of two level three-phase space vector pulse-width modulation and SVPWM optimization method thereof - Google Patents

Abstract

The invention discloses a kind of two level three-phase space vector pulse-width modulation and SVPWM optimization method thereof, for the impact that Dead Time and narrow pulse width limit, extend actual linear modulator zone, optimize Overmodulation Method, and achieve the linearization process of overmodulation easily.Two described level three-phase space vector pulse-width modulation, include given reference voltage correcting module, voltage coordinate conversion module, voltage range computing module, vector time computing module, modulation algorithm optimization module, PWM comparison point Time Calculation module six modules.The present invention, with algorithm the easiest, achieves making full use of most of busbar voltage, improves the linearity exporting fundamental voltage, reduces total harmonic distortion of output voltage.

Description

A kind of two level three-phase space vector pulse-width modulation and SVPWM optimization method thereof

Technical field

The present invention relates to the technical field of AC Motor Control, refer in particular to and a kind ofly consider the two level three-phase space vector pulse-width modulation that dead band and narrow spaces limit and SVPWM optimization method thereof.

Background technology

Pulse width modulation (PWM, pulsewidthmodulation) is the important component part of electric machine control system.Due to the high voltage utilance of vector pulse width modulation (SVPWM, spacevectorPWM) technology, low-voltage harmonic wave and the easy characteristic such as Digital Implementation, it is used widely in motor vector control.

In two level three-phase inversion systems, 8 kinds of states of switching tube can produce 6 basic voltage vectors v ₁/ v ₂/ ... / v ₆with 2 zero vector v ₀/ v ₇, the scope (voltage space) that the regular hexagon region (comprising border) that basic voltage vectors is formed can arrive for output voltage.Free voltage vector in voltage space by adjacent two basic vectors and zero vector synthesis, can be SVPWM technology.

If given reference voltage U _r(U _r∠ θ) with maximal phase voltage (the regular hexagon inradius that basic voltage vectors is formed) is benchmark standardization, standardization result u _r(u _r∠ θ) (θ ∈ [0,2 π)), u _rbe designated as modulation degree, namely so, maximum output voltage is that (amplitude is basic voltage vectors ), modulation degree is work as u _rwhen≤1, output voltage vector u _rtrack all (does not exceed inscribed circle) in regular hexagon, normally can export loop circle flux, is linear modulation district; When time, output voltage vector u _rhaving partial traces to exceed regular hexagon scope (exceeding inscribed circle), normally can not export loop circle flux, is overmodulation.

Proposing multiple overmodulation method at present, in the hope of reducing the harmonic wave of overmodulation, having reduced over modulation operation amount, improved the overmodulation linearity.

As shown in Figure 5 a, voltage space can basic vector be that vector space is divided into S1/S2/S3/S4/S5/S6 six regions, voltage vector u in each region by border _rthe adjacent basic voltage vectors v of forward direction can be passed through _k, backward adjacent basic voltage vectors v _k+1with zero vector v _z(v ₀or v ₇) synthesis, namely

$\left\{\begin{array}{c}{u}_r=t_1{v}_k+t_2{v}_{k+1}\\ 1=t_1+t_2+t_0\end{array}\right.$

Wherein T _s, T ₁, T ₂and T ₀be respectively PWM cycle, forward direction adjacent basic vector time, backward adjacent basic vector time and zero vector time, t ₁=T ₁/ T _s, t ₂=T ₂/ T _s, t ₀=T ₀/ T _s.SVPWM realizes the general symmetrical modulation adopting seven segmentations, as shown in Figure 5 b, wherein T _a, T _band T _cbe respectively the brachium pontis PWM comparison point time (high level conducting) in A phase, B phase and C phase.

But, in actual two level three-phase inversion system application, generally take the complementary PWM way of output of upper and lower bridge arm, in order to ensure that pipe can not lead directly to up and down, must insert suitable Dead Time; Meanwhile, in order to reduce switching loss, usually minimum output pulse width can be limited.Due to the impact that Dead Time and narrow spaces limit, the output duty cycle of PWM is restricted, and can only be operated in [t _lim, 1-t _lim] ∪ (0) ∪ (1) scope, namely at [t _lim, 1-t _lim] between continuously adjustabe or constant high level or constant low level, and can not (0, t _lim) and (1-t _lim, 1) between regulate, wherein t _limfor Dead Time and narrow spaces binding hours sum.Dead Time and narrow pulse width limit and reduce the actual voltage space scope that can arrive, and the Overmodulation Method performance actual linear modulator zone is reduced, proposing at present greatly reduces.

Summary of the invention

The object of the invention is to overcome the deficiencies in the prior art, there is provided a kind of and consider the two level three-phase space vector pulse-width modulation that dead band and narrow spaces limit and SVPWM optimization method thereof, extend actual linear modulator zone, optimize Overmodulation Method, and achieve the linearization process of overmodulation easily.

For achieving the above object, its two level three-phase space vector pulse-width modulation of technical scheme provided by the present invention, comprising:

Given reference voltage correcting module, according to given reference voltage u _r(u _r∠ θ), do not change voltage phase angle, as ur > 1, according to revise voltage magnitude, obtain revised reference voltage u _m(u _m∠ θ);

Voltage coordinate conversion module, for by revised reference voltage u _m(u _m∠ θ) by polar coordinate representation mode conversion to two-phase rest frame u _m(u _a, u _β), i.e. u _α=u _mcos θ and u _β=u _msin θ;

Voltage range computing module, for calculating u in two-phase rest frame _mcorresponding to the interval position in voltage space, i.e. voltage range sector;

Vector time computing module, according to described two-phase rest frame u _m(u _a, u _β) and relevant voltage interval sector obtain adjacent basic vector time t ₁, t ₂with zero vector time t ₀=1-t ₁-t ₂;

Modulation algorithm optimizes module, according to described adjacent basic vector time t ₁, t ₂with zero vector time t ₀, according to the modulation algorithm optimized, calculate the adjacent basic vector time t after optimization ₁', t ₂' and zero vector time t ₀', and trigger PWM comparison point time τ at first ₀;

PWM comparison point Time Calculation module, according to described t ₁', t ₂', τ ₀obtain A phase, B phase, C phase with relevant voltage interval sector and respectively go up PWM comparison point time T under the conducting of brachium pontis high level mutually _a, T _b, T _c.

The modulation algorithm of described optimization comprises the following steps:

1) if t ₀>=2t _lim, t ₁'=t ₁, t ₂'=t ₂, t ₀'=t ₀;

2) if t _lim≤ t ₀< 2t _lim, t ₁'=t ₁, t ₂'=t ₂, t ₀'=t ₀; Work as t ₁> t ₂time, τ ₀=0, otherwise τ ₀=t ₀';

3) t is worked as _lim/ 2≤t ₀< t _limtime, adopt equal proportion compression method, t ₀'=t _lim; Work as t ₁> t ₂time, τ ₀=0, otherwise τ ₀=t ₀';

4) t is worked as ₀< t _limwhen/2, output voltage is operated on voltage space regular hexagon border, i.e. t ₀'=0, τ ₀=0, now t ₁', t ₂' computational methods as follows:

4.1) as 0≤t ₀< t _limwhen/2 or work as t ₀< 0 ∩ t ₁+ t ₂/ 2 < 1 ∩ t ₁/ 2+t ₂during < 1, adopt equal proportion Zoom method, namely work as t ₁' < t _limtime, t ₁'=0, t ₂'=1; Work as t ₂' < t _limtime, t ₁'=1, t ₂'=0;

4.2) t is worked as ₁>=t ₂∩ t ₁+ t ₂when/2>=1, export forward direction basic vector v _k, i.e. t ₁'=1, t ₂'=0;

4.3) t is worked as ₁< t ₂∩ t ₁/ 2+t ₂when>=1, export backward basic vector v _k+1, i.e. t ₁'=0, t ₂'=1;

Wherein, described t _limfor Dead Time and narrow spaces binding hours sum.

The SVPWM optimization method of two level three-phase space vector pulse-width modulation of the present invention is: if t ₀>=2t _lim, adopt seven segmentation SVPWM; If t _lim≤ t ₀< 2t _lim, adopt DPWM1 mode, i.e. a kind of five-part form PWM; If t ₀< t _lim, voltage vector is transformed into DPWM1, syllogic PWM or one-part form PWM voltage space; Wherein,

Described t _limfor Dead Time and narrow spaces binding hours sum; In described seven segmentation SVPWM, there is no constant level, have τ ₀and τ ₇two duty-cycle limit; In described DPWM1, $\left\{\begin{array}{cc}{\mathrm{\&tau;}}_0=0,{\mathrm{\&tau;}}_7=t_0,& t_1\&GreaterEqual;t_2\\ {\mathrm{\&tau;}}_0=t_0,{\mathrm{\&tau;}}_7=0,& else\end{array}\right.,$ Namely a certain is constant level mutually, only has τ ₀or τ ₇a duty-cycle limit; In described syllogic PWM, certain two-phase is constant level, and only have an other phase voltage to regulate, virtual voltage space only has orthohexagonal discontinuous border; Described one-part form PWM is three-phase and is constant level, and virtual voltage can only be operated on basic vector and zero vector;

Because Dead Time and narrow pulse width limit, in actual overmodulation, some regions are actual can not directly be arrived, and thus needs to adopt the overmodulation method optimized to process, and comprises the following steps:

1) revise given reference voltage, make former given reference voltage range with revised given reference voltage range correspondence, i.e. u _rwith u _mbetween set up mapping relations: phase angle remains unchanged; As (1-t _lim) < u _rwhen≤1, amplitude is constant, i.e. u _m=u _r; When time, amplitude makes linear revise, namely $u_m=(\frac{2}{\sqrt{3}}+1)(u_r-1)+1\&Element;(1,4/3\&rsqb;;$

2) revised given reference voltage u _mmodulate according to the modulation algorithm of described optimization, obtain actual output voltage u _p, comprise the following steps:

2.1) t is worked as ₀>=t _limtime, directly export u _m, i.e. u _p=u _m;

2.2) t is worked as _lim/ 2≤t ₀< t _limtime, by equal proportion compression method process u _mobtain u _p, namely $\begin{array}{cc}{t}_1^{\&prime;}=\frac{t_1}{t_1+t_2}\&CenterDot;(1-t_{\lim }),& t_2^{\&prime;}=\frac{t_2}{t_1+t_2}\&CenterDot;(1-t_{\lim })\end{array},$ t ₀′＝t _lim；

2.3) t is worked as ₀< t _limwhen/2, as follows:

2.3.1) as 0≤t ₀< t _limwhen/2, by equal proportion drawing process process u _mobtain u _p, namely $t_2^{\&prime;}=\frac{t_2}{t_1+t_2},$ t ₀′＝0；

2.3.2) work as t ₀< 0 ∩ t ₁+ t ₂/ 2 < 1 ∩ t ₁/ 2+t ₂during < 1, by equal proportion compression method process u _mobtain u _p, namely $\begin{array}{cc}{t}_1^{\&prime;}=\frac{t_1}{t_1+t_2},& t_2^{\&prime;}=\frac{t_2}{t_1+t_2}\end{array},$ t ₀′＝0；

2.3.3) work as t ₁>=t ₂∩ t ₁+ t ₂when/2>=1, export forward direction basic vector v _k;

2.3.4) work as t ₁< t ₂∩ t ₁/ 2+t ₂when>=1, export backward basic vector v _k+1;

2.3.5) equal proportion stretched and drop on inaccessiable working point on voltage space regular hexagon border, with the basic voltage vectors v closed on after equal proportion compression _kor v _k+1substitute.

Compared with prior art, tool has the following advantages and beneficial effect in the present invention:

1, extend actual linear modulator zone, because Dead Time and narrow pulse width limit, the linear modulation district of seven segmentation SVPWM have lost 2t _lim, namely actual linear modulation district is u _r∈ [0, (1-2t _lim)], and after adopting the present invention, linear for reality modulator zone can be expanded to u _r∈ [0, (1-t _lim)];

2, adopt Linear Mapping mode, achieve the linearization process of overmodulation easily;

3, optimize Overmodulation Method, by the modulation algorithm integrated treatment of new actual linearly modulator zone and overmodulation, simplify modulation operation, be convenient to Project Realization;

4, achieve making full use of most of busbar voltage, reduce the difference of output voltage and reference voltage, reduce the harmonic wave of output voltage, improve and export the linearity of fundamental voltage relative to reference voltage.

Accompanying drawing explanation

Fig. 1 is the structured flowchart of two level three-phase space vector pulse-width modulation of the present invention.

Fig. 2 is the modulation algorithm flow chart of optimization of the present invention.

Fig. 3 a is the virtual voltage space diagram of seven segmentation SVPWM.

Fig. 3 b is virtual voltage space diagram of the present invention.

Fig. 4 a works as t in overmodulation method of the present invention _lim/ 2≤t ₀< t _limtime output voltage track schematic diagram.

Fig. 4 b is as 0≤t in overmodulation method of the present invention ₀< t _limthe track schematic diagram of output voltage when/2.

Fig. 4 c works as t in overmodulation method of the present invention ₀< 0 ∩ t ₁+ t ₂/ 2 < 1 ∩ t ₁/ 2+t ₂the track schematic diagram of output voltage during < 1.

Fig. 4 d works as t in overmodulation method of the present invention ₁>=t ₂∩ t ₁+ t ₂when/2>=1 or t ₁< t ₂∩ t ₁/ 2+t ₂the track schematic diagram of output voltage when>=1.

Fig. 5 a is the voltage space block plan in background technology.

Fig. 5 b is the PWM duty ratio output map of seven segmentation SVPWM.

Embodiment

Below in conjunction with specific embodiment, the invention will be further described.

The present embodiment discloses a kind ofly considers the two level three-phase space vector pulse-width modulation that dead band and narrow spaces limit and SVPWM optimization method thereof, the impact of Dead Time and narrow pulse width restriction is taken into account, with the easiest method, achieve making full use of most of busbar voltage, improve and export fundamental voltage relative to the linearity of reference voltage, reduce total harmonic distortion of output voltage.

As shown in Figure 1, two level three-phase space vector pulse-width modulation described in the present embodiment, include given reference voltage correcting module 1, voltage coordinate conversion module 2, voltage range computing module 3, vector time computing module 4, modulation algorithm optimization module 5, PWM comparison point Time Calculation module 6, wherein

Described given reference voltage correcting module 1, according to given reference voltage u _r(u _r∠ θ), do not change voltage phase angle, (1) revises voltage magnitude according to the following formula, obtains revised reference voltage u _m(u _m∠ θ);

$u_m=\left\{\begin{array}{cc}{u}_r,& u_r\&le;1\\ (\frac{2}{\sqrt{3}}+1)(u_r-1)+1,& u_r>1\end{array}\right.---\left(1\right)$

Described voltage coordinate conversion module 2, by revised reference voltage u _m(u _m∠ θ) by polar coordinate representation mode conversion to two-phase rest frame u _m(u _a, u _β), shown in (2):

$\left\{\begin{array}{c}{u}_{\mathrm{\&alpha;}}=u_m\cos \mathrm{\&theta;}\\ u_{\mathrm{\&beta;}}=u_m\sin \mathrm{\&theta;}\end{array}\right.---\left(2\right)$

Described voltage range computing module 3, according to u in two-phase rest frame _m(u _a, u _β), calculate u _mcorresponding to the interval position in voltage space, i.e. interval sector, described interval sector=4c+2b+a; Definition intermediate variable V _ref1, V _ref2, V _ref3shown in (3):

V _ref1＝u _β

$V_{ref2}=\frac{1}{2}(\sqrt{3}{u}_{\mathrm{\&alpha;}}-u_{\mathrm{\&beta;}})---\left(3\right)$

$V_{ref3}=\frac{1}{2}(-\sqrt{3}{u}_{\mathrm{\&alpha;}}-u_{\mathrm{\&beta;}})$

If V _ref1> 0, then a=1, otherwise, a=0; If V _ref2> 0, then b=1, otherwise, b=0; If V _ref3> 0, then c=1, otherwise, c=0;

Described vector time computing module 4, according to u in two-phase rest frame _m(u _a, u _β), (4) calculate X, Y, Z according to the following formula, then from lower question blank 1, check in adjacent basic vector time t by relevant voltage interval sector ₁, t ₂, so zero vector time is t ₀=1-t ₁-t ₂;

X＝u _β

$Y=\frac{1}{2}(\sqrt{3}{u}_{\mathrm{\&alpha;}}+u_{\mathrm{\&beta;}})---\left(4\right)$

$Z=\frac{1}{2}(-\sqrt{3}{u}_{\mathrm{\&alpha;}}+u_{\mathrm{\&beta;}})$

Voltage range sector question blank 1

sector

S1

S2

S3

S4

S5

S6

t 1

Y

-X

-Z

Z

X

-Y

t 2

Z

Y

X

-X

-Y

-Z

v k/v k+1

v 2/v 3

v 6/v 1

v 1/v 2

v 4/v 5

v 3/v 4

v 5/v 6

T a/(T s/2)

τ 0+t 2′

τ 0

τ 0

τ 0+t 1′+t 2′

τ 0+t 1′

τ 0+t 1′+t 2′

T b/(T s/2)

τ 0

τ 0+t 1′+t 2′

τ 0+t 1′

τ 0+t 2′

τ 0+t 1′+t 2′

τ 0

T c/(T s/2)

τ 0+t 1′+t 2′

τ 0+t 2′

τ 0+t 1′+t 2′

τ 0

τ 0

τ 0+t 1′

Described modulation algorithm optimizes module 5, according to adjacent basic vector time t ₁, t ₂with zero vector time t ₀, according to the modulation algorithm optimized, calculate the adjacent basic vector time t after optimization ₁', t ₂' and zero vector time t ₀', and trigger PWM comparison point time τ at first ₀; As shown in Figure 2, the modulation algorithm concrete condition of described optimization is as follows:

1) if t ₀>=2t _lim, t ₁'=t ₁, t ₂'=t ₂, t ₀'=t ₀;

2) if t _lim≤ t ₀< 2t _lim, t ₁'=t ₁, t ₂'=t ₂, t ₀'=t ₀; Work as t ₁> t ₂time, τ ₀=0, otherwise τ ₀=t ₀';

3) t is worked as _lim/ 2≤t ₀< t _limtime, adopt equal proportion compression method, t ₀'=t _lim; Work as t ₁> t ₂time, τ ₀=0, otherwise τ ₀=t ₀';

4) t is worked as ₀< t _limwhen/2, output voltage is operated on voltage space regular hexagon border, i.e. t ₀'=0, τ ₀=0, now t ₁', t ₂' computational methods as follows:

4.1) as 0≤t ₀< t _limwhen/2 or work as t ₀< 0 ∩ t ₁+ t ₂/ 2 < 1 ∩ t ₁/ 2+t ₂during < 1, adopt equal proportion Zoom method, namely work as t ₁' < t _limtime, t ₁'=0, t ₂'=1; Work as t ₂' < t _limtime, t ₁'=1, t ₂'=0;

4.2) t is worked as ₁>=t ₂∩ t ₁+ t ₂when/2>=1, export forward direction basic vector v _k, i.e. t ₁'=1, t ₂'=0;

4.3) t is worked as ₁< t ₂∩ t ₁/ 2+t ₂when>=1, export backward basic vector v _k+1, i.e. t ₁'=0, t ₂'=1;

Above-mentioned t _limfor Dead Time and narrow spaces binding hours sum;

Described PWM comparison point Time Calculation module 6, according to t ₁', t ₂', τ ₀from upper question blank 1, check in A phase, B phase, C phase by voltage range sector and respectively go up PWM comparison point time T under the conducting of brachium pontis high level mutually _a, T _b, T _c.

In addition, SVPWM optimization method described in the present embodiment, that seven traditional segmentation SVPWM are improved to the discontinuous PWM (GDPWM of composite type, GeneralizedDiscontinuousPWM), virtual voltage space is region shown in Fig. 3 b dark parts from area extension shown in Fig. 3 a dark parts, and its concrete condition is as follows:

If t ₀>=2t _lim, adopt seven segmentation SVPWM; If t _lim≤ t ₀< 2t _lim, adopt DPWM1 mode, i.e. a kind of five-part form PWM; If t ₀< t _lim, adopt certain modulating rule voltage vector to be transformed into DPWM1, syllogic PWM or one-part form PWM voltage space.

Described t _limfor Dead Time and narrow spaces binding hours sum; In described seven segmentation SVPWM, there is no constant level, have τ ₀and τ ₇two duty-cycle limit (i.e. zero vector time t ₀>=2t _lim); In described DPWM1, $\left\{\begin{array}{cc}{\mathrm{\&tau;}}_0=0,{\mathrm{\&tau;}}_7=t_0,& t_1\&GreaterEqual;t_2\\ {\mathrm{\&tau;}}_0=t_0,{\mathrm{\&tau;}}_7=0,& else\end{array}\right.,$ Namely a certain is constant level mutually, only has τ ₀or τ ₇a duty-cycle limit (i.e. zero vector time t ₀>=t _lim); In described syllogic PWM, certain two-phase is constant level, and only have an other phase voltage to regulate, virtual voltage space only has orthohexagonal discontinuous border; Described one-part form PWM is three-phase and is constant level, and virtual voltage can only be operated on basic vector and zero vector.

Because Dead Time and narrow pulse width limit, the linear modulation district of seven segmentation SVPWM have lost 2t _lim, namely actual linear modulation district is u _r∈ [0, (1-2t _lim)].After adopting the discontinuous PWM of composite type of the present invention, linear for reality modulator zone can be expanded to u _r∈ [0, (1-t _lim)].As shown in Figure 3 b, be new linear modulation district (0≤u in inscribed circle _r≤ (1-t _lim)), inscribed circle be outward actual overmodulation ( ).In new linear modulation district, adopt taking over seamlessly of seven segmentation SVPWM to DPWM1; In actual overmodulation, directly can not arrive because some regions are actual, thus need to adopt the overmodulation method optimized to process.

In actual overmodulation, note u _rfor former given reference voltage (referencevoltage), u _mfor revised given reference voltage (modifiedreferencevoltage), u _pfor the actual output voltage (practicalvoltage) after ovennodulation process.Above-mentioned ovennodulation process comprises following two steps:

1) revise given reference voltage, make former given reference voltage range with revised given reference voltage range correspondence, i.e. u _rwith u _mbetween set up mapping relations: phase angle remains unchanged; As (1-t _lim) < u _rwhen≤1, amplitude is constant, i.e. u _m=u _r; When time, amplitude makes linear revise, namely $u_m=(\frac{2}{\sqrt{3}}+1)(u_r-1)+1\&Element;(1,4/3\&rsqb;.$

2) revised given reference voltage u _mmodulate according to the modulation algorithm of described optimization, obtain actual output voltage u _p:

2.1) t is worked as ₀>=t _limtime, directly export u _m, i.e. u _p=u _m;

2.2) t is worked as _lim/ 2≤t ₀< t _limtime, by the process of equal proportion compression method shown in Fig. 4 a u _mobtain u _p, namely $\begin{array}{cc}{t}_1^{\&prime;}=\frac{t_1}{t_1+t_2}\&CenterDot;(1-t_{\lim }),& t_2^{\&prime;}=\frac{t_2}{t_1+t_2}\&CenterDot;(1-t_{\lim })\end{array},$ t ₀′＝t _lim；

2.3) t is worked as ₀< t _limwhen/2, as follows:

2.3.1) as 0≤t ₀< t _limwhen/2, by the process of equal proportion drawing process shown in Fig. 4 b u _mobtain u _p, namely $\begin{array}{cc}{t}_1^{\&prime;}=\frac{t_1}{t_1+t_2},& t_2^{\&prime;}=\frac{t_2}{t_1+t_2}\end{array},$ t ₀′＝0；

2.3.2) work as u _mduring ∈ BCD, i.e. t ₀< 0 ∩ t ₁+ t ₂/ 2 < 1 ∩ t ₁/ 2+t ₂during < 1, by the process of equal proportion compression method shown in Fig. 4 c u _mobtain u _p, namely t ₀'=0;

2.3.3) work as u _mduring ∈ BDF, i.e. t ₁>=t ₂∩ t ₁+ t ₂when/2>=1, by exporting forward direction basic vector v shown in Fig. 4 d _k;

2.3.4) work as u _mduring ∈ CDE, i.e. t ₁< t ₂∩ t ₁/ 2+t ₂when>=1, by exporting backward basic vector v shown in Fig. 4 d _k+1;

2.3.5) Fig. 4 b equal proportion stretched and drop on inaccessiable working point on voltage space regular hexagon border, with the basic voltage vectors v closed on after the compression of Fig. 4 c equal proportion _kor v _k+1substitute.

The examples of implementation of the above are only the preferred embodiment of the present invention, not limit practical range of the present invention with this, therefore the change that all shapes according to the present invention, principle are done, all should be encompassed in protection scope of the present invention.

Claims (3)

1. two level three-phase space vector pulse-width modulation, is characterized in that, comprising:

Given reference voltage correcting module (1), according to given reference voltage u _r(u _r∠ θ), do not change voltage phase angle, work as u _rduring > 1, according to revise voltage magnitude, obtain revised reference voltage u _m(u _m∠ θ);

Voltage coordinate conversion module (2), for by revised reference voltage u _m(u _m∠ θ) by polar coordinate representation mode conversion to two-phase rest frame u _m(u _a, u _β), i.e. u _α=u _mcos θ and u _β=u _msin θ;

Voltage range computing module (3), for calculating u in two-phase rest frame _m(u _a, u _β) corresponding to the interval position in voltage space, i.e. voltage range sector;

Vector time computing module (4), according to described two-phase rest frame u _m(u _a, u _β) and relevant voltage interval sector obtain adjacent basic vector time t ₁, t ₂with zero vector time t ₀=1-t ₁-t ₂;

Modulation algorithm optimizes module (5), according to described adjacent basic vector time t ₁, t ₂with zero vector time t ₀, according to the modulation algorithm optimized, calculate the adjacent basic vector time t ' after optimization ₁, t ' ₂with zero vector time t ' ₀, and trigger PWM comparison point time τ at first ₀;

PWM comparison point Time Calculation module (6), according to described t ' ₁, t ' ₂, τ ₀obtain A phase, B phase, C phase with relevant voltage interval sector and respectively go up PWM comparison point time T under the conducting of brachium pontis high level mutually _a, T _b, T _c.

2. a kind of two level three-phase space vector pulse-width modulation according to claim 1, it is characterized in that, the modulation algorithm of described optimization comprises the following steps:

1) if t ₀>=2t _lim, t ' ₁=t ₁, t ' ₂=t ₂, t ' ₀=t ₀;

2) if t _lim≤ t ₀< 2t _lim, t ' ₁=t ₁, t ' ₂=t ₂, t ' ₀=t ₀; Work as t ₁> t ₂time, τ ₀=0, otherwise τ ₀=t ' ₀;

3) t is worked as _lim/ 2≤t ₀< t _limtime, adopt equal proportion compression method, t ' ₀=t _lim; Work as t ₁> t ₂time, τ ₀=0, otherwise τ ₀=t ' ₀;

4) t is worked as ₀< t _limwhen/2, output voltage is operated on voltage space regular hexagon border, i.e. t ' ₀=0, τ ₀=0, now t ' ₁, t ' ₂computational methods as follows:

4.1) as 0≤t ₀< t _limwhen/2 or work as t ₀< 0 ∩ t ₁+ t ₂/ 2 < 1 ∩ t ₁/ 2+t ₂during < 1, adopt equal proportion Zoom method, namely as t ' ₁< t _limtime, t ' ₁=0, t ' ₂=1; As t ' ₂< t _limtime, t ' ₁=1, t ' ₂=0;

4.2) t is worked as ₁>=t ₂∩ t ₁+ t ₂when/2>=1, export forward direction basic vector v _k, i.e. t ' ₁=1, t ' ₂=0;

4.3) t is worked as ₁< t ₂∩ t ₁/ 2+t ₂when>=1, export backward basic vector v _k+1, i.e. t ' ₁=0, t ' ₂=1;

Wherein, described t _limfor Dead Time and narrow spaces binding hours sum.

3. a SVPWM optimization method for two level three-phase space vector pulse-width modulation as claimed in claim 1, is characterized in that: if t ₀>=2t _lim, adopt seven segmentation SVPWM; If t _lim≤ t ₀< 2t _lim, adopt DPWM1 mode, i.e. a kind of five-part form PWM; If t ₀< t _lim, voltage vector is transformed into DPWM1, syllogic PWM or one-part form PWM voltage space; Wherein,

Described t _limfor Dead Time and narrow spaces binding hours sum; In described seven segmentation SVPWM, there is no constant level, have τ ₀and τ ₇two duty-cycle limit; In described DPWM1, $\left\{\begin{array}{cc}{\mathrm{\&tau;}}_0=0,{\mathrm{\&tau;}}_7=t_0,& t_1\&GreaterEqual;t_2\\ {\mathrm{\&tau;}}_0=t_0,{\mathrm{\&tau;}}_7=0,& else\end{array}\right.,$ Namely a certain is constant level mutually, only has τ ₀or τ ₇a duty-cycle limit; In described syllogic PWM, certain two-phase is constant level, and only have an other phase voltage to regulate, virtual voltage space only has orthohexagonal discontinuous border; Described one-part form PWM is three-phase and is constant level, and virtual voltage can only be operated on basic vector and zero vector;

Because Dead Time and narrow pulse width limit, in actual overmodulation, some regions are actual can not directly be arrived, and thus needs to adopt the overmodulation method optimized to process, and comprises the following steps:

1) revise given reference voltage, make former given reference voltage range with revised given reference voltage range correspondence, i.e. u _rwith u _mbetween set up mapping relations: phase angle remains unchanged; As (1-t _lim) < u _rwhen≤1, amplitude is constant, i.e. u _m=u _r; When time, amplitude makes linear revise, namely $u_m=(\frac{2}{\sqrt{3}}+1)(u_r-1)+1\&Element;(1,4/3\&rsqb;;$

2) revised given reference voltage u _mmodulate according to the modulation algorithm of described optimization, obtain actual output voltage u _p, comprise the following steps:

2.1) t is worked as ₀>=t _limtime, directly export u _m, i.e. u _p=u _m;

2.2) t is worked as _lim/ 2≤t ₀< t _limtime, by equal proportion compression method process u _mobtain u _p, namely $\begin{array}{ccc}{t}_1^{\&prime;}=\frac{t_1}{t_1+t_2}\&CenterDot;(1-t_{\lim }),& t_2^{\&prime;}=\frac{t_2}{t_1+t_2}\&CenterDot;(1-t_{\lim })& t_0^{\&prime;}=t_{lim}\end{array};$

2.3) t is worked as ₀< t _limwhen/2, as follows:

2.3.1) as 0≤t ₀< t _limwhen/2, by equal proportion drawing process process u _mobtain u _p, namely $t_2^{\&prime;}=\frac{t_2}{t_1+t_2},$ t′ ₀＝0；

2.3.2) work as t ₀< 0 ∩ t ₁+ t ₂/ 2 < 1 ∩ t ₁/ 2+t ₂during < 1, by equal proportion compression method process u _mobtain u _p, namely $\begin{array}{ccc}{t}_1^{\&prime;}=\frac{t_1}{t_1+t_2},& t_2^{\&prime;}=\frac{t_2}{t_1+t_2},& t_0^{\&prime;}=0\end{array};$

2.3.3) work as t ₁>=t ₂∩ t ₁+ t ₂when/2>=1, export forward direction basic vector v _k;

2.3.4) work as t ₁< t ₂∩ t ₁/ 2+t ₂when>=1, export backward basic vector v _k+1;

2.3.5) equal proportion stretched and drop on inaccessiable working point on voltage space regular hexagon border, with the basic voltage vectors v closed on after equal proportion compression _kor v _k+1substitute.