CN103683179B - Switchgear in current distribution system - Google Patents
Switchgear in current distribution system Download PDFInfo
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- CN103683179B CN103683179B CN201210419507.1A CN201210419507A CN103683179B CN 103683179 B CN103683179 B CN 103683179B CN 201210419507 A CN201210419507 A CN 201210419507A CN 103683179 B CN103683179 B CN 103683179B
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Abstract
The present invention relates to a kind of switchgear, especially there is low-voltage power switch, it disconnects automatically when meeting previously given current condition respectively, the digital communication connection (6 being connected with the public interface (8) of one on the switch (2) with above setting, 7) it is and with form serial bit sequence (VBF, BF data signal (S8), SI), it is made up of high state and low state, and pass through communication connection (6 when meeting current condition, 7) switch (2) forwardly set is sent, the switch (2) wherein above set is not turned off at least after signal (S8) is received within a previously given time delay respectively.To be able to ensure defencive function, it is proposed that：Each position being set (B3 B7) is built by low state, and each multiple successive position (B3 directly with one another of bit sequence (VBF), B3 and B6, B7 the previously given position (B5, B6) of the last time zone (H)) or at the end of bit sequence (BF) is set.
Description
Technical field
The present invention relates to the switchgear in the current distribution system according to the present invention.
Background technology
It is known in current distribution system by switch particularly low-voltage power switch to (or the power consumption of individual equipment branch road
Device) distribution electric current.These switches are respectively that rated current designs and interrupted in case of a fault the electric current for flowing through switch, for example
The electric current occurred in short circuit.The break down or equipment branch road closest to failure should only be cut off respectively herein.It is this
Behavior is referred to as selectively cutting off.At least each seen from power supply exist in the switch above set detection means and
One trip unit.Detection means gathers the electric current for flowing through switch by converter respectively, and wherein trip unit verifies whether full
The previously given current condition of foot.If it is, trip unit makes switch trip.
Known such switchgear, wherein switch communicates with one another selectively to cut off.Then one it is for example special because
To notify what is above set to open this by corresponding signal in the presence of short-circuit (the setting below) switch for meeting current condition
Close.The switch above set as a result does not disconnect itself immediately, but in the defined time (prespecified time delay)
Whether the switch that interior wait is set below threads off.If the switch set below is not being threaded off after above-mentioned time delay,
The switch interrupts electric current flowing above set.The switch that the avenues of communication is set below upwards by supplier of electricity respectively is carried out.People
This selectivity is called the selectivity control ZSS of shortening time, and it is also referred to as ZSI (Zone Selective
Interlocking, zone selective interlock).
Signal can be built as data signal, as known to from US 7058482.
If directly setting multiple switch behind a switch, they are generally for example led to by a public interface
A bus is crossed to be connected with the switch above set.
Have the disadvantage, in the known communication by data signal, if the switch that two switches are forwardly set simultaneously
Signal is sent, then may occur uncertain state on public interface, this may influence defencive function.
The content of the invention
The task of the present invention is to avoid uncertain state, to ensure defencive function at any time.
The task is solved by the feature of the present invention；The present invention describes favourable design.
First scheme is provided, the position being set of the first bit sequence (Bitfolge) of signal is built by low state and is led to
Cross high state and build the position being not set, the signal is started with a position being set respectively to be synchronous, and the first bit sequence
There are multiple successive positions being set directly with one another respectively.
To shorten time delay, it is proposed that：A data signal is provided, it includes the second bit sequence, and its position is by high state
Constituted with low state, and the switch that it is forwardly set by communicating to connect respectively by the switch set below is sent, its
In, the switch above set disconnects after the signal is received respectively, wherein, the second bit sequence has multiple phases directly with one another respectively
After the position being set, it is and different from the first bit sequence by the position being set at least one position.
If the number of the position being set successive directly with one another of the second bit sequence is more than the straight each other of the first bit sequence
The number of the successive position being set is connect, then can improve defencive function.
If each successive position being set directly with one another of the first bit sequence in the case where there are other bit sequences
Number is more than the number of the position being set successive directly with one another of other bit sequences, then can obtain the further of defencive function
Improve.
If the first bit sequence is multiple to have the position being set successive directly with one another, it can also realize and preferably protect.
It is suitable that the temporal bit length of single position is identical respectively.
Second solution provides that the position being set of bit sequence is built by low state, and the bit sequence is by following one another
Time zone build, the very first time region there is the position that is set at the beginning of bit sequence, when one it is previously given
Position or multiple previously given positions time zone last when being set include delay information, last time zone when
Between upper long than remaining time zone, and previously given one of last time zone that ought be at the end of bit sequence
Or multiple positions are when being set, the signal trigger delay time.
Brief description of the drawings
The present invention is described in detail below according to one embodiment.In accompanying drawing：
Fig. 1 shows a current distribution system, above set with one and two switches set below,
Fig. 2 shows the communication connection of the switch according to Fig. 1, for the information that transmission form is data signal,
Fig. 3 shows the example of the signal according to Fig. 2,
Fig. 4 shows the example of the signal according to Fig. 3, and it includes delay information,
Fig. 5 shows the example of the signal according to Fig. 3, and it includes revocation information, and
Fig. 6 shows the example of the signal according to Fig. 2, and it is made up of three time zones.
Embodiment
Fig. 1 shows a kind of electric current distribution 1, and with three switches 2,3,4, they are constructed as low-voltage power switch, and
And connected in power supply 5.From power supply 5, switch 2 is directly set before two switches 3,4, and two switches 3,4 directly exist
Switch 2 is set below.
The electric current for flowing through the switch 3,4 directly set below also flows through the switch 2 above set.Each switch 2,3,
4 automatically disconnect respectively when generally meeting previously given current condition, are when more than current threshold here.Current threshold
Value is for example exceeded in short circuit.
Switch 2,3,4 is set according to hierarchical level (hierarchically), wherein switch 2 sets up a hierarchical level (grade), is directly existed
The switch 3,4 set below is set up in its lower hierarchical level (grade) set.Then the switch directly set below in switch 3,4
(here in the absence of) sets up hierarchical level for being located under it, etc..
Each switch 2 and 3, a 4 prespecified time delays to a level, it will switch after more than current threshold
2nd, 3,4 dropout and the interruption delay of electric current time delay thus.All switches 2 of the time delay for same one-level
All identical respectively with 3,4, it increases on the direction towards power supply 5.
Because switch 3,4 constitutes nethermost levels, their (preferably) forthwith thread off, that is to say, that they prolong
The slow time is 0ms.The time delay of switch 2 is, for example, 50ms herein.(in the case where being distributed according to Fig. 1 electric current, if
Another unique level is existed under in switch 3,4 and its switch constitutes nethermost level and therefore correspondingly (excellent
Choosing) forthwith to thread off, then the time delay for switching 2 is, for example, 100ms, and the time delay of switch 3,4 is 50ms.)
If switch 3 is not threaded off also more than current threshold and after the 50ms of switch 2 time delay,
(above setting) switch 2 is threaded off.
The time delay of the switch above set for reduction, is only the time delay of switch 2 here, and switch 3,4 passes through logical
Letter connection 6,7 is connected to each other.Connection 6,7 connects 6a, 7a as bus and realized, and in a public affairs of the switch 2 above set
Converge at common EBI 8.
ZSI systems (or the ZSI connections of 6a, 7a switch 2,3,4 are connected by bus) are diagrammatically illustrated in fig. 2
Basic structure.As can be seen that each switch 2,3,4 had both had communication input ZSI_IN2, ZSI_IN3, ZSI_IN4, also have
There are communication output ZSI_OUT2, ZSI_OUT3, ZSI_OUT4, they are belonging respectively to an ETU/ZSI module：ETU/ZSI2、
ETU/ZSI3, ETU/ZSI4, wherein, ZSI be Zone Selective Interlocking (Signal
Abbreviation selectively), ETU is the abbreviation of Electronic Trip Unit (electronics trip unit).Public EBI 8
At the input ZSI_IN2 of the switch 2 above set.Connected by bus behind 6a, 7a, the switch 2 above set and two
The switch 3,4 of setting exchanges information, that is to say, that bus connection 6a, 7a are bi-directionally connected herein, but can also be configured to
Unidirectional connection between set below 3,4 and the switch 2 above set.The information for connecting 6a, 7a by bus is exchanged for example
Carried out by transmission and reception signal S1-S9.
Fig. 3 shows such as nine different signal S1-S9, and they are built in the form of the position coding of numeral.Signal
Position B1-B20 (binary digits, the binary digit) compositions that S1-S9 follows one another on the time, their voltage electricity
It is flat to be either located at 0 volt (low state) herein or positioned at+5 volts (high state).The time span of one position is divided herein
10 μ s (microsecond) are not defined as.One position is set (that is, logic 1) when it has low state, when it has high state not
It is set (that is, logical zero), that is to say, that depending on what is existed in the corresponding position of bit sequence be low state or high state.
Voltage level must in high regime exist prespecified in all signal S1-S9 before 20 position B1-B20 beginning
At least 60 μ s.
Each signal S1-S9 is started with the sync bit a being set B1, and followed by position B2, it is not set to respectively
Position.The two B1, B2 (logical binary number " 10 ", that is, a binary number 1 and a binary number 0) are in signal S1-
The starting of S9 is respectively used to synchronization, and they are represented as synchronization bit sequence SBF in figure 3.
Follow five position B3-B7 first after two positions B1, B2, they constitute a position for including the information to be transmitted
Sequence, hereinafter referred to as signal bit sequence IBF.Signal bit sequence IBF all five position B3-B7 can be set in theory
Position；Bit sequence IBF most four position B3-B7 are set in the case of signal S1-S9 in figure 3.
Repeated one by one for redundancy reasons without synchronous signal bit sequence IBF, wherein, in every three information bits
One position B8, B14, B20 being not set is set between sequence IBF as framing bits TB.
Binary logic correspondences 10 11,011 0 11,011 0 of the signal S8 (postpones signal VS) together with it is shown in Fig. 4
11011 0.Postpones signal VS is used for, and starts the time delay of the switch 2 above set by the switch 3 or 4 set below, here
It is after the current threshold more than switch 3 or 4.Signal S8 three signal bit sequence IBF each (logical binary number
11011), referred to below as postpone bit sequence VBF, respectively by two directly with one another the successive position (logic 11) being set constitute, it
By a position being not set (logical zero) separate.Two directly with one another the successive position being set for first delay
Bit sequence VBF is B3, B4 and B6, B7, that is to say, that two positions to B3, B4 and B6, B7 (be respectively logic 11), they
Here exist twice.
That is, general earth signal S8 has (first) bit sequence, that is, postpone bit sequence VBF, repeatedly with many
The individual successive position (B3, B4 and B6, the B7 that are set directly with one another；…).Successive position (B3, B4 and B6, B7 directly with one another；…)
Repeatedly (being twice here) deposits in delay bit sequence VBF (logical binary number 10 11,011 0 11,011 0 11,011 0)
.
If switch 3 recognizes short circuit, the switch 2 that it is forwardly set sends signal S8, and switch 2 equally recognizes short
Road, but do not thread off, and the time delay of the 50ms to its reception triggering prespecified, by signal S8 is to wait for, also
It is to say delay (oneself) dropout.If switch 3 is not threaded off also after 50ms, the switch 2 above set is threaded off.
If the interruption by the electric current of switch 3 is impossible for some reason, switch 3 by signal S9, (believe by revocation
Number AS) again revocation (end) by signal S8 trigger before the delay of switch 2 that sets.
Signal S9 is illustrated in Figure 5, and includes revocation bit sequence ABF (logical binaries as signal bit sequence IBF
Number 00111).B3, B4, B5, B6, B7 for the first revocation bit sequence ABF, it have two directly with one another it is successive not by
Position B3, B4 (logical binary number 00) of set and three directly with one another successive position B5, B6, B7 for being set (logic two is entered
Number 111 processed), wherein delay bit sequence VBF and revocation bit sequence ABF ascend the throne a position, B5 is different from each other.Here position is cancelled
The number of sequence ABF position successive directly with one another is more than the delay bit sequence VBF triggered number.
General earth signal S9 includes (second) bit sequence, that is, cancels bit sequence ABF, it has as signal S8
Multiple successive positions directly with one another.Two bit sequences, that is, postpone bit sequence VBF and revocation bit sequence ABF, at least one position
(position B5, B11, B17) is different from each other.Here it is somebody's turn to do successive directly with one another being set to of (second) bit sequence (revocation bit sequence ABF)
The number of the position of position is more than the position being set of (first) bit sequence (delay bit sequence VBF) triggered.
If switch 3 is not turned off due to the technical problem of appearance, the switch 2 that it is forwardly set sends signal S9, should
Signal is cancelled by the delay of the signal S8 switches 2 triggered again, and is switched 2 and threaded off immediately.
The signal S1-S7 existed outside signal S8, S9 is without the position being set successive directly with one another.
In general, the number of signal S8, S9 two bit sequences VBF, ABF position successive directly with one another is more than signal
The number of S1-S7 bit sequence IBF position successive directly with one another, the number of the latter is, for example, one here.
Fig. 6 shows that signal S1-S9 information can also be alternatively included in a signal SI, and signal SI is by band
The bit sequence BF for having three time zones SYN, IL, H is constituted, and wherein time zone SYN, IL, H is set one by one respectively,
And there is the position (being B1, B2, B3, B4, B5, B6 here) being set of the number of prespecified fixation respectively.Each
Time zone SYN, IL, H include at least one information SYN, ESCD, S, G, V.Very first time region SYN includes synchronization information
SYN, is the sync bit a being set B1 here.The second time zone with three (can be set) position B2, B3, B4
IL, i.e. interlock time region, herein comprising three information：Early stage short-circuit detecting (ESCD), short time delay (S), ground connection event
Hinder electric current (earth-fault current G), each of which position B2, B3, B4 is corresponding to an information：ESCD、S、G.To be more straight in Fig. 6
See all three B2, B3, B4 to be all set, actually the unique position B2 or B3 or B4 respectively in only three positions is set to
Position.It is in last time zone H to postpone information V to be included in the 3rd, that is to say, that sequence B F in place end is set.It can
To be made up of one or more position, it is made up of here two positions B5, B6.
That is, information SYN, ESCD, S, G, V are included in signal SI with fixed order one by one, wherein,
For position B2, B3, B4, B5, B6 belonging to set information SYN, ESCD, S, G, V respectively necessary set.
Usually delay information V is arranged at one of bit sequence BF far away from time zone H below.
Bit sequence BF (usually) is made up of time zone SYN, IL, the H followed one another, and bit sequence BF first when
Between region (carry synchronization information SYN) there is a position being set respectively.If bit sequence BF last time zone
One or more previously given position (being B5, B6 here) of (being H here) is set, then signal SI releases time delay.
Here position B1, B2, B3, B4, B5, B6 difference is their length in this embodiment.Reason is, position B2,
" basic bit " that B3, B4 actually have position B1 length by two is constituted, and position B5, B6 are then constituted by three.It may be said that position B1
Only it is made up of one " basic bit ".When only having delay information V time zone H in time than remaining from the reason
Between region SYN, IL length, preferably it is longer than two other time zone SYN, IL as shown in Figure 6.
It should be noted that each switch 2,3,4 has an intrinsic time delay by structures shape respectively, it can not possibly quilt
It is less than, and is, for example, 35ms herein.It must be added with the time delay above-mentioned for all switches 2,3,4 respectively.
Claims (7)
1. a kind of switchgear distributed for electric current, seen with one from power supply (5) in the switch (2) above set and at least
Two direct switches (3,4) set behind,
The switch contact automatic disconnection respectively of (2,3,4) is switched wherein when meeting previously given current condition, and
The electric current for wherein flowing through the switch (3,4) directly set below also flows through the switch above set,
(6,7) are connected with the digital communication between the switch (2,3,4) set below above set and direct, it
Be connected by a public interface (8) with the switch (2) above set, and
With data signal (S8), it includes a first serial bit sequence (VBF), its position (B3, B4, B5, B6, B7) by
High state and low state are constituted, and it is respectively by a switch set below (3,4) by communicating to connect (6,7) forwardly
The switch (2) of setting is sent, wherein, the switch (2) above set respectively after signal (S8) is received at least one in advance to
Do not turned off in fixed time delay,
Characterized in that,
The position (B3-B7) being set of the first bit sequence (VBF) of the signal (S8) is built by low state, without being set to
The position (B3-B7) of position is built by high state,
The signal is started with a position being set (B1) respectively in order to synchronous, and
First bit sequence (VBF) has multiple successive positions (B3, B4 and B6, B7) being set directly with one another respectively.
2. switchgear according to claim 1, it is characterised in that
A data signal (S9) is provided, it includes the second bit sequence (ABF), and its position (B3, B4, B5, B6, B7) is by high state
Constituted with low state, and it is forwardly set by communicating to connect (6,7) respectively by a switch set below (3,4)
Switch (2) send, wherein in reception, the signal (S9) disconnects the switch (2) above set afterwards respectively, the wherein second sequence
Arrange (ABF) has multiple successive positions (B5-B7) being set directly with one another respectively, and passes through one at least one position
The individual position (B5) being set is different from the first bit sequence (VBF).
3. switchgear according to claim 2, it is characterised in that
The number of the position (B5, B6, B7) being set successive directly with one another of second bit sequence (ABF) is more than the first bit sequence
(VBF) the position (B3, the B4 that are set successive directly with one another；B6, B7) number.
4. the switchgear according to one of claim 2-3, it is characterised in that
Each successive position being set directly with one another of the first bit sequence (VBF) in the case where there are other bit sequences (IBF)
Number be more than other bit sequences (IBF) the position being set successive directly with one another number.
5. the switchgear according to one of claim 1-3, it is characterised in that
First bit sequence (VBF) is multiple to have the position (B3, the B4 that are set successive directly with one another；B6, B7).
6. the switchgear according to one of claim 1-3, it is characterised in that
The temporal bit length difference of position (B1-B7) is identical.
7. a kind of switchgear of current distribution system, seen with one from power supply (5) in the switch (2) above set and at least
Two direct switches (3,4) set behind,
It is automatic respectively wherein when meeting previously given current condition to disconnect, and
The electric current for wherein flowing through the switch (3,4) directly set below also flows through the switch (2) above set,
(6,7) are connected with the digital communication between the switch (2,3,4) set below above set and direct, it
Be connected by a public interface (8) with the switch (2) above set, and
With the data signal (SI) that form is serial bit sequence (BF), it is made up of high state and low state, and by one
The switch (2) that the individual switch (3,4) set below is forwardly set by communicating to connect (6,7) respectively is sent, wherein above setting
The switch (2) put is not turned off at least after signal (SI) is received within a previously given time delay respectively,
Characterized in that,
The position (B1-B6) being set of bit sequence (BF) is built by low state,
Bit sequence (BF) is built by the time zone (SYN, IL, H) followed one another,
Very first time region (SYN) has with the synchronization of a position being set (B1) at the beginning of bit sequence (BF),
If a previously given position or multiple previously given positions (B5, B6) are set, then last time zone (H)
Comprising delay information (V), and
If previously given one of the last time zone (H) at the end of bit sequence (BF) is previously given more
Individual position (B5, B6) is set, then signal (SI) the trigger delay time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210419507.1A CN103683179B (en) | 2012-08-30 | 2012-08-30 | Switchgear in current distribution system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210419507.1A CN103683179B (en) | 2012-08-30 | 2012-08-30 | Switchgear in current distribution system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103683179A CN103683179A (en) | 2014-03-26 |
| CN103683179B true CN103683179B (en) | 2017-11-03 |
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ID=50319864
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210419507.1A Expired - Fee Related CN103683179B (en) | 2012-08-30 | 2012-08-30 | Switchgear in current distribution system |
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| Country | Link |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003073176A1 (en) * | 2002-02-25 | 2003-09-04 | General Electric Company | Protection system for power distribution systems |
| CN1805235A (en) * | 2005-12-08 | 2006-07-19 | Tcl低压电器(无锡)有限公司 | Regioselectivity interlocking apparatus |
| CN101771269A (en) * | 2008-12-31 | 2010-07-07 | 通用电气公司 | Directional zone select interlock method |
-
2012
- 2012-08-30 CN CN201210419507.1A patent/CN103683179B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003073176A1 (en) * | 2002-02-25 | 2003-09-04 | General Electric Company | Protection system for power distribution systems |
| CN1805235A (en) * | 2005-12-08 | 2006-07-19 | Tcl低压电器(无锡)有限公司 | Regioselectivity interlocking apparatus |
| CN101771269A (en) * | 2008-12-31 | 2010-07-07 | 通用电气公司 | Directional zone select interlock method |
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| Publication number | Publication date |
|---|---|
| CN103683179A (en) | 2014-03-26 |
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