CN103681334A - Method for inhibiting depletion of grid polysilicon in PMOS device technology - Google Patents
Method for inhibiting depletion of grid polysilicon in PMOS device technology Download PDFInfo
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- CN103681334A CN103681334A CN201210337223.8A CN201210337223A CN103681334A CN 103681334 A CN103681334 A CN 103681334A CN 201210337223 A CN201210337223 A CN 201210337223A CN 103681334 A CN103681334 A CN 103681334A
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- polycrystalline silicon
- grid polycrystalline
- pmos device
- boron
- grid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
Abstract
The invention discloses a method for inhibiting depletion of a grid polysilicon in a PMOS (p-channel metal oxide semiconductor) device technology. The method comprises the following steps: implanting boron ions into the grid polysilicon; implanting nitrogen ions on the surface of the grid polysilicon; forming a wolfram silicon layer on the surface of the grid polysilicon. Through nitrogen ion implantation after boron ion implantation into the grid polysilicon of a PMOS device, a dense nitride film can be formed on the surface of the grid polysilicon, and the nitride film can prevent boron from diffusing to the surface of the grid polysilicon and can reduce a risk that in the subsequent thermal process, boron is promoted to penetrate into the wolfram silicon layer, so that the depletion of the grid polysilicon caused by boron penetration into a WSI (wolfram silicon layer) in the PMOS device technology can be effectively inhibited, and the threshold voltage of the PMOS device is stable.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to the method that grid polycrystalline silicon in a kind of inhibition PMOS technique exhausts (Poly Depletion Effects).
Background technology
In existing technique, integrated in order to be convenient to nmos device, the grid polycrystalline silicon of PMOS device adopts the doping condition identical with the grid polycrystalline silicon of nmos device, be all that N-type is adulterated and all requires heavy doping, after the grid polycrystalline silicon N-type doping of PMOS device, must form in channel region a P type buried channel (buried channel) and could solve the higher problem of threshold voltage (Vt) that N-type grid polycrystalline silicon causes, the introducing of P type buried channel can produce larger leakage problem again.In order to solve the problem of higher Vt that the buried channel of existing PMOS device causes and larger leakage current, available technology adopting P type boron impurity carries out the doping of P type to the grid polycrystalline silicon of PMOS device and is heavy doping, the grid polycrystalline silicon that is nmos device forms the structure of N-type doping, the grid polycrystalline silicon of PMOS device forms the structure of P type doping, could reduce like this P type grid polycrystalline silicon of PMOS device and the contact gesture between the channel region on silicon substrate, can reach and reduce the threshold voltage of PMOS device and the effect of electric leakage.But because nmos device and PMOS device will integrate, therefore guarantee the grid of nmos device and the grid of PMOS device, can realize good contacting, owing to having contact problems between P type grid polycrystalline silicon and N-type grid polycrystalline silicon, so available technology adopting all forms respectively tungsten silicon layer (WSI, Tungsten Polycide) and realizes the good contact of the grid of nmos device and the grid of PMOS device and be connected on P type grid polycrystalline silicon and N-type grid polycrystalline silicon.
The grid polycrystalline silicon of PMOS device adopts boron doping and forms after tungsten silicon layer, because boron solubility in tungsten silicon layer and polysilicon is roughly 100:1, the easy like this impact that is subject to subsequent heat treatment, cause boron to pass through the interface of tungsten silicon layer and grid polycrystalline silicon, enter into tungsten silicon layer and build up at tungsten silicon layer, the grid polycrystalline silicon that finally can produce PMOS device exhausts (Poly Depletion Effects), thereby causes the threshold voltage shift of PMOS device.As shown in Figure 1, on silicon substrate 101, be formed with gate oxide 102, and gate polysilicon layer 103 and tungsten silicon layer 104, wherein in gate polysilicon layer 103, be injected with P type boron impurity, this structure is after carrying out subsequent heat treatment, because the solubility in tungsten silicon layer 104 of boron is larger, therefore boron impurity can be penetrated in tungsten silicon layer 104, the boron impurity of gate polysilicon layer 103 can greatly reduce, and will be the threshold voltage shift of the last PMOS device forming like this.
In order to overcome above-mentioned boron penetration, to the situation in tungsten silicon layer, occur; as shown in Figure 2; existing a kind of process is to carry out after boron doping at gate polysilicon layer 103; on the surface of gate polysilicon layer 103, form the barrier layer 105 of one deck titanium and titanium nitride (Ti/TiN); on barrier layer 105, form tungsten silicon layer 104, wherein the silicon nitride layer on tungsten silicon layer 104 106 is isolated protective layer again.Be that existing method utilizes barrier layer 105 to stop the boron impurity in grid polycrystalline silicon 103 in tungsten silicon layer 104, to permeate gathering after heating.Although said method can suppressor grid depletion of polysilicon occur, but the new titanium of introducing be easy to follow-up grid polycrystalline silicon to reoxidize (Re-oxidation) technique oxidized and expand, finally cause hemisphere jut (pilling), this can be very large on the pattern impact of grid structure, is unfavorable for the stable performance of device.Meanwhile,, also there is the risk of metal ion pollution in the introducing of titanium to the product in processing line.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of method that in the PMOS of inhibition device technology, grid polycrystalline silicon exhausts, and can suppress boron penetration in the grid polycrystalline silicon of PMOS device in tungsten silicon layer, makes the threshold voltage of PMOS device stable.
For solving the problems of the technologies described above, the method that in inhibition PMOS device technology provided by the invention, grid polycrystalline silicon exhausts comprises the steps:
The surface of step 3, the described grid polycrystalline silicon after nitrogen Implantation forms tungsten silicon layer, consists of the grid of described PMOS device described tungsten silicon layer and described grid polycrystalline silicon.
Further improvement is, the energy of the B Implanted ion in step 1 is 3KeV～8Kev, and implantation dosage is 1E15cm
-2～1E16cm
-2.
Further improvement is, the energy of the injecting nitrogen ion in step 2 is 5KeV～20KeV, and implantation dosage is 5E14cm
-2～4E15cm
-2.
After the inventive method is injected by the grid polycrystalline silicon boron at PMOS device, carry out again nitrogen Implantation, can form on grid polycrystalline silicon surface the nitride film of one deck densification, this nitride film can stop boron to the diffusion into the surface of grid polycrystalline silicon, can be reduced in subsequent thermal process impels boron to be penetrated into the risk in tungsten silicon layer, thereby can effectively suppress in PMOS device technology boron penetration in WSI layer and the grid polycrystalline silicon causing exhausts the generation of phenomenon, make the threshold voltage of PMOS device stable.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is that existing PMOS device is with the grid structure of tungsten silicon layer and polysilicon layer;
Fig. 2 is that existing PMOS device is with the grid structure of tungsten silicon layer, barrier layer and polysilicon layer;
Fig. 3 is the flow chart of embodiment of the present invention method;
Fig. 4 A-Fig. 4 C is device architecture figure in each step of embodiment of the present invention method.
Embodiment
As shown in Figure 3, be the flow chart of embodiment of the present invention method; The embodiment of the present invention suppresses the method that in PMOS device technology, grid polycrystalline silicon exhausts and comprises the steps:
In the side of the grid of PMOS device, form side wall afterwards, and in the described silicon substrate 1 of described grid both sides, form the source-drain area of PMOS device.
General and the nmos device of PMOS device integrates formation, and in forming the region of nmos device, the grid polycrystalline silicon of nmos device adopts N-type to adulterate, and is also formed with tungsten silicon layer on grid polycrystalline silicon.When PMOS device and nmos device integrate, by tungsten silicon layer, realize the connection of the grid between device.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (3)
1. suppress the method that in PMOS device technology, grid polycrystalline silicon exhausts, it is characterized in that, comprise the steps:
Step 1, on silicon substrate, form after grid polycrystalline silicon, B Implanted ion in described grid polycrystalline silicon, makes described grid polycrystalline silicon be P type doped structure;
Step 2, after boron Implantation, on described grid polycrystalline silicon surface, carry out nitrogen Implantation, on described grid polycrystalline silicon surface, form one deck nitride film;
The surface of step 3, the described grid polycrystalline silicon after nitrogen Implantation forms tungsten silicon layer, consists of the grid of described PMOS device described tungsten silicon layer and described grid polycrystalline silicon.
2. the method that in inhibition PMOS device technology as claimed in claim 1, grid polycrystalline silicon exhausts, is characterized in that: the energy of the B Implanted ion in step 1 is 3KeV～8KeV, implantation dosage is 1E15cm
-2～1E16cm
-2.
3. the method that in inhibition PMOS device technology as claimed in claim 1, grid polycrystalline silicon exhausts, is characterized in that: the energy of the injecting nitrogen ion in step 2 is 5KeV～20KeV, implantation dosage is 5E14cm
-2～4E15cm
-2.
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| CN103681334B CN103681334B (en) | 2017-03-29 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5648673A (en) * | 1994-12-28 | 1997-07-15 | Nippon Steel Corporation | Semiconductor device having metal silicide film on impurity diffused layer or conductive layer |
| US5846871A (en) * | 1997-08-26 | 1998-12-08 | Lucent Technologies Inc. | Integrated circuit fabrication |
| KR20070079802A (en) * | 2006-02-03 | 2007-08-08 | 주식회사 하이닉스반도체 | Method for forming transistor of semiconductor device |
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2012
- 2012-09-12 CN CN201210337223.8A patent/CN103681334B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5648673A (en) * | 1994-12-28 | 1997-07-15 | Nippon Steel Corporation | Semiconductor device having metal silicide film on impurity diffused layer or conductive layer |
| US5846871A (en) * | 1997-08-26 | 1998-12-08 | Lucent Technologies Inc. | Integrated circuit fabrication |
| KR20070079802A (en) * | 2006-02-03 | 2007-08-08 | 주식회사 하이닉스반도체 | Method for forming transistor of semiconductor device |
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| CN103681334B (en) | 2017-03-29 |
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