CN103678245B - Low-power-consumption on-chip network task mapping method - Google Patents
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Abstract
The invention discloses a low-power-consumption on-chip network task mapping method. The low-power-consumption on-chip network task mapping method comprises the following steps of S10, building an on-chip network topology model, S11, building a multi-task model, S12, determining constraint conditions, S13, setting up a mapping set, and S14, carrying out mapping between tasks and an on-chip network. According to the low-power-consumption on-chip network task mapping method, due to the facts that the model is built for the tasks in the on-chip network, the relation among the tasks is analyzed, and then the tasks are mapped through dual constraint conditions including communication delay and energy consumption, mapping efficiency is improved, and power consumption of mapping is reduced.
Description
Technical field
The invention belongs to network-on-chip technical field, is related to a kind of network-on-chip duty mapping method of low-power consumption.
Background technology
As the dominant frequency of general processor breaks through 4GHz, it has been found that the way of single lifting dominant frequency can not be effective again
Ground improves performance, but brings rising sharply for power consumption on the contrary, and high-frequency road has gradually gone to the end.Then for calculating
The research of machine processor starts the direction for turning to multiprocessing core.The symmetric multiprocessor (SMP) of early stage is utilized in same more
Collect the mode of one group of CPU on computer, shared drive subsystem and bus structures between them.Afterwards, due to nanoscale
The introducing of manufacturing process, SMP start to be changed into chip multiprocessors (Chip Multiprocessor, CMP), i.e., same
Integrated multiple processing cores on chip, define the polycaryon processor now described in us.The structural relation of processor itself is arrived
The area of whole chip, power consumption and performance.The achievement for how inheriting and developing conventional processors directly influences polycaryon processor
Performance and performance period.
Between the program that each process cores of polycaryon processor are performed sometimes for carry out data sharing with it is synchronous, therefore which is hard
Part structure must support intercore communication.Efficient communication mechanism is the high performance important leverage of polycaryon processor.It is high on piece at present
Effect communication mechanism generally has two kinds：Based on the cache structures of shared bus, the interconnection structure based on network-on-chip.Based on shared
The cache structures of bus refer to that each process cores possesses shared two grade or three-level cache, for preserving the more commonly used number
According to, and communicated by bus.The advantage of this system is simple structure, and communication speed is fast；Have the disadvantage poor expandability.
Shared bus obviously cannot meet the needs of large scale system.Interference networks are used for system-on-chip designs, are solved
Communication on piece between component, here it is network-on-chip.Network-on-chip (- Network On Chip, NoC) technology is with which
The features such as support is accessed simultaneously, reliability is high, reusability is high is considered as more preferable CMP interconnection techniques on a large scale, its
The shortcoming of bus structures poor expandability is overcome, and a kind of feasible SOC(system on a chip) communication device is provided for 1,000,000,000 transistor epoch
System.
In network-on-chip, how will be very important problem on the processor core of duty mapping to network-on-chip.One
Aspect needs to meet the constraint of the communication delay between task；On the other hand, due in network-on-chip communication energy consumption it is higher, need
Communication energy consumption is reduced as far as possible.Existing mapping method often adopts complicated method to be mapped, and needs to expend a large amount of
Time carrying out the calculating of mapping process, this also increases energy consumption to a certain extent.
The content of the invention
To solve the above problems, it is an object of the invention to provide a kind of network-on-chip duty mapping method of low-power consumption.
For achieving the above object, the technical scheme is that：
A kind of network-on-chip duty mapping method of low-power consumption, comprises the steps：
S10：Set up network-on-chip topological model；
S11：Set up multi task model；
S12：Determine constraints, specifically include：
To task T in set of tasks TmAnd Tn, it is respectively mapped to the processor core C of network-on-chipiAnd Cj, meet communication and prolong
Slow constraints is：
Lij≤L(qmn)
Wherein, LijRepresent from processor core CiTo processor core CjDelay, L (qmn) represent task TmAnd TnBetween it is logical
Letter postpones to require；
Also, after all tasks are mapped to network-on-chip, the energy that communicates between all mapped processor cores to be made
Consumption E=Σ wij*EijIt is minimum；
S13：Set up mapping set；
S14：The mapping between task and network-on-chip is carried out, is specifically included：
S140：To set of tasks T, descending sort is carried out according to the f values of task, if the f of two or more tasks
Value is identical, then be ranked up according to the W values of task, and the expression of the f values of the task and the task have other of correspondence
The quantity of business, the communication bandwidth between W value expression tasks；After sequence new set of tasks be T ', T and T ' between corresponding relation
For Map (T ← → T ')；
S141：To processor core set C, descending sort, the process are carried out to processor core according to the h values of processor core
The h values of device core represent the quantity of the processor core that the processor core is directly connected in all directions；New set of tasks after sequence
For C ', C and C ' between corresponding relation be Map (C ← → C ')；
S142：First task T is taken out from T '0', there is maximum h values in mapping that to all processor cores
Processor core Cx' on, and by (T0’,Cx') be added in G；
S143：First non-mapped task T is taken out from T 'm', for T (Tm') in mapped task be located
Processor core, calculate Tm' all E for being mapped on the non-mapped processor core being directly connected in these processor cores
Value, removes the E values of the constraints for being unsatisfactory for postponing according to formula in step S12；It is identical if two or more
E values, then take min (E) for processor core and number minimum processor core Cmin' E values, represented in all E values using min (E)
Minimum E values；Calculate Tm' it is mapped to Cmin' on after, calculate Cmin' and the delay of processor core that communicates with, if met
The constraints of delay, is mapped, by (Tm’,Cmin') be added in G；If being unsatisfactory for the constraints for postponing, going
Fall current min (E) all E it is worthwhile in pick up new min (E)；The constraints for postponing is met until finding
Cmin', mapped, by (Tm’,Cmin') be added in G；If T is (Tm') in there is no mapped task, then from C '
Select first non-mapped processor core Ck' mapped, by (Tm’,Ck') be added in G；
S144：Repeat step S143, until all of task is mapped on network-on-chip；
S145：All of mapping in G is corresponded to by C and T according to corresponding relation Map (T ← → T ') and Map (C ← → C ')
On.
Further, in step S14, to set of tasks T, descending sort is carried out according to the f values of task, if two or two
The f values of individual above task are identical, then be ranked up according to the W values of task, and the f values of the task are represented to be existed with the task and communicated
The quantity of other tasks of relation, the communication bandwidth between W value expression tasks.
Further, in step S14, to processor core set C, processor core is dropped according to the h values of processor core
Sequence sorts, and the h values of the processor core represent the quantity of the processor core that the processor core is directly connected in all directions.
Further, in step S14, first task T0 is taken out from set of tasks ', map that to all processors
Processor core with maximum h values in core.
Compared to prior art, a kind of network-on-chip duty mapping method of low-power consumption of the invention is for more in network-on-chip
Task creation model, analyzes the relation between multitask, then task is carried out under the double constraints of communication delay and energy consumption
Mapping, so as to improve mapping efficiency, reduces mapping power consumption.
Description of the drawings
Fig. 1 is method of the present invention flow process diagram.
Fig. 2 is the schematic diagram of the network-on-chip that one embodiment of the invention has 9 processor cores.
Fig. 3 is one embodiment of the invention for the multi task model correspondence figure of 6 tasks.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, it is below in conjunction with drawings and Examples, right
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, and
It is not used in the restriction present invention.
As shown in figure 1, a kind of network-on-chip duty mapping method of low-power consumption of the invention comprises the steps：
S10：Set up network-on-chip topological model
For network-on-chip, represent that wherein C is processor core C with N (C, P)nSet, P is path PijSet；Its
In, PijRepresent from processor core CiTo processor core CjA path.And s=| Ci→Cj| represent from processor core CiEverywhere
Reason device core CjThe quantity of the network-on-chip router for being passed through；EbitRepresent that 1bit data are entered between two adjacent processor core
Average energy consumption during row transmission；ErAverage energy consumption when representing that 1bit data are passed through on network-on-chip router；LbitRepresent
Average retardation when 1bit data are transmitted between two adjacent processor core；LrRepresent 1bit data on network-on-chip road
By average retardation when passing through on device；h(Ci) represent processor core CiThe quantity of the processor core being directly connected in all directions；C
(Cj) represent and processor core CiSet with the processor core being directly connected to.
Then from processor core CiTo processor core CjEnergy consumption EijFor：
Eij=(s+1) * Ebit+s*Er (1)
From processor core CiTo processor core CjDelay LijFor：
Lij=(s+1) * Lbit+s*Lr (2)
S11：Set up multi task model
For multiple tasks set up multi task model, represent that wherein T is task T with U (T, Q)mSet；Q is qmnCollection
Close, qmnExpression task TmAnd TnBetween there is correspondence；And L (qmn) represent task TmAnd TnBetween communication delay require；
fmRepresent and task TmThere is the quantity of other tasks of correspondence；wijExpression task TmAnd TnBetween communication bandwidth；T
(Tm) represent all and task TmThe set of the task with correspondence；W(Tm) represent task TmTotal communication bandwidth.
S12：Determine constraints
To task T in TmAnd Tn, it is respectively mapped to the processor core C of network-on-chipiAnd Cj, meet the constraint of communication delay
Condition is：
Lij≤L(qmn) (3)
After all tasks are mapped to network-on-chip, between all mapped processor cores, communication energy consumption is：
E=Σ wij*Eij (4)
Then to be made the communication energy consumption between the processor core after mapping minimum, i.e., E will be made minimum；
S13：Set up mapping set
For the mapping that will be carried out, mapping set G is set up, be now empty in G, be original state；
S14：Carry out the mapping between task and network-on-chip
S140：To set of tasks T, descending sort is carried out according to the f values of task, if the f of two or more tasks
Value is identical, then be ranked up according to the W values of task；After sequence new set of tasks be T ', T and T ' between corresponding relation be
Map(T←→T’)；
S141：To processor core set C, descending sort is carried out to processor core according to the h values of processor core；It is new after sequence
Set of tasks be C ', C and C ' between corresponding relation be Map (C ← → C ')；
S142：First task T is taken out from T '0', there is maximum h values in mapping that to all processor cores
Processor core Cx' on, and by (T0’,Cx') be added in G；
S143：First non-mapped task T is taken out from T 'm', for T (Tm') in mapped task be located
Processor core, calculate Tm' all E for being mapped on the non-mapped processor core being directly connected in these processor cores
Value, removes the E values of the constraints for being unsatisfactory for postponing according to formula (3)；If two or more identical E values,
Then take min (E) minimum processor core C is numbered for processor coremin' E values, represent in all E values minimum using min (E)
E values；Calculate Tm' it is mapped to Cmin' on after, calculate Cmin' and the delay of processor core that communicates with, if meeting what is postponed
Constraints, is mapped, by (Tm’,Cmin') be added in G；It is if being unsatisfactory for the constraints for postponing, current removing
Min (E) all E it is worthwhile in pick up new min (E)；Until finding the C for meeting the constraints for postponingmin', carry out
Mapping, by (Tm’,Cmin') be added in G；If T is (Tm') in there is no mapped task, then select first from the C '
Non-mapped processor core Ck' mapped, by (Tm’,Ck') be added in G；
S144：Repeat step S143, until all of task is mapped on network-on-chip；
S145：All of mapping in G is corresponded to by C and T according to corresponding relation Map (T ← → T ') and Map (C ← → C ')
On.
In the present invention, it is directly that model is set up in network-on-chip and multitask, is mapped in the way of more brief,
The complexity of mapping method is reduced, the speed of mapping is improve；And pass through the relation between task, carry out task on piece
Mapping in network so that the communication delay between task greatly reduces, so as to effectively reduce the energy consumption of network-on-chip.This
Invention suitable for the duty mapping towards network-on-chip, the delay with network-on-chip as constraints, using low-power consumption as task
Important parameter during mapping, had both met requirement of the network-on-chip to communication delay, taken into account again communication when power consumption, so as to
In the case of ensureing communication efficiency, the power consumption of network-on-chip is reduced.
Specifically, in step S10, illustrate by taking the network-on-chip with 9 processor cores as an example.For with 9
The network-on-chip of processor core, is represented by N (C, P), in wherein processor core set C is：C0,C1,C2,C3,C4,C5,C6,C7,
C8；And P is as shown in Fig. 2 can be communicated by line between processor core.All of s is as shown in the table：
| s | C0 | C1 | C2 | C3 | C4 | C5 | C6 | C7 | C8 |
| C0 | / | 0 | 1 | 0 | 1 | 2 | 1 | 2 | 3 |
| C1 | 0 | / | 0 | 1 | 0 | 1 | 2 | 1 | 2 |
| C2 | 1 | 0 | / | 2 | 1 | 0 | 3 | 2 | 1 |
| C3 | 0 | 1 | 2 | / | 0 | 1 | 0 | 1 | 2 |
| C4 | 1 | 0 | 1 | 0 | / | 0 | 1 | 0 | 1 |
| C5 | 2 | 1 | 0 | 1 | 0 | / | 2 | 1 | 0 |
| C6 | 1 | 2 | 3 | 0 | 1 | 2 | / | 0 | 1 |
| C7 | 2 | 1 | 2 | 1 | 0 | 1 | 0 | / | 0 |
| C8 | 3 | 2 | 1 | 2 | 1 | 0 | 1 | 0 | / |
Table 1
In table 1, "/" represents not this value, such as：C0And C0Between do not exist using router connect situation.Then：
Ebit=1；Er=2；Lbit=1；Lr=2；H values are as shown in the table：
| C0 | C1 | C2 | C3 | C4 | C5 | C6 | C7 | C8 | |
| h | 2 | 3 | 2 | 2 | 4 | 3 | 2 | 3 | 2 |
Table 2
All of C (Cj) as shown in the table：
Table 3
Power consumption values are as shown in the table：
| Eij | C0 | C1 | C2 | C3 | C4 | C5 | C6 | C7 | C8 |
| C0 | / | 1 | 4 | 1 | 4 | 7 | 4 | 7 | 10 |
| C1 | 1 | / | 1 | 4 | 1 | 4 | 7 | 4 | 7 |
| C2 | 4 | 1 | / | 2 | 4 | 1 | 10 | 7 | 4 |
| C3 | 1 | 4 | 7 | / | 1 | 4 | 1 | 4 | 7 |
| C4 | 4 | 1 | 4 | 1 | / | 1 | 4 | 1 | 4 |
| C5 | 7 | 4 | 1 | 4 | 1 | / | 7 | 4 | 1 |
| C6 | 4 | 7 | 10 | 1 | 4 | 2 | / | 1 | 4 |
| C7 | 7 | 4 | 7 | 4 | 1 | 4 | 1 | / | 1 |
| C8 | 10 | 7 | 4 | 7 | 4 | 1 | 4 | 1 | / |
Table 4
Postpone LijIt is as shown in the table：
Table 5
In step S11, illustrate by taking 6 tasks as an example, for 6 tasks, set up multi task model U (T, Q), wherein
T is：T0,T1,T2,T3,T4,T5；Correspondence is as shown in Figure 3.
Communication delay requires as shown in the table：
| L(qmn) | T0 | T1 | T2 | T3 | T4 | T5 |
| T0 | / | 2 | 3 | 3 | 3 | 4 |
| T1 | 2 | / | 1 | 2 | 3 | 3 |
| T2 | 3 | 1 | / | 3 | 2 | 2 |
| T3 | 3 | 2 | 3 | / | 2 | 3 |
| T4 | 3 | 3 | 2 | 2 | / | 3 |
| T5 | 4 | 3 | 2 | 3 | 3 | / |
Table 6
F values are as shown in the table：
| T0 | T1 | T2 | T3 | T4 | T5 | |
| f | 3 | 2 | 1 | 2 | 1 | 3 |
Table 7
Wherein, the numerical value in w values such as Fig. 3 on line.
T(Tm) as shown in the table：
Table 8
W(Tm) as shown in the table：
| T0 | T1 | T2 | T3 | T4 | T5 | |
| W(Tm) | 8 | 7 | 2 | 5 | 2 | 10 |
Table 9
Then for the network-on-chip with 9 cores and 6 tasks to be mapped, there is following process：
(1) to T={ T0,T1,T2,T3,T4,T5, ranking results are { T5,T0,T1,T3,T2,T4, then T '={ T0’,T1’,
T2’,T3’,T4’,T5’}.Corresponding relation between T and T ' is that Map (T ← → T ') is as shown in the table：
| T | T0 | T1 | T2 | T3 | T4 | T5 |
| T’ | T1’ | T2’ | T4’ | T3’ | T5’ | T0’ |
(2) C={ C0,C1,C2,C3,C4,C5,C6,C7,C8, it is { C after sequence4,C1,C5,C7,C0,C2,C3,C6,C8}；C’
={ C0’,C1’,C2’,C3’,C4’,C5’,C6’,C7’,C8', the corresponding relation between C and C ' is Map (C ← → C ') such as following table
It is shown：
| C | C0 | C1 | C2 | C3 | C4 | C5 | C6 | C7 | C8 |
| C’ | C4’ | C1’ | C5’ | C6’ | C0’ | C2’ | C7’ | C3’ | C8’ |
(3) first task T of taking-up from T '0', there is in mapping that to all processor cores the place of maximum h values
Reason device core C0' on, and by (T0’,C0') be added in G；Now G={ (T0’,C0’)}；
(4) first non-mapped task is taken out from T ', be T1', T (T1') in the place that is located of mapped task
Reason device core is C0’；
Calculate T1' it is mapped to C0' on the non-mapped processor core being directly connected on all E values, the place that can be mapped
Reason device core has four, respectively C1', C2', C3', C6’；E values are respectively：
It is mapped to C1’：1
It is mapped to C2’：1
It is mapped to C3’：1
It is mapped to C6’：1
As E values are equal, then the minimum C of processor core numbering is taken1', calculate C1' to C0' communication delay be 1, it is full
The constraints that foot postpones；By (T1’,C1') be added in G, now G={ (T0’,C0’),(T1’,C1’)}；
First non-mapped task is taken out from T ' again, is T2', T (T2') middle endlessly mapped task；Then from C '
First non-mapped processor core of middle selection is C2', by (T2’,C2') be added in G；Now G={ (T0’,C0’),
(T1’,C1’),(T2’,C2’)}；
First non-mapped task is taken out from T ' again, is T3', T (T3') in the place that is located of mapped task
Reason device core is C0’；C0' be directly connected to and non-mapped processor core be C3', C4', C5' and C6’；E values are respectively：
It is mapped to C3’：5
It is mapped to C4’：5
It is mapped to C5’：5
It is mapped to C6’：5
As E values are equal, then the minimum C of processor core numbering is taken3', calculate C3' to C0' communication delay be 1,
C3' to C1' communication delay be 4, meet postpone constraints；By (T3’,C3') be added in G, now G={ (T0’,
C0’),(T1’,C1’),(T2’,C2’),(T3’,C3’)}；
First non-mapped task is taken out from T ' again, is T4', T (T4') in the place that is located of mapped task
Reason device core is C2’；C2' be directly connected to and non-mapped processor core be C5' and C8’；E values are respectively：
It is mapped to C5’：1
It is mapped to C8’：1
As E values are equal, then the minimum C of processor core numbering is taken5', calculate C5' to C2' communication delay be 1, it is full
The constraints that foot postpones, by (T4’,C5') be added in G；Now G={ (T0’,C0’),(T1’,C1’),(T2’,C2’),
(T3’,C3’),(T4’,C5’)}；
First non-mapped task is taken out from T ' again, is T5', T (T5') in the place that is located of mapped task
Reason device core is C0' and C1’；C0' and C1' be directly connected to and non-mapped processor core be C4' and C6’；E values are respectively：
It is mapped to C4’：5
It is mapped to C6’：5
As E values are equal, then the minimum C of processor core numbering is taken4', calculate C4' to C1' communication delay be 1, meter
Calculate C4' to C0' communication delay be 4, meet postpone constraints, by (T4’,C4') be added in G；Now G={ (T0’,
C0’),(T1’,C1’),(T2’,C2’),(T3’,C3’),(T4’,C4’)}；
First non-mapped task is taken out from T ' again, is T5', T (T5') in the place that is located of mapped task
Reason device core is C0' and C4’；C0' and C4' be directly connected to and non-mapped processor core be C6’；E values are：
It is mapped to C6’：5
Now, calculate C6' to C4' communication delay be 1, calculate C6' to C1' communication delay be 4, meet
The constraints of delay, by (T5’,C6') be added in G；Now G={ (T0’,C0’),(T1’,C1’),(T2’,C2’),(T3’,
C3’),(T4’,C4’),(T5’,C6’)}；
(6) all of mapping in G is corresponded on C and T according to corresponding relation Map (T ← → T ') and Map (C ← → C '),
It is then：
G={ (T5,C4),(T0,C1),(T1,C5),(T3,C7),(T2,C0),(T4,C3)}
Communication delay between task as constraints, had both been met network-on-chip to communication by this specific embodiment
The requirement of delay, has taken into account power consumption during communication again, so as in the case where communication efficiency is ensured, realize towards network-on-chip
Low-power consumption duty mapping..
Presently preferred embodiments of the present invention is the foregoing is only, not to limit the present invention, all essences in the present invention
Any modification, equivalent and improvement made within god and principle etc., should be included within the scope of the present invention.
Claims (1)
1. a kind of network-on-chip duty mapping method of low-power consumption, it is characterised in that comprise the steps：
S10：Set up network-on-chip topological model；
S11：Set up multi task model；
S12：Determine constraints, specifically include：
To task T in set of tasks TmAnd Tn, it is respectively mapped to the processor core C of network-on-chipiAnd Cj, meet the pact of communication delay
Beam condition is：
Lij≤L(qmn)
Wherein, LijRepresent from processor core CiTo processor core CjDelay, L (qmn) represent task TmAnd TnBetween communication prolong
Require late；
Also, after all tasks are mapped to network-on-chip, communication energy consumption E=between all mapped processor cores to be made
Σwij*EijMinimum, wherein wijExpression task TmAnd TnBetween communication bandwidth, EijRepresent from processor core CiTo processor core Cj
Energy consumption；
S13：Set up mapping set G；
S14：The mapping between task and network-on-chip is carried out, is specifically included：
S140：To set of tasks T, descending sort is carried out according to the f values of task, if the f value phases of two or more tasks
Together, then it is ranked up according to the W values of task, the f values of the task represent other tasks that there is correspondence with the task
Quantity, the communication bandwidth between W value expression tasks；After sequence new set of tasks be T ', T and T ' between corresponding relation be
Map(T←→T’)；
S141：To processor core set C, descending sort, the processor core are carried out to processor core according to the h values of processor core
H values represent the quantity of processor core that the processor core is directly connected in all directions；After sequence, new set of tasks is C ',
Corresponding relation between C and C ' is Map (C ← → C ')；
S142：First task T is taken out from T '0', there is in mapping that to all processor cores the processor of maximum h values
Core Cx' on, and by (T0’,Cx') be added in G；
S143：First non-mapped task T is taken out from T 'm', for T (Tm') in the place that is located of mapped task
Reason device core, calculates Tm' all E values for being mapped on the non-mapped processor core being directly connected in these processor cores,
Remove the E values of the constraints for being unsatisfactory for postponing according to formula in step S12；If two or more identicals E
Value, then take min (E) for processor core and number minimum processor core Cmin' E values, represented in all E values most using min (E)
Little E values；Calculate Tm' it is mapped to Cmin' on after, calculate Cmin' and the delay of processor core that communicates with, if meet prolonged
Slow constraints, is mapped, by (Tm’,Cmin') be added in G；If being unsatisfactory for the constraints for postponing, removing
New min (E) is picked up during all E of current min (E) are worthwhile；Until finding the C for meeting the constraints for postponingmin',
Mapped, by (Tm’,Cmin') be added in G；If T is (Tm') in there is no mapped task, then the is selected from the C '
One non-mapped processor core Ck' mapped, by (Tm’,Ck') be added in G；
S144：Repeat step S143, until all of task is mapped on network-on-chip；
S145：All of mapping in G is corresponded on C and T according to corresponding relation Map (T ← → T ') and Map (C ← → C ').
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