CN103650108B - Layered semiconductor substrate and manufacture method thereof - Google Patents
Layered semiconductor substrate and manufacture method thereof Download PDFInfo
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- CN103650108B CN103650108B CN201280032405.2A CN201280032405A CN103650108B CN 103650108 B CN103650108 B CN 103650108B CN 201280032405 A CN201280032405 A CN 201280032405A CN 103650108 B CN103650108 B CN 103650108B
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- 239000000758 substrate Substances 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 239000002019 doping agent Substances 0.000 claims abstract description 76
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 44
- 239000010703 silicon Substances 0.000 claims abstract description 44
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 42
- 239000000203 mixture Substances 0.000 claims description 8
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052787 antimony Inorganic materials 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 230000003247 decreasing Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 123
- JMASRVWKEDWRBT-UHFFFAOYSA-N gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 23
- 229910052782 aluminium Inorganic materials 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminum Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 239000000126 substance Substances 0.000 description 8
- TWXTWZIUMCFMSG-UHFFFAOYSA-N nitride(3-) Chemical compound [N-3] TWXTWZIUMCFMSG-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 230000001419 dependent Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000007792 addition Methods 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 2
- 229910052986 germanium hydride Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000000737 periodic Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- IEXRMSFAVATTJX-UHFFFAOYSA-N tetrachlorogermane Chemical compound Cl[Ge](Cl)(Cl)Cl IEXRMSFAVATTJX-UHFFFAOYSA-N 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N Trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N Trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N Trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 230000003042 antagnostic Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000630 rising Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Abstract
The present invention relates to layered semiconductor substrate, it includes the ground floor (1) of monocrystalline, and it contains the silicon of at least 80%, and has the first thickness and the first lattice paprmeter (a1), described first lattice paprmeter (a1) determined by the first dopant element and the first concentration of dopant, and the second layer (2) of monocrystalline, it contains the silicon of at least 80%, and has the second thickness and the second lattice paprmeter (a2), described second lattice paprmeter (a2) determined by the second dopant element and the second concentration of dopant, the described second layer (2) directly contacts with described ground floor, third layer (4) with monocrystalline, it comprises group III-nitride, make the described second layer between described ground floor and described third layer, wherein said second lattice paprmeter (a2) more than described first lattice paprmeter (a1), the lattice of wherein said ground floor (1) and the described second layer (2) is Lattice Matching, and the arch of wherein said layered semiconductor substrate is in the range of 50 μm to 50 μm.The method that the invention still further relates to manufacture this layered semiconductor substrate.
Description
The present invention relates to layered semiconductor substrate based on silicon, further relate to manufacture the method for this substrate, institute
State the substrate that layered semiconductor substrate is used as the deposition of Ill-nitride layer.
Owing to the material between GaN and Si (111) does not mates, silicon (Si) substrate (GaN-Si Rotating fields,
GaN is upper) there are some basic problems in gallium nitride (GaN) layer of upper epitaxial deposition.Such as, GaN
Thermal coefficient of expansion (TEC) is more than the thermal coefficient of expansion of silicon.For the nitrogen of other elements of 3 races in periodic chart
There is same problem in compound.During the depositing temperature of Ill-nitride layer is cooled to room temperature,
This difference of thermal coefficient of expansion causes the concave arcuate on a large scale (bow) of wafer.The amount of arch is along with III
The thickness of group iii nitride layer increases and increases.If the arch of wafer is the highest, then can not locate further
Reason.Therefore, it is necessary to keep low arch.
Have been proposed for some solutions.State-of-the-art method is at the GaN layer heap producing compressive stress
Depositing inter-layer in stack, the most at low temperatures cvd nitride aluminum (AlN) intermediate layer.Such as,
US2003/0136333A1 discloses in GaN layer stacking some AlN of internal deposition on a silicon substrate
Interbed.AlN has the lattice paprmeter less than GaN.Therefore, during growing, raw on AlN
Long GaN layer is under pressure.The tension that this pressure compensation cooling period occurs.This makes
Thick and flawless GaN layer can be grown on a silicon substrate.
AlN layer must deposit in a low temperature of causing low rate of growth.Therefore, the deposition right and wrong of AlN layer
The most time-consuming.It addition, the deposition of the GaN layer occurred under the relatively-high temperature of about 1100 DEG C must quilt
Interrupt.Between GaN and AlN deposition step, reduction and the rising of temperature needs the extra time.Enter
The shortcoming of one step is to be created additional stress by AlN intermediate layer in GaN layer, which results in GaN
The increase of defect concentration in Ceng.
It is alternatively possible at the one or more layer of backside deposition of wafer, the one or more layer produces
Raw antagonism is from the arch of the arch contribution of the GaN layer on front wafer surface.US4830984 teaches
Deposit metal (such as tungsten) silicide layer on the back side of silicon substrate wafer and annealed, having convex with formation
The warped structures of front surface.Then, the front of silicon substrate wafer deposits GaAs (GaAs) layer.
When structure is cooled to room temperature, two-layer, the GaAs layer on front and the metal silicide layer on the back side
The opposite face of silicon substrate wafer applies stretching force, result in the almost plane surface of GaAs layer.It is subject to
The deposition of pressure back layer needs to add some processing steps, and (deposition back layer (may invert wafer), etching
Edge and front to remove deposit, extra polishing front), these add processing steps add
The complexity manufactured and cost.It addition, the non-Si back side is the polluter of all further processing steps.
Therefore, technical problem solved by the invention is to provide the high-quality III nitrogen with little arch
Compound layer, preparation institute's time spent of these Ill-nitride layer is fewer than known structure.
This problem is solved by layered semiconductor substrate, and this layered semiconductor substrate includes:
The ground floor 1 of-monocrystalline, it contains the silicon of at least 80%, and has the first thickness and the first crystalline substance
Lattice constant a1, described first lattice paprmeter a1Determined by the first dopant element and the first concentration of dopant,
With
The second layer 2 of-monocrystalline, it contains the silicon of at least 80%, and has the second thickness and the second crystalline substance
Lattice constant a2, described second lattice paprmeter a2Determined by the second dopant element and the second concentration of dopant,
The described second layer 2 directly contacts with described ground floor, and
The third layer 4 of-monocrystalline, it comprises group III-nitride so that the described second layer is positioned at described
Between one layer and described third layer,
Wherein said second lattice paprmeter a2More than described first lattice paprmeter a1, wherein said ground floor
1 and the lattice of the described second layer 2 be Lattice Matching, and the bow of wherein said layered semiconductor substrate
Shape is in the range of-50 μm to 50 μm.
Compared to prior art, the present invention uses the most silica-based layer stack stack, produces stress,
To compensate by the stress that deposited Ill-nitride layer on the substrate is applied.
According to the present invention, relative to described ground floor, the composition of the described second layer of described substrate passes through
Add at least one unit to one of described layer layer usually to change, at the described second layer and described ground floor
Between produce lattice do not mate.Lattice paprmeter with the described second layer is normal more than the lattice of described ground floor
The mode of number comes chosen dopant element and concentration thereof.In this manual, term " lattice paprmeter " should be managed
Solve as the lattice paprmeter of material when lattice loosens.If described material forms the epitaxially deposited layer of pressurized,
As described in the case of the second layer as described in deposition on ground floor 1, actual interior lattice of described material
The lattice paprmeter of described material under constant deviation relaxation state.By regulation described dopant element, institute
State the concentration (hereinafter referred to as " concentration of dopant ") of dopant element and described ground floor and the thickness of the second layer
Degree, produces certain amount of stress, result in the concave arcuate of wafer.The amount of stress foot produced in substrate
Enough counteracting is caused by the Ill-nitride layer being deposited on above the described second layer of described substrate
Stress.
The present invention can also be combined with other technologies and reduce arch, the most above-mentioned prior art or use
Preferential arch on substrate.
It is an advantage of the invention that improve the Ill-nitride layer being deposited on the described second layer quality and
The less process time (i.e. low cost), mend because eliminating the stress being included in GaN epitaxy deposition
Repay layer, and simplify the growth of (Al) GaN cushion.
Better quality produces lacking of layer owing to Ill-nitride layer internal stress.Which reduce III
Defect concentration in nitride layer.Use the Si epitaxy technique of the standard of the high-crystal quality producing layer,
Can easily by described ground floor or described second layer epitaxial deposition on other layers.
Compared to the deposition of stress compensation layer in (Al) GaN cushion, the deposition of doping Si layer has
Higher volume of production (low cost).Therefore, simplify whole technique and reduce manufacturing cost.
The present invention is described in detail below in conjunction with three accompanying drawings.
Fig. 1 schematically depict deposition Ill-nitride layer (not according to the present invention) on a silicon substrate.
The stratiform that Fig. 2 schematically depict before depositing group III-nitride nitride layer according to the present invention is partly led
The midbody product of structure base board.
Fig. 3 schematically depict the layered semiconductor substrate according to the present invention, and it includes first and
Two silicon base layers, intermediate layer and Ill-nitride layer.
Layered semiconductor substrate according to the present invention is constituted by least three layers:
The ground floor 1 of monocrystalline is containing at least 80% and the silicon of preferably at least 90%.(in this manual,
The composition of all of layer is given with atomic percent.) ground floor 1 has the first thickness and the first lattice is normal
Number a1.First lattice paprmeter a1By concentration (this explanation of the first dopant element and the first dopant element
Book is referred to as " the first concentration of dopant ") determine.Crystal lattices orientation is preferably (111).
The second layer 2 of monocrystalline also contains at least 80% and the silicon of preferably at least 90%.It is thick that it has second
Degree and the second lattice paprmeter a2.Second lattice paprmeter a2By the second dopant element and the second adulterant unit
The concentration (being referred to as " the second concentration of dopant " in this specification) of element determines.
The second layer 2 directly contacts with ground floor.There are not other between ground floor 1 and the second layer 2
Layer.The deposition second layer 2 in one way, to form strain epitaxially deposited layer, the reality of the second layer 2
In face, lattice paprmeter matches with lattice paprmeter in the face of ground floor 1.Because the second lattice paprmeter a2Greatly
In the first lattice paprmeter a1, so the second layer 2 strains relative to ground floor 1 compressibility.In deposition the
Arch (the table contrary with ground floor 1 relative to the second layer 2 of concave surface was which results in before three layer 4
Face).Fig. 2 shows this situation.
The third layer 4 (Fig. 3) of monocrystalline (is referred to as in this explanation by the nitride of the group-III element of periodic chart
" group III-nitride ") composition.Aluminium nitride (AlN) in these group III-nitride, gallium nitride (GaN) and
Indium nitride (InN) and mixture thereof are particular importances.Generally, layered semiconductor substrate include one with
Upper Ill-nitride layer (referred to as " third layer 4 ").Preferably, the stacked body of Ill-nitride layer starts
In AlN layer, with chemical isolation silicon based substrate, prepare the growth of two-dimensional layer and by lattice paprmeter from second
Lattice paprmeter a of layer2The lattice paprmeter of regulation extremely uppermost Ill-nitride layer.It is highly preferred that
Ill-nitride layer above is made up of GaN.
In the layered semiconductor substrate according to the present invention, the second layer 2 is positioned at ground floor 1 and third layer 4
Between.Third layer 4 directly can contact with the second layer 2.However, it is also possible to by one or more
Interbed 3 is placed between the second layer 2 and third layer 3.
Layered semiconductor structure according to the present invention preferably has the shape of Circular wafer.
The mutually compensating for, such as ASTM F5343.1.2 of strain due to ground floor, the second layer and third layer
Limited like that with SEMI MF534, the arch of layered semiconductor substrate from-50 μm to 50 μm
In the range of.As explained above, the thermal coefficient of expansion (TEC) of Ill-nitride layer is more than the thermal expansion of silicon
Coefficient.Therefore, when at high temperature on silicon substrate 5 epitaxial deposition Ill-nitride layer 4 (Fig. 1) and
When being then cooled to room temperature, GaN layer 4 shrink than silicon substrate more than 5.Which results in and have such as Fig. 1
The structure of shown sizable concave arcuate.According to the present invention, this arch is (by the GaN layer cooled down
Elongation strain produces) compensated by the reverse strain in silicon based substrate.The knot of silicon based substrate shown in Fig. 2
Structure.Silicon based substrate includes ground floor 1 and the second layer 2 with the first lattice paprmeter, the second layer 2 with
Ground floor 1 directly contacts and its lattice paprmeter is more than the lattice paprmeter of ground floor 1.
In first embodiment of the invention, the first dopant element and the second dopant element are identical,
And only the first concentration of dopant is different with the second concentration of dopant.
In the first embodiment, if the covalency atomic radius of dopant element is less than silicon, then select
First concentration of dopant is higher than the second concentration of dopant.Therefore, the first lattice paprmeter a1Become less than
Two lattice paprmeters a2.Boron (B) is the covalency atomic radius typical dopant element less than silicon, and excellent
It is selected in this situation.Second concentration of dopant can as little as zero, but in this case first doping
Agent concentration have to be larger than zero.
In the first embodiment, if dopant element has bigger covalency atomic radius, then select
Select the second concentration of dopant higher than the first concentration of dopant.Therefore, the first lattice paprmeter a1Again become
Less than the second lattice paprmeter a2.Germanium (Ge) and antimony (Sb) are the typical doping more than silicon of the covalency atomic radius
Agent element, and be optimized in this situation.First concentration of dopant can as little as zero, but
In this situation, the second concentration of dopant have to be larger than zero.
In a second embodiment of the present invention, the first dopant element and the second dopant element are not
Same element.In this case, the covalency atomic radius of the first dopant element is less than silicon, and the
The covalency atomic radius of two dopant elements is more than silicon.Preferably, the first dopant element be boron and
Second dopant element is germanium or antimony.
Required dependent variable (result in the silicon based substrate i.e. concave surface of the stacked body of ground floor 1 and the second layer 2
Arch) dependent variable (result in concave arcuate) that caused by intermediate layer 3 (if present) and third layer 4 is certainly
Fixed.The amount of this concave arcuate and then by the thickness of layer 3 and 4, lattice paprmeter and TEC (and therefore
By forming) determine.Similarly, the concave arcuate amount of the stacked body of ground floor 1 and the second layer 2 depends on
The thickness of layer 1 and 2 and lattice paprmeter (and being accordingly dependent on composition).Therefore, ground floor 1 He is selected
The thickness of the second layer 2 and lattice paprmeter (and therefore composition), so that in ground floor and the stacking of the second layer
Body causes required dependent variable.The appropriately combined of these parameters can be by simply testing decision.Logical
Cross and properly select these parameters, it is possible to obtain there is the layer of the least arch of-50 μm to 50 μm
Shape semiconductor substrate, preferably-10 μm are to 10 μm.
Such as Frank and Van der Merve (F.C.Frank and J.H.van der Merve, Proc.Roy.
Soc, A198,216 (1949)) first prophesy as, when thickness exceedes the given difference in lattice paprmeter
Under critical thickness time, reached the upper limit of the bearing course stacked body generating ground floor 1 and the second layer 2.
For Si (111) Rotating fields, it is impossible to determine critical thickness well, and must test with experiment
Limit, such as by measuring the arch of layer stack stack.Below critical thickness, arch can be changed and intend
It is combined into Stoney and Freund equation and (sees L.B.Freund et
Al.Appl.Phys.Lett.74,1987 (1999)), the Rotating fields final to be prone to optimization.
Layered semiconductor substrate according to the present invention can be manufactured by the method comprised the following steps:
-grow the silicon containing at least 80% and first dopant element with the first concentration of dopant
Monocrystalline, this monocrystalline has the first lattice paprmeter,
-from described monocrystalline, cut (slicing) at least one wafer,
-thickness of described wafer is decreased to the first thickness, wafer constitutes ground floor 1,
-on a surface of wafer the epitaxial deposition second layer 2, and
-epitaxial deposition comprises the third layer 4 of group III-nitride.
In the first step of described method, growth containing at least 80% silicon preferably at least 90%
The monocrystalline of silicon.Preferably, the Czochralski method long crystal in next life known to use.If first mixes
Miscellaneous agent concentration is more than zero, then to be suitable for being incorporated in the silicon single crystal just grown the first concentration of dopant
Concentration, the first dopant element is doped in silicon melt.The monocrystalline of growth has and depends on first
Dopant element and the first lattice paprmeter of the first concentration of dopant.Use Czochralski method, mesh
Before can grow the silicon single crystal of the diameter with maximum 450mm.
In the second step, from monocrystalline, at least one wafer is cut.According to the present invention, the side cut
Method does not has specific restriction.For economic reasons, multi-line cutting machine (MWS) is preferably used, with by monocrystalline
It is cut into multiple wafer simultaneously.
In third step, remove the surface layer of the single-crystal wafer that cut step is destroyed, and by crystalline substance
The thickness of sheet is reduced to the value equal to required first thickness.This is by machinery, chemistry and chemical machinery
The combination of reason step completes.Mechanical treatment step is e.g. ground or grinds.Chemical treatment can be
Liquid phase etching or vapor phase etchant.Polishing is widely used chemical mechanical processing.Final wafer is constituted
The ground floor 1 of layered semiconductor substrate to be formed.
In the 4th step, the second layer 2 extension of the silicon containing at least 80% and preferably at least 90% is sunk
Amass on a surface of ground floor 1.Preferably, chemical gaseous phase deposition (CVD) is used to deposit extension
The second layer.Silicon source gas is preferably trichlorosilane.If the second concentration of dopant is more than zero, then must
Must be under being suitable for being incorporated to the second concentration of dopant the concentration of epitaxial layer just grown, it is provided that adulterant
The additional source gas of element.In the case of the second dopant element is germanium, germanium tetrachloride (GeCl4) or
Germanium tetrahydride (GeH4) it is preferably used as additional source gas.
If it is necessary to can on the surface of the second layer 2 the one or more intermediate layer of epitaxial deposition 3.
In the final step of described method, the second layer 2 surface (or the surface at extra play 3,
If present) upper epitaxial deposition is by group III-nitride (such as AlN, GaN or InN or its mixing
Thing) third layer 4 that constitutes.Can also (and preferably) more than one Ill-nitride layer of continued growth.
Preferably, first by trimethyl aluminium (Al (CH3)3)) and ammonia (NH3) carry out growing AIN seed as presoma
Crystal layer (seed layer).Then, before growth GaN layer, along with the classification AlGaN increasing Ga concentration
Layer is used as transition zone.Generally, trimethyl gallium (Ga (CH3)3)) it is used as presoma, and use mark
Accurate MOCVD reactor completes deposition under the growth temperature between 700 DEG C and 1200 DEG C.
By suitable selection the first dopant element and the second dopant element, the first concentration of dopant
With the second concentration of dopant and the first thickness and the second thickness, it is possible to manufacture and include Ill-nitride layer
Layered semiconductor substrate, it has absolute value is 50 μm or less or even 10 μm or less
Arch.
Described manufacture method can include other step, the most one or more limits making wafer
Step (chamfering, edge polishing), cleaning step, inspection step and the encapsulation step of edge molding.
Layered semiconductor substrate according to the present invention can be used for manufacturing electronic installation (such as merit as substrate
Rate device) or electrooptical device such as light emitting diode (LED).
Claims (8)
1. layered semiconductor substrate, it includes
The wafer of the ground floor (1) of-composition monocrystalline, the ground floor (1) of described monocrystalline is containing at least 80%
Silicon, has (111) crystal lattice orientation, and has the first thickness and the first lattice paprmeter (a1), described first
Lattice paprmeter (a1) determined by the first dopant element and the first concentration of dopant, and
The second layer (2) of-monocrystalline, it contains the silicon of at least 80%, and has the second thickness and second
Lattice paprmeter (a2), described second lattice paprmeter (a2) by the second dopant element and the second concentration of dopant
Determining, the described second layer (2) directly contacts with described ground floor, and
The third layer (4) of-monocrystalline, it is made up of group III-nitride so that the described second layer is positioned at described
Between ground floor and described third layer,
Wherein it is in the described second lattice paprmeter (a of relaxation state2) more than described first lattice paprmeter
(a1), the lattice of wherein said ground floor (1) and the described second layer (2) is Lattice Matching, thus described
The second layer (2) strains, and according to the third layer of monocrystalline, selects described ground floor thickness, the first lattice
Constant (a1), second layer thickness and the second lattice paprmeter (a2), thus the bow of layered semiconductor substrate
Shape in the range of-50 μm to 50 μm, and
Wherein said first dopant element and the second dopant element are identical, and its covalency atomic radius is little
In the covalency atomic radius of silicon, or wherein said first dopant element and the second dopant element are
Antimony, or the covalency atomic radius of wherein said first dopant element is less than the covalency atomic radius of silicon,
And the covalency atomic radius of described second dopant element is more than the covalency atomic radius of silicon.
Layered semiconductor substrate the most according to claim 1, wherein said first dopant element
Covalency atomic radius with the second dopant element is less than the covalency atomic radius of silicon, and wherein said
First concentration of dopant is higher than described second concentration of dopant.
Layered semiconductor substrate the most according to claim 2, wherein said first dopant element
It is boron with the second dopant element.
4. according to the layered semiconductor substrate described in Claims 2 or 3, wherein said second adulterant
Concentration is zero.
Layered semiconductor substrate the most according to claim 1, wherein said first dopant element
It is antimony with the second dopant element, and wherein said second concentration of dopant is higher than described first doping
Agent concentration.
Layered semiconductor substrate the most according to claim 5, wherein said first concentration of dopant
It is zero.
Layered semiconductor substrate the most according to claim 1, wherein said first dopant element
Being boron, described second dopant element is germanium or antimony.
8. for the method that manufactures layered semiconductor substrate according to claim 1, it include with
Lower step:
-grow the silicon containing at least 80% and first dopant element with the first concentration of dopant
Monocrystalline, described monocrystalline has the first lattice paprmeter,
-from described monocrystalline, cut at least one wafer,
-thickness of described wafer is decreased to the first thickness, described wafer constitutes described ground floor (1),
-on a surface of described wafer, extension sinks the described second layer (2), and
The described third layer (4) that-epitaxial deposition is made up of group III-nitride.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP11172250 | 2011-06-30 | ||
| EP11172250.0 | 2011-06-30 | ||
| EP11191535.1 | 2011-12-01 | ||
| EP11191535.1A EP2541589B1 (en) | 2011-06-30 | 2011-12-01 | Layered semiconductor substrate and method for manufacturing it |
| PCT/EP2012/059581 WO2013000636A1 (en) | 2011-06-30 | 2012-05-23 | Layered semiconductor substrate and method for manufacturing it |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103650108A CN103650108A (en) | 2014-03-19 |
| CN103650108B true CN103650108B (en) | 2016-11-30 |
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Citations (1)
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