CN103647265A

CN103647265A - Integrated circuit full-chip electro static discharge protection method and circuit

Info

Publication number: CN103647265A
Application number: CN201310636949.6A
Authority: CN
Inventors: 李志国
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2013-12-03
Filing date: 2013-12-03
Publication date: 2014-03-19

Abstract

The invention is an integrated circuit full-chip electro static discharge (ESD, Electro Static Discharge) protection method. According to an integrated circuit full-chip ESD structure of the method, one power-ground ESD discharge path is added in each signal IO unit, namely, a full chip not only contains an electro static discharge path 102 in a power IO unit, but also contains the electro static discharge path 101 in each signal IO unit. Therefore, the number of the electro static discharge paths in the full chip is increased, the electro static discharge path between IO is shortened, the discharge resistance between IO is reduced, the full-chip electro static discharge efficiency is improved, and the full-chip ESD level is upgraded.

Description

The full chip electro-static discharge guard method of a kind of integrated circuit and circuit

Technical field

This invention is applicable to integrated circuit esd protection design field; the large scale integrated circuit that is particularly useful for multi-pipe pin, is applicable to the esd protection design of the integrated circuit that device architecture is more fragile, inefficacy voltage is lower nanometer technology integrated circuit and ESD have relatively high expectations.

Background technology

Along with integrated circuit (IC:integrated circuit) manufacturing technology level enters deep-submicron epoch, nanometer era in succession, the MOS transistor in integrated circuit all adopts shallow doped structure LDD (Lightly Doped Drain); Silicide is covered on MOS transistor diffusion region; Polycrystalline compounds technique is for reducing the series resistance of grid polycrystalline; And MOS transistor thickness of grid oxide layer is more and more thinner, channel length is more and more less.These improve the integrated level that has all improved chip and the arithmetic speed that improves chip, reduce chip power-consumption, but the static discharge design for deep submicron integrated circuit, but brought very large drawback, because the static environment that integrated circuit faces does not change, but the device reliability that technique progress causes reduces greatly, cause the reliability decrease of integrated circuit (IC) products.The device of manufacturing for deep submicron process, it is withstand voltage about about 25V, for nanometer technology device, it is withstand voltage will drop to below 20V, even below 15V, and seem fragile in the static environment of this kilovolt on hundreds of easily, so the target of ESD design guarantees that high voltage can not appear in integrated circuit (IC)-components two ends exactly.

Integrated circuit mainly comprises two large divisions, peripheral IO unit, and kernel circuitry.The IO unit of integrated circuit; it is the exchange channels of its kernel circuitry and external environment condition; mainly comprise signal IO unit and power supply IO unit; signal carrys out sending and receiving by signal IO; power supply IO provide chip operating voltage; but it is to be also passed to inside by these IO that static threatens, and causes the damage of internal structure, so the emphasis of integrated circuit electrostatic protection design is in the electrostatic protection design of IO.In traditional structure; in signal IO, comprise power supply and esd protection device over the ground; when static discharge occurs, can pass through the esd protection device to power supply, the electrostatic charge of signal IO is transferred on power supply; also can pass through esd protection device over the ground; the electrostatic charge of signal IO is transferred on the ground, then needs through long power/ground, electrostatic current reaches power supply IO unit; by the ESD device in power supply IO, form closed esd discharge loop, complete static discharge.The layout strategy of esd protection circuit will avoid static to enter kernel circuitry exactly, while guaranteeing, between any two IO unit, ESD occurs, can between IO unit, form the electrostatic discharging path of low-resistance, and static is bled off.

In current integrated circuit (IC) design, scale is increasing, a circuit has hundreds and thousands of IO unit to become more and more general, how the large pin of scale just means that the power line of integrated circuit is more and more longer, existence due to the larger dead resistance of long power line, by causing, the total voltage falling-rising in ESD loop is high, if the voltage on a certain node on ESD loop, higher than the puncture voltage of the device of its connection, will cause this device to puncture inefficacy.Even if this voltage does not have the puncture voltage higher than device on the other hand, for hundreds of IO unit, complete the ESD test that full chip is complete, possible this circuit will be hit thousands of times by static, in this very long electrostatic test process, the result of the high heat that high voltage causes is exactly that the heat of accumulation can form the rising of device temperature, if temperature is increased to the fusing point of material, will cause the thermal failure of device.So for multi-pipe pin large scale integrated circuit, the overall presure drop that reduces static discharge loop becomes most important.In the ESD PRACTICE OF DESIGN of integrated circuit, engineers often finds, one in small scale in circuitry through the ESD structure of checking, be transplanted to while applying in the large scale integrated circuit of multi-pipe pin, often ESD ability can decline to a great extent, and Here it is because the dead resistance of long power line causes.

Summary of the invention

What the present invention proposed is a kind of effective solution, is not increasing circuit area, does not increase in the situation of manufacturing process, reduces static discharge loop voltage and falls, and improves integrated circuit ESD ability.

The invention provides a kind of static discharge new architecture, in traditional E SD design basis, by increase the esd discharge path 101 on a power supply-ground in each signal IO unit of multi-pipe pin large scale integrated circuit, can realize reduction ESD loop voltage falls, reduce the voltage of sensitive nodes, promote chip electro-static discharge efficiency, thereby realize the lifting of full chip ESD level.

Wherein, the ESD structure of signal IO unit comprises the electrostatic discharging path 105 that ESD device from IO to power supply provides IO-power supply, and the PMOS being protected by grid connecting resistance forms; The ESD device comprising from IO to ground provides the electrostatic discharging path 104 between IO-ground, and the NMOS being protected by grid connecting resistance forms; Comprise power supply-ground esd discharge path 101 simultaneously and consist of NMOS discharge device, be connected across between power supply-ground, its grid is controlled by static discriminator circuit 103, thereby in signal IO, realizes the static discharge on power supply-ground.

Power supply IO unit, its structure is a nmos device, is connected across between power supply-ground wire, its grid is controlled by static discriminator circuit 103 equally, realizes the esd discharge path 102 of power supply-ground wire.

In traditional design, the GCNMOS structure that ESD device in power supply IO unit is normally driven by RC delay circuit, can directly use the RC drive circuit in power supply/ground IO in the present invention, can form static discriminator circuit 103, thereby this static discriminator circuit 103 can be controlled the opening and closing of the power supply-ground esd discharge device in each IO, when ESD occurs, this static discriminator circuit 103 can be exported start signal 106, open the power supply-ground esd discharge device 101,102 in each signal IO, realize the static discharge from power supply to ground.And when circuit is normally worked, this static discriminator circuit will keep output shutdown signal, maintain the closed condition of the power supply-ground esd discharge device in each signal IO, the normal work of circuit is impacted avoiding.This static discriminator circuit 103 consists of RC delay circuit, and its RC value is greater than static discharge rising time, is less than the power supply electrifying time, thereby can screen out circuit for which kind of state.

Because the method has reduced the voltage drop of ESD loop, so reduced the area requirements to power supply and ESD device over the ground in IO, therefore can be on the area of saving designing power supply to the electro-static discharging device on ground, therefore the area of IO whole unit does not increase, therefore the gross area of integrated circuit does not increase yet, the present invention simultaneously only relates to the improvement of circuit structure, so manufacturing cost is not increased yet.

Accompanying drawing explanation

Fig. 1 is the invention process case.

Fig. 2 is traditional E SD design case study on implementation.

Embodiment

Conventionally in integrated circuit, there is overall power and ground, and all signal IO and power supply/ground IO are connected between power/ground.ESD test comprises IO-VDD, IO-GND, IO-IO, the test of VDD-GND, take IO-IO test as example, when to carry out+ESD of IO A test and during IO B ground connection, static discharge current is as Fig. 1, discharge path shown in curve arrow in 2, in traditional E SD design, this electric current flow through the long GND line->NM2->B of the long vdd line->NM3-> of A->PM1-> (), in multi-pipe pin large scale integrated circuit, general vdd line and GND line are all longer, its dead resistance can reach more than 4 ohm, approximately 5 ohm of ESD break-over of device resistance, for HBM2000V, test, the about 1.33A of its discharging current, in traditional E SD design, more than the voltage drop of this circuit discharging loop can reach 30V, be that A node voltage in IO unit surpasses 30V, this has surpassed the puncture voltage of general device, and A node is connected with inner small size device, therefore will cause internal components ESD to lose efficacy.And in the present invention's design as Fig. 1, owing to having increased the discharge device from VDD to GND in each IO unit, in IO A, increased NM3, in IO B, increased NM4, equally IO A is carried out to forward ESD test and during IO B ground connection, ESD device in NM3 and NM4 and other IO therebetween will be brought into play Main Function, needn't in power supply/ground IO, discharge through longer power line, so its electrostatic discharging path mainly comprises PM1->NM3/NM4->NM2 and arrives ground, because NM3/NM4 is in parallel with the ESD device between the power supply-ground in other IO, its resistance is very little, with maximum 1 ohm of estimation, equally under HBM2000V test 1.33A current conditions, the voltage drop of ESD loop is only 14.6V, this is less than the puncture voltage of general device, so can protecting internal circuit that ESD does not occur effectively, this design lost efficacy.For IO-VDD, IO-GND, VDD-GND test pattern, can reduce the voltage drop of ESD loop equally, promote full chip electro-static discharge level.

Claims

1. the full chip electro-static discharge guard method of integrated circuit; it is characterized in that; by design the esd discharge path on a power supply-ground in each signal IO unit of multi-pipe pin large scale integrated circuit; increase electrostatic discharging path in full chip; shortened the electrostatic discharging path between IO; reduce esd discharge resistance, reduce ESD loop voltage and fall, promote full chip electro-static discharge efficiency.

2. the full chip electro-static discharge protective circuit of integrated circuit, is characterized in that comprising the ESD device 105 from signal IO unit to power supply IO unit, the ESD device 104 from signal IO unit to ground, and NMOS esd discharge device 101, static discriminator circuit 103, wherein:

The P-type mos that ESD device 105 is protected by grid connecting resistance forms;

The N-type metal-oxide semiconductor (MOS) that ESD device 104 is protected by grid connecting resistance forms;

NMOS esd discharge device 101 is connected across between power supply-ground wire, and its grid is controlled by static discriminator circuit 103, thereby in signal IO unit, realizes the esd discharge path on power supply-ground.

3. circuit according to claim 2, it is characterized in that, each power supply IO unit, its structure is a N-type metal oxide semiconductor device, be connected across and between power supply-ground wire, form electrostatic discharging path 102, its grid is controlled by static discriminator circuit 103, realizes the esd discharge path on power supply-ground.

4. circuit according to claim 2, it is characterized in that, the control signal 106 that static discriminator circuit 103 produces is controlled the signal IO unit of full chip and the opening and closing of the power supply-ground NMOS esd discharge device in power supply IO unit, when ESD occurs, these static discriminator circuit 103 output start signal 106, open the power supply-ground esd discharge device 101 in each IO, 102, the static discharge of realization from power supply to ground, and when circuit is normally worked, this static discriminator circuit 103 will keep output shutdown signal, maintain the closed condition of the power supply-ground esd discharge device in each IO, the normal work of circuit is impacted avoiding.

5. circuit according to claim 4, it is characterized in that, this static discriminator circuit 103 consists of RC delay circuit, and its RC value is greater than static discharge rising time, be less than the power supply electrifying time, thereby can screen out circuit in static discharge state or circuit normal operating conditions.