CN103646934A - Secondary plating-prior-to-etching metal frame subtraction imbedded chip normal-installation flat pin structure and process method - Google Patents
Secondary plating-prior-to-etching metal frame subtraction imbedded chip normal-installation flat pin structure and process method Download PDFInfo
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- CN103646934A CN103646934A CN201310645302.XA CN201310645302A CN103646934A CN 103646934 A CN103646934 A CN 103646934A CN 201310645302 A CN201310645302 A CN 201310645302A CN 103646934 A CN103646934 A CN 103646934A
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- photoresistance film
- metal substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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Abstract
The invention relates to a secondary plating-prior-to-etching metal frame subtraction imbedded chip normal-installation flat pin structure and a process method. The structure comprises a metal substrate fame (1). The metal substrate fame (1) is internally provided with base islands (2) and pins (3). The pins (3) are in step shapes. The back surface of each base island (2) is flush with the step surface of each pin (3). The step surface of each pin (3) is provided with a metal layer (4). The back surface of each base island (2) is normally equipped with a chip (6). The surface of the chip (6) is connected with the surface of the metal layer (4) through a metal line (7). The metal substrate fame (1) is internally filled with plastic packaging material (8). The front surface of the plastic packaging material (8) is flush with the step surface of the pin (3). The back surface of the plastic packaging material (8) is flush with the back surface of the metal substrate fame (1). The front surface of the base island (2), the front surface and the back surface of each pin (3) as well as the front surface and the back surface of the metal substrate fame (1) are provided with an anti-oxidation layer (9). The beneficial effect of the structure and method is that: the problem that the function and the application performance of a conventional metal lead frame are limited since an object cannot be imbedded in the metal lead frame is solved.
Description
Technical field
The present invention relates to a kind of secondary and first plate rear erosion metal frame subtraction and bury the flat leg structure of chip formal dress and process, belong to semiconductor packaging field.
Background technology
Traditional flat-four-side mainly contains two kinds without pin metal leadframe structure:
Be flat-four-side without pin package (QFN) lead frame, the lead frame of this structure forms (as shown in figure 22) by copper material metal framework and high temperature resistant glued membrane;
Be to seal in advance flat-four-side without pin package (PQFN) lead frame, the lead frame structure of this structure comprises pin Yu Ji island, and the etching area between pin Yu Ji island is filled with plastic packaging material (as shown in figure 23).
There is following shortcoming in above-mentioned traditional metal lead frame:
1, traditional metal lead frame is as the package carrier that loads chip, and itself does not possess systemic-function, thereby has limited integrated functionality and application performance after traditional metal leadframe package;
2, because traditional metal lead frame itself does not possess systemic-function, can only carry out in lead frame front tiling or the stacked package of chip and assembly, and power device and control chip are encapsulated in same packaging body, the heat radiation of power device can affect the transmission of control chip signal;
3, because traditional metal lead frame itself does not possess systemic-function, so multifunction system integration module can only be in traditional metal lead frame front by tiling or stacking realization of multi-chip and assembly, correspondingly also just increase component module shared space on PCB.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, provide a kind of secondary first to plate rear erosion metal frame subtraction and bury the flat leg structure of chip formal dress and process, it can solve the problem that traditional metal lead frame lacks systemic-function.
The object of the present invention is achieved like this: a kind of secondary first plates rear erosion metal frame subtraction and buries the flat leg structure of chip formal dress, it comprises Metal Substrate sheet frame, described Metal Substrate sheet frame inside is provided with Ji Dao and pin, described pin is step-like, the front of described Ji Dao and pin flushes with Metal Substrate sheet frame front, the back side of described pin flushes with the back side of Metal Substrate sheet frame, the described Ji Dao back side flushes with the step surface of pin, on the step surface of described pin, be provided with metal level, chip is just being equipped with by conduction or non-conductive bonding material in the described Ji Dao back side, between described chip surface and layer on surface of metal, by metal wire, be connected, described Metal Substrate sheet frame interior zone is filled with plastic packaging material, described plastic packaging material is positive to be flushed with pin step surface, the described plastic packaging material back side flushes with the Metal Substrate sheet frame back side, described base island is positive, the front and back of the front and back of pin and Metal Substrate sheet frame is provided with metal oxidation resistance layer or coating antioxidant (OSP).
Described chip Yu Ji island is provided with metal level between the back side.
Secondary first plates the process that rear erosion metal frame subtraction buries the flat leg structure of chip formal dress, said method comprising the steps of:
Step 1, get metal substrate
Step 2, the operation of subsides photoresistance film
In metal substrate front and the back side stick respectively the photoresistance film that can carry out exposure imaging;
Part photoresistance film is removed at step 3, metal substrate front and the back side
Graph exposure is carried out, develops and removes part figure photoresistance film, the region of electroplating to expose the follow-up needs in metal substrate front and the back side in the metal substrate front and the back side that utilize exposure imaging equipment that step 2 is completed to the operation of subsides photoresistance film;
In step 3, anti-oxidant metal layer or coating antioxidant (OSP) are electroplated in the region of metal substrate front and back side removal part photoresistance film;
Remove the photoresistance film of metallic substrate surfaces;
Step 6, the operation of subsides photoresistance film
In step 4, complete metal substrate front and the back side of electroplating after anti-oxidant metal layer and stick the photoresistance film that can carry out exposure imaging;
Part photoresistance film is removed at step 7, the metal substrate back side
Part figure photoresistance film is carried out graph exposure, develops and removes in the metal substrate back etched region that utilizes exposure imaging equipment that step 6 is completed to the operation of subsides photoresistance film, and to expose, the metal substrate back side is follow-up need to carry out etched region;
Step 8, etching
In step 7, chemical etching is carried out in the region of metal substrate back side removal part photoresistance film;
Step 9, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 10, the operation of subsides photoresistance film
The photoresistance film that can carry out exposure imaging is sticked at the metal substrate front and the back side that in step 8, complete after etching;
Part photoresistance film is removed at step 11, the metal substrate back side
Graph exposure is carried out, develops and removes part figure photoresistance film, the region of electroplating to expose the follow-up needs in metal substrate back etched region in the metal substrate back etched region that utilizes exposure imaging equipment that step 10 is completed to the operation of subsides photoresistance film;
Step 12, plated metal line layer
In step 11, in the region of metal substrate back etched region removal part photoresistance film, electroplate metallic circuit layer, metallic circuit layer forms corresponding Ji Dao and pin at the metal substrate back side after having electroplated;
Step 13, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 14, load
In step 12, form the back side, Ji island and implant chip by conduction or non-conductive bonding material;
Step 15, metal wire bonding
Between chip front side and the pin of step 12 formation, carry out the operation of bonding metal wire;
Step 10 six, epoxy resin plastic packaging
The protection of epoxy resin plastic packaging is carried out in metal substrate back etched region after completing load routing;
Step 10 seven, the operation of subsides photoresistance film
The photoresistance film that can carry out exposure imaging is sticked at the metal substrate front and the back side that in step 10 six, complete after epoxy resin plastic packaging;
Step 10 eight, the positive part photoresistance film of removing of metal substrate
Part figure photoresistance film is carried out graph exposure, develops and removes in the metal substrate front that utilizes exposure imaging equipment that step 10 seven is completed to the operation of subsides photoresistance film, and to expose, metal substrate front is follow-up need to carry out etched region;
Step 10 nine, etching
In step 10 eight, chemical etching is carried out in the positive region of removing part photoresistance film of metal substrate;
Step 2 ten, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces.
When the anti-oxidant metal layer of step 4 plating is nickel gold or NiPdAu, step 6 and step 7 can be omitted.
Compared with prior art, the present invention has following beneficial effect:
1, the interlayer of subtractive metallization technology lead frame can be because of the needs of system and function be imbedded active member or assembly or passive assembly in the position of needs or region, becomes a system-level metal lead wire frame of individual layer circuit;
2, from the outward appearance of subtractive metallization technology lead frame finished product, can't see inner interlayer has completely imbedded because of system or the object of function needs, especially the imbedding X-ray and all cannot inspect of the chip of silicon material, fully reaches confidentiality and the protectiveness of system and function;
3, the interlayer of subtractive metallization technology lead frame can be imbedded high-power component in manufacturing process, secondary encapsulation carries out the load of control chip again, thereby high-power component and control chip are contained in respectively subtractive metallization technology lead frame both sides, can avoid high-power component to disturb the signal of control chip because of thermal radiation and transmit;
4, subtractive metallization technology lead frame itself includes the function of imbedding object, after secondary encapsulation, can fully realize the integrated of systemic-function and integrate, it is little that thereby the volume size of the component module of said function comes than the module of conventional lead frame encapsulation, corresponding space shared on PCB is also just fewer, thereby has also just reduced cost;
5, the interlayer of subtractive metallization technology lead frame can be because heat conduction or heat radiation need in manufacturing process be imbedded heat conduction or heat radiation object in the position of needs or region, thereby improves the radiating effect of whole encapsulating structure;
6, subtractive metallization technology lead frame finished product itself has just been rich in various assemblies, if no longer carry out, in the situation of follow-up encapsulation for the second time, subtractive metallization technology lead frame being cut according to each lattice unit, itself just can become a ultra-thin packaging body;
7, subtractive metallization technology lead frame, except itself including imbedding of object can also superpose in packaging body periphery function different unit package or system in package, fully reaches the dual system of individual layer circuit metal lead wire frame or the encapsulation technology ability of polyphyly irrespective of size again;
8, object or the object in subtractive metallization technology lead frame, imbedded all flush with metal thickness, embody fully among the ultra-thin and highdensity thickness space being filled in subtractive metallization technology lead frame.
9, secondary first loses rear plating frame subtraction technology lead frame and can present certain height offset in plastic packaging material front, die-attach area surface, its advantage be after plastic packaging material plastic packaging for the second time firmly snatch live metal salient point, thereby reduced plastic-sealed body and die-attach area produce layering reliability bad because of the gap of CTE (coefficient of expansion or shrinkage).
Accompanying drawing explanation
Fig. 1 ~ Figure 20 is that a kind of secondary of the present invention first plates each operation schematic diagram that rear erosion metal frame subtraction buries the flat leg structure process of chip formal dress.
Figure 21 is that a kind of secondary of the present invention first plates the schematic diagram that rear erosion metal frame subtraction buries the flat leg structure of chip formal dress.
Figure 22 is that traditional flat-four-side is without the schematic diagram of pin package (QFN) lead frame structure.
Figure 23 is for to seal flat-four-side without the schematic diagram of pin package (PQFN) lead frame structure in advance.
Wherein:
Metal Substrate sheet frame 1
Base island 2
Pin 3
Conduction or non-conductive bonding material 5
Chip 6
Metal wire 7
Plastic packaging material 8
Anti oxidation layer 9.
Embodiment
Referring to Figure 21, a kind of secondary of the present invention first plates rear erosion metal frame subtraction and buries the flat leg structure of chip formal dress, it comprises Metal Substrate sheet frame 1, described Metal Substrate sheet frame 1 inside is provided with base island 2 and pin 3, described pin 3 is step-like, the front of described base island 2 and pin 3 flushes with Metal Substrate sheet frame 1 front, the back side of described pin 3 flushes with the back side of Metal Substrate sheet frame 1, 2 back sides, described base island flush with the step surface of pin 3, on the step surface of described pin 3, be provided with metal level 4, chip 6 is just being equipped with by conduction or non-conductive bonding material 5 in 2 back sides, described base island, between described chip 6 surfaces and metal level 4 surfaces, by metal wire 7, be connected, described Metal Substrate sheet frame 1 interior zone is filled with plastic packaging material 8, described plastic packaging material 8 is positive to be flushed with pin 3 step surfaces, described plastic packaging material 8 back sides flush with Metal Substrate sheet frame 1 back side, 2 fronts, described base island, the front and back of the front and back of pin 3 and Metal Substrate sheet frame 1 is provided with anti oxidation layer 9.
Described chip 6 Yu Ji island is provided with metal level 4 between 2 back sides.
Its process is as follows:
Step 1, get metal substrate
Referring to Fig. 1, get the metal substrate that a slice thickness is suitable, the material of metal substrate can be metallics or the nonmetallic substance that copper material, iron material, zinc-plated material, stainless steel, aluminium maybe can reach conducting function, and the selection of thickness can be selected according to product performance;
Step 2, the operation of subsides photoresistance film
Referring to Fig. 2, in metal substrate front and the back side stick respectively the photoresistance film that can carry out exposure imaging, photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film;
Part photoresistance film is removed at step 3, metal substrate front and the back side
Referring to Fig. 3, graph exposure is carried out, develops and removes part figure photoresistance film, the region of electroplating to expose the follow-up needs in metal substrate front and the back side in the metal substrate front and the back side that utilize exposure imaging equipment that step 2 is completed to the operation of subsides photoresistance film;
Referring to Fig. 4, in step 3, anti-oxidant metal layer or coating antioxidant (OSP) are electroplated in the region of metal substrate front and back side removal part photoresistance film;
Referring to Fig. 5, remove the photoresistance film of metallic substrate surfaces, the method for removing photoresistance film adopts chemical medicinal liquid to soften and adopts high pressure water washing;
Step 6, the operation of subsides photoresistance film
Referring to Fig. 6, in step 4, complete metal substrate front and the back side of electroplating after anti-oxidant metal layer and stick the photoresistance film that can carry out exposure imaging, photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film;
Part photoresistance film is removed at step 7, the metal substrate back side
Referring to Fig. 7, part figure photoresistance film is carried out graph exposure, develops and removes in the metal substrate back etched region that utilizes exposure imaging equipment that step 6 is completed to the operation of subsides photoresistance film, and to expose, the metal substrate back side is follow-up need to carry out etched region;
Step 8, etching
Referring to Fig. 8, in step 7, chemical etching is carried out in the region of metal substrate back side removal part photoresistance film, and the technology of chemical etching can adopt copper chloride, iron chloride or can carry out the chemical agent of corroding metal material;
Step 9, removal photoresistance film
Referring to Fig. 9, remove the photoresistance film of metallic substrate surfaces, the method for removing photoresistance film adopts chemical medicinal liquid to soften and adopts high pressure water washing;
Step 10, the operation of subsides photoresistance film
Referring to Figure 10, the photoresistance film that can carry out exposure imaging is sticked at the metal substrate front and the back side that in step 8, complete after etching, and photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film;
Part photoresistance film is removed at step 11, the metal substrate back side
Referring to Figure 11, graph exposure is carried out, develops and removes part figure photoresistance film, the region of electroplating to expose the follow-up needs in metal substrate back etched region in the metal substrate back etched region that utilizes exposure imaging equipment that step 10 is completed to the operation of subsides photoresistance film;
Step 12, plated metal line layer
Referring to Figure 12, in step 11, in the region of metal substrate back etched region removal part photoresistance film, electroplate metallic circuit layer, metallic circuit layer forms corresponding Ji Dao and pin at the metal substrate back side after having electroplated, the material of metallic circuit layer can be silver, nickel is golden or NiPdAu etc., thickness or the conductive metal material that can electroplate according to different qualities conversion, plating mode can be that metallide also can adopt the mode of chemical deposition;
Step 13, removal photoresistance film
Referring to Figure 13, remove the photoresistance film of metallic substrate surfaces, the method for removing photoresistance film adopts chemical medicinal liquid to soften and adopts high pressure water washing;
Step 14, load
Referring to Figure 14, in step 12, form the back side, Ji island and implant chip by conduction or non-conductive bonding material, implanting the mode of chip can select flexibly according to product performance, can adopt the mode of the positive millet cake mucilage binding of Ji Dao sheet, chip back covering glue layer or DAF (Die Attach Film) film to carry out load;
Step 15, metal wire bonding
Referring to Figure 15, between chip front side and the pin of step 12 formation, carry out the operation of bonding metal wire;
Step 10 six, epoxy resin plastic packaging
Referring to Figure 16, the protection of epoxy resin plastic packaging is carried out in the metal substrate back etched region after completing load routing, and epoxide resin material can be selected to have filler or do not have Packed kind according to product performance;
Step 10 seven, the operation of subsides photoresistance film
Referring to Figure 17, the photoresistance film that can carry out exposure imaging is sticked at the metal substrate front and the back side that in step 10 six, complete after epoxy resin plastic packaging;
Step 10 eight, the positive part photoresistance film of removing of metal substrate
Referring to Figure 18, part figure photoresistance film is carried out graph exposure, develops and removes in the metal substrate front that utilizes exposure imaging equipment that step 10 seven is completed to the operation of subsides photoresistance film, and to expose, metal substrate front is follow-up need to carry out etched region;
Step 10 nine, etching
Referring to Figure 19, in step 10 eight, chemical etching is carried out in the positive region of removing part photoresistance film of metal substrate, and the technology of chemical etching can adopt copper chloride, iron chloride or can carry out the chemical agent of corroding metal material;
Step 2 ten, removal photoresistance film
Referring to Figure 20, remove the photoresistance film of metallic substrate surfaces, the method for removing photoresistance film adopts chemical medicinal liquid to soften and adopts high pressure water washing.
Claims (4)
1. a secondary first plates rear erosion metal frame subtraction and buries the flat leg structure of chip formal dress, it is characterized in that: it comprises Metal Substrate sheet frame (1), described Metal Substrate sheet frame (1) inside is provided with Ji Dao (2) and pin (3), described pin (3) is step-like, the front of described Ji Dao (2) and pin (3) flushes with Metal Substrate sheet frame (1) front, the back side of described pin (3) flushes with the back side of Metal Substrate sheet frame (1), described Ji Dao (2) back side flushes with the step surface of pin (3), on the step surface of described pin (3), be provided with metal level (4), chip (6) is just being equipped with by conduction or non-conductive bonding material (5) in described Ji Dao (2) back side, between described chip (6) surface and metal level (4) surface, by metal wire (7), be connected, described Metal Substrate sheet frame (1) interior zone is filled with plastic packaging material (8), described plastic packaging material (8) is positive to be flushed with pin (3) step surface, described plastic packaging material (8) back side flushes with Metal Substrate sheet frame (1) back side, described Ji Dao (2) front, the front and back of the front and back of pin (3) and Metal Substrate sheet frame (1) is provided with anti oxidation layer (9).
2. a kind of secondary according to claim 1 first plates rear erosion metal frame subtraction and buries the flat leg structure of chip formal dress, it is characterized in that: described chip (6) Yu Ji island (2) is provided with metal level (4) between the back side.
3. secondary first plates the process that rear erosion metal frame subtraction buries the flat leg structure of chip formal dress, it is characterized in that said method comprising the steps of:
Step 1, get metal substrate
Step 2, the operation of subsides photoresistance film
In metal substrate front and the back side stick respectively the photoresistance film that can carry out exposure imaging;
Part photoresistance film is removed at step 3, metal substrate front and the back side
Graph exposure is carried out, develops and removes part figure photoresistance film, the region of electroplating to expose the follow-up needs in metal substrate front and the back side in the metal substrate front and the back side that utilize exposure imaging equipment that step 2 is completed to the operation of subsides photoresistance film;
Step 4, plating anti-oxidant metal layer
In step 3, anti-oxidant metal layer is electroplated in the region of metal substrate front and back side removal part photoresistance film;
Step 5, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 6, the operation of subsides photoresistance film
In step 4, complete metal substrate front and the back side of electroplating after anti-oxidant metal layer and stick the photoresistance film that can carry out exposure imaging;
Part photoresistance film is removed at step 7, the metal substrate back side
Part figure photoresistance film is carried out graph exposure, develops and removes in the metal substrate back etched region that utilizes exposure imaging equipment that step 6 is completed to the operation of subsides photoresistance film, and to expose, the metal substrate back side is follow-up need to carry out etched region;
Step 8, etching
In step 7, chemical etching is carried out in the region of metal substrate back side removal part photoresistance film;
Step 9, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 10, the operation of subsides photoresistance film
The photoresistance film that can carry out exposure imaging is sticked at the metal substrate front and the back side that in step 8, complete after etching;
Part photoresistance film is removed at step 11, the metal substrate back side
Graph exposure is carried out, develops and removes part figure photoresistance film, the region of electroplating to expose the follow-up needs in metal substrate back etched region in the metal substrate back etched region that utilizes exposure imaging equipment that step 10 is completed to the operation of subsides photoresistance film;
Step 12, plated metal line layer
In step 11, in the region of metal substrate back etched region removal part photoresistance film, electroplate metallic circuit layer, metallic circuit layer forms corresponding Ji Dao and pin at the metal substrate back side after having electroplated;
Step 13, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 14, load
In step 12, form the back side, Ji island and implant chip by conduction or non-conductive bonding material;
Step 15, metal wire bonding
Between chip front side and the pin of step 12 formation, carry out the operation of bonding metal wire;
Step 10 six, epoxy resin plastic packaging
The protection of epoxy resin plastic packaging is carried out in metal substrate back etched region after completing load routing;
Step 10 seven, the operation of subsides photoresistance film
The photoresistance film that can carry out exposure imaging is sticked at the metal substrate front and the back side that in step 10 six, complete after epoxy resin plastic packaging;
Step 10 eight, the positive part photoresistance film of removing of metal substrate
Part figure photoresistance film is carried out graph exposure, develops and removes in the metal substrate front that utilizes exposure imaging equipment that step 10 seven is completed to the operation of subsides photoresistance film, and to expose, metal substrate front is follow-up need to carry out etched region;
Step 10 nine, etching
In step 10 eight, chemical etching is carried out in the positive region of removing part photoresistance film of metal substrate;
Step 2 ten, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces.
4. a kind of secondary according to claim 3 first plates the process that rear erosion metal frame subtraction buries the flat leg structure of chip formal dress, it is characterized in that: when the anti-oxidant metal layer of step 4 plating is nickel gold or NiPdAu, step 6 and step 7 can be omitted.
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CN201310645302.XA CN103646934B (en) | 2013-12-05 | 2013-12-05 | First plate for two times and lose metal frame subtraction afterwards and bury chip and just filling flat leg structure and processing method |
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Citations (4)
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US20030064547A1 (en) * | 1999-02-01 | 2003-04-03 | Salman Akram | High density modularity for IC's |
CN1921108A (en) * | 2005-08-23 | 2007-02-28 | 新光电气工业株式会社 | Semiconductor package and manufacturing method thereof |
CN103298275A (en) * | 2013-05-20 | 2013-09-11 | 江苏长电科技股份有限公司 | Metal circuit plating and etching successive method for multilayer circuit base board with metal frame |
CN103413766A (en) * | 2013-08-06 | 2013-11-27 | 江苏长电科技股份有限公司 | Etching-first-packaging-second upside-upward-installation three-dimensional system-in-package metal circuit board structure and process method |
-
2013
- 2013-12-05 CN CN201310645302.XA patent/CN103646934B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US20030064547A1 (en) * | 1999-02-01 | 2003-04-03 | Salman Akram | High density modularity for IC's |
CN1921108A (en) * | 2005-08-23 | 2007-02-28 | 新光电气工业株式会社 | Semiconductor package and manufacturing method thereof |
CN103298275A (en) * | 2013-05-20 | 2013-09-11 | 江苏长电科技股份有限公司 | Metal circuit plating and etching successive method for multilayer circuit base board with metal frame |
CN103413766A (en) * | 2013-08-06 | 2013-11-27 | 江苏长电科技股份有限公司 | Etching-first-packaging-second upside-upward-installation three-dimensional system-in-package metal circuit board structure and process method |
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