CN103633032B - The formation method of semiconductor device, the formation method of transistor - Google Patents
The formation method of semiconductor device, the formation method of transistor Download PDFInfo
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- CN103633032B CN103633032B CN201210299450.6A CN201210299450A CN103633032B CN 103633032 B CN103633032 B CN 103633032B CN 201210299450 A CN201210299450 A CN 201210299450A CN 103633032 B CN103633032 B CN 103633032B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
Abstract
A kind of formation method of semiconductor device, the formation method of transistor, wherein, the formation method of semiconductor device comprises: provide semiconductor-on-insulator substrate, semiconductor-on-insulator substrate comprises: the insulating barrier of substrate, substrate surface and the semiconductor layer of surface of insulating layer; Form mask layer at semiconductor substrate surface and expose part semiconductor substrate surface; Take mask layer as mask, adopt the first anisotropic wet-etching technology etching semiconductor layer, in semiconductor layer, form the first opening and expose surface of insulating layer; After formation first opening, remove mask layer; Adopt the second anisotropic wet-etching technology etching semiconductor layer afterwards, form the second opening in the semiconductor layer between adjacent first opening and expose surface of insulating layer; Then remove partial insulative layer, form the nano wire be suspended on above substrate; Again thermal annealing is carried out to nano wire, make cross section become circle.The nanowire size formed reduces.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of formation method of semiconductor device, a kind of formation method of transistor.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is towards higher component density, and the future development of higher integrated level.Transistor is just being widely used at present as the most basic semiconductor device, and therefore along with the component density of semiconductor device and the raising of integrated level, the grid size of transistor is also shorter and shorter.But the grid size of transistor shortens and transistor can be made to produce short-channel effect, and then produces leakage current, finally affects the electric property of semiconductor device.
In order to overcome the short-channel effect of transistor, suppress leakage current, prior art proposes a kind of all-around-gate nano-wire transistor; Described all-around-gate nano-wire transistor, while reduction transistor size, can overcome short-channel effect, suppresses the generation of leakage current.Prior art forms the method for all-around-gate nano-wire transistor as shown in Figures 1 to 5, comprising:
Please refer to Fig. 1, form mask layer 101 on Semiconductor substrate 100 surface, described Semiconductor substrate 100 comprises nanowire region 113, and described mask layer 101 exposes the semiconductor substrate surface beyond nanowire region 113; Described Semiconductor substrate 100 is semiconductor-on-insulator (SOI, SemiconductorOnInsulator); Described semiconductor-on-insulator comprises: the insulating barrier 111 on substrate 110, substrate 110 surface and the semiconductor layer 112 on insulating barrier 111 surface; The material of described substrate 110 is monocrystalline silicon, and the material of described insulating barrier 111 is silica.
Described semiconductor-on-insulator comprises: silicon-on-insulator and germanium on insulator; Described silicon-on-insulator is preferably for the formation of nmos pass transistor, and described germanium on insulator is preferably for the formation of PMOS transistor.
Please refer to Fig. 2, shown in institute mask layer 101(Fig. 1) for mask, etch described semiconductor layer 112 and insulating barrier 111, till exposing substrate 110, in Semiconductor substrate 100, form some openings 102; After the some openings 102 of formation, remove mask layer 101.
Please refer to Fig. 3 and Fig. 4, Fig. 4 is the generalized section of Fig. 3 on AA ' direction, after removal mask layer 101, removes insulating barrier 111(and please refer to Fig. 2), form the nano wire be suspended on above substrate 110, and described nano wire two ends are supported by insulating barrier 110.
Please refer to Fig. 5, shown in removal insulating barrier 111(Fig. 4) after, carry out thermal anneal process, make shown in semiconductor layer 112(Fig. 4) form some nano wire 112a arranged in parallel, and the cross section of described nano wire 112a is circular.
But the size forming nano wire and follow-up formation all-around-gate nano-wire transistor with existing technique is bigger than normal, causes the integrated level of semiconductor device lower.
The formation method of more all-around-gate nanowire semiconductor devices, please refer to the U.S. patent documents that publication number is US2011/0133162A1.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor device, and a kind of formation method of transistor, reduces the size of nanowire size and the all-around-gate nano-wire transistor formed, thus improves the integrated level of semiconductor device.
For solving the problem, the invention provides a kind of formation method of semiconductor device, comprising: provide Semiconductor substrate, described Semiconductor substrate comprises: the insulating barrier of substrate, substrate surface and the semiconductor layer of surface of insulating layer; Form some mask layers at described semiconductor substrate surface, described mask layer exposes part semiconductor substrate surface; With described mask layer for mask, adopt the first anisotropic wet-etching technology to etch described semiconductor layer, in described semiconductor layer, form the first opening, described first opening exposes surface of insulating layer; After formation first opening, remove described mask layer; After the described mask layer of removal, adopt the second anisotropic wet-etching technology to etch described semiconductor layer, form the second opening in the semiconductor layer between adjacent first opening, described second opening exposes surface of insulating layer; After formation second opening, remove the described insulating barrier of part, form the nano wire be suspended on above substrate; After removal insulating barrier, thermal annealing is carried out to described nano wire, makes the cross section of described nano wire become circle.
Alternatively, the width of described first open top is 5-100 nanometer.
Alternatively, the top dimension of described first opening or the 3rd opening is greater than bottom size.
Alternatively, the sidewall of described first opening or the 3rd opening and described surface of insulating layer are 50 ~ 60 degree of angles.
Alternatively, also comprise: after formation first opening, form oxide layer at the sidewall of described first opening; Described oxide layer was removed before thermal anneal process.
Alternatively, the formation process of described oxide layer is thermal oxidation technology.
Alternatively, the nanowire cross-section formed after removing insulating barrier is triangle.
Alternatively, the width of described mask layer is 5-100 nanometer.
Alternatively, the thickness of described semiconductor layer is 20 ~ 1000 nanometers.
Alternatively, the material of described semiconductor layer is silicon or germanium.
Alternatively, the etching liquid of described first anisotropic wet-etching technology or the second anisotropic wet-etching technology is tetramethylphosphonihydroxide hydroxide base amine, NaOH, potassium hydroxide, lithium hydroxide or ammoniacal liquor.
Alternatively, the time of described thermal anneal process is 5 seconds ~ 5 hours, and temperature is 650 DEG C ~ 1150 DEG C, and protective gas is hydrogen or inert gas, and air pressure is 0 ~ 760Torr, and described inert gas is argon gas, helium or neon.
Alternatively, after thermal anneal process, the diameter of described nano wire circular cross section is 5-50 nanometer.
Alternatively, the technique of described removal mask layer is dry etching, wet etching or chemico-mechanical polishing.
Alternatively, the material of described insulating barrier is silica.
Alternatively, the technique of described removal insulating barrier is wet etching, and described etching liquid is hydrofluoric acid, phosphoric acid, hydrogen fluorine nitric acid or hydrogen fluorine acetic acid.
Alternatively, the material of described mask layer is silicon nitride, silica or silicon oxynitride.
Correspondingly, the present invention also provides a kind of formation method of transistor, comprising: provide Semiconductor substrate, and described Semiconductor substrate comprises: the insulating barrier of substrate, substrate surface and the semiconductor layer of surface of insulating layer; Form some mask layers at described semiconductor substrate surface, described mask layer exposes part semiconductor substrate surface; With described mask layer for mask, adopt the first anisotropic wet-etching technology to etch described semiconductor layer, in described semiconductor layer, form the first opening, described first opening exposes surface of insulating layer; After formation first opening, remove described mask layer; After the described mask layer of removal, adopt the second anisotropic wet-etching technology to etch described semiconductor layer, form the second opening in the semiconductor layer between adjacent first opening, described second opening exposes surface of insulating layer; After formation second opening, remove insulating barrier, form the nano wire be suspended on above substrate; After removal insulating barrier, thermal annealing is carried out to described nano wire, makes the cross section of described nano wire become circle; After thermal annealing, form gate dielectric layer in described nanowire surface; Gate electrode layer is formed on described gate dielectric layer surface; With described gate electrode layer for mask, in the Semiconductor substrate at described nano wire two ends, doping forms source/drain region.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the formation method of described semiconductor device, take mask layer as mask, adopt the semiconductor layer in Semiconductor substrate described in the first anisotropic wet etching, form the first opening; After removal mask layer, adopt the second anisotropic wet etching semiconductor layer, make described semiconductor layer be formed the second opening by the part that described mask layer covers; Because the formation process of described first opening and the second opening is anisotropic wet etching, therefore the sidewall of described first opening and the second opening tilts relative to surface of insulating layer, and the top dimension of described first opening and the second opening is greater than bottom size, thus the semiconductor layer between the first adjacent opening and the second opening can form nano wire in subsequent technique.Therefore, the part that described semiconductor layer is covered by mask layer can form two nano wires, and formed nanowire size is reduced, and the integrated level of the semiconductor device formed improves further.
In the formation method of transistor described in the present embodiment, the part that described semiconductor layer is covered by mask layer can form two nano wires, therefore formed nanowire size reduces, and the corresponding reduction of the size of the transistor formed, the integrated level of described transistor is higher.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the cross-sectional view that prior art forms the process of all-around-gate nano-wire transistor;
Fig. 6 to Figure 11, Figure 13 are the cross-sectional view of the forming process of the semiconductor device of the first embodiment;
Figure 12 is the cross-sectional view of Figure 11 on BB ' direction;
Figure 14, Figure 16 and Figure 17 are the cross-sectional view of the forming process of the semiconductor device of the second embodiment;
Figure 15 is the cross-sectional view of Figure 14 on CC ' direction.
Embodiment
As stated in the Background Art, the size forming nano wire and follow-up formation all-around-gate nano-wire transistor with existing technique is bigger than normal, causes the integrated level of semiconductor device lower.
The present inventor finds through research, the reason that the nanowire size causing existing technique to be formed cannot reduce further is, the precision of existing photoetching process and the restriction of etching alignment precision, the mask layer 101(causing prior art to be formed is as shown in Figure 1) size and adjacent mask layer 101 between size cannot reduce further, thus limit the size of nano wire, the integrated level of formed semiconductor device cannot be improved further.
In order to not reduce described mask layer size with in the accuracy situation guaranteeing photoresist exposure and etching, the size of formed nano wire is reduced further, the present inventor finds after further research, after semiconductor substrate surface forms mask layer, the first anisotropic wet etching is adopted to form the first opening; Remove described mask layer afterwards, and the semiconductor layer adopting the former mask layer of the second anisotropic wet etching to cover, form the second opening; Because the formation process of described first opening and the second opening is anisotropic wet etching, therefore the first formed opening and the top dimension of the second opening are all greater than bottom size, and its sidewall tilts relative to surface of insulating layer, thus the semiconductor layer between described second opening and the first opening can form nano wire in subsequent technique; It can thus be appreciated that, the semiconductor layer originally with mask layer covering can form two nano wires, the number of nanowires formed is the twice of prior art, and the size of described mask layer is same as the prior art, the size of therefore formed nano wire reduces further, improves the integrated level of semiconductor device.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
First embodiment
Be described below with reference to the formation method of accompanying drawing to the semiconductor device of the embodiment of the present invention, Fig. 6 to Figure 11 and Figure 13 is the cross-sectional view of the forming process of the semiconductor device of the present embodiment, and Figure 12 is the cross-sectional view of Figure 11 on BB ' direction.
Please refer to Fig. 6, provide Semiconductor substrate 200, described Semiconductor substrate 200 is semiconductor-on-insulator, and described semiconductor-on-insulator comprises: the insulating barrier 202 on substrate 201, substrate 201 surface and the semiconductor layer 203 on insulating barrier 202 surface.
Described Semiconductor substrate 200 is for providing workbench for subsequent technique; The material of described substrate 201 is monocrystalline silicon, and the material of described insulating barrier 202 is silica; The thickness of described semiconductor layer 203 is 20 nanometer ~ 1000 nanometers, and the material of described semiconductor layer 203 is silicon or germanium; When described semiconductor layer 203 is silicon, the material of the nano wire formed in subsequent technique is silicon; When described semiconductor layer 203 is germanium, the material of the nano wire formed in subsequent technique is germanium; Because the effective mass of charge carrier in germanium is comparatively low in silicon, then the mobility of charge carrier in germanium is high, when the material of the nano wire that subsequent technique is formed is germanium, and the more excellent performance of the semiconductor device formed with described nano wire; Because the present embodiment adopts twice anisotropic wet etching to form nano wire in subsequent technique, in order to make the wet etching of subsequent technique be parallel to semiconductor layer 203 surface and etch rate perpendicular to described semiconductor layer 203 surface direction very fast, and it is the slowest at the etch rate of (111) crystal face, in the present embodiment, the crystal face on described semiconductor layer 203 surface is (100).
Please refer to Fig. 7, form mask layer 204 on described Semiconductor substrate 200 surface, described mask layer 204 exposes part semiconductor substrate 200 surface.
The material of described mask layer 204 is silica, silicon nitride or silicon oxynitride; The formation method of described mask layer 204 is chemical vapour deposition technique, thermal oxidation method or tropical resources method; Described mask layer 204 is in the follow-up first anisotropic wet-etching technology, and protection needs semiconductor layer 203 surface forming nano wire.
The width of described mask layer 204 is 5 nanometer-100 nanometers, and the diameter range making the nano wire of follow-up formation is 5 ~ 50 nanometers, and the nanowire size formed is less; The formation process of described mask layer 204 is: adopt depositing operation to form mask film on described Semiconductor substrate 200 surface; Form photoresist layer at described mask film surface, described photoresist layer, through exposure imaging and heat treatment, defines the follow-up correspondence position needing to be formed nano wire; With described photoresist layer for mask, adopt dry etching or wet-etching technology, etch described mask film, form mask layer 204.
But, due to the photoetching process of prior art and the alignment precision of described etching technics limited, cause the size of formed mask layer 204 to reduce further, cause the size of follow-up the is formationed nano wire defined with described mask layer 204 cannot continue reduction; On the other hand, the growth requirement of prior art wishes that again the size of semiconductor device is little as far as possible, to reach higher integration level necessitates; Therefore, the present inventor is being formed successively after mask layer 204, and adopt twice anisotropic wet-etching technology, the semiconductor layer 203 that each mask layer 204 is covered can form two nano wires, the twice of the number of nanowires that prior art is formed; Even if when not reducing mask layer 204 size, the nanowire size formed still reduces, and what meet semiconductor device and integrated circuit further develops demand.
Please refer to Fig. 8, with described mask layer 204 for mask, adopt the first anisotropic wet-etching technology to etch described semiconductor layer 203, in described semiconductor layer 203, form the first opening 205, described first opening 205 exposes insulating barrier 202 surface.
The etching liquid of described first anisotropic wet etching is alkaline solution, comprising: potassium hydroxide (KOH), ammoniacal liquor (NH
4or tetramethyl aqua ammonia (TMAH) OH); When described Semiconductor substrate 200(please refer to Fig. 8) surface crystal face for (100) time, described wet-etching technology is very fast at etch rate that is surperficial perpendicular to Semiconductor substrate 200 and that be parallel in Semiconductor substrate 200 surface direction, and the slowest to the etch rate of crystal face (111); Therefore through the first anisotropic wet etching, and after the follow-up second anisotropic wet etching, the semiconductor layer 203 between the first opening 205 formed and the second opening of follow-up formation can form nano wire.
The width at described first opening 205 top is 5-100 nanometer; Because anisotropic wet-etching technology is very fast at etch rate that is surperficial perpendicular to Semiconductor substrate 200 and that be parallel in Semiconductor substrate 200 surface direction, and the slowest to the etch rate of crystal face (111), the sidewall inclination surperficial relative to insulating barrier 202 of the first therefore formed opening 205; And the top dimension of described first opening 205 is greater than bottom size, and the sidewall of described first opening 205 and described insulating barrier 202 surface are in 50 degree ~ 60 degree angles; Because the shape of the second opening of follow-up formation is identical with the first opening 205, the semiconductor layer 203 therefore between described first opening 205 and the second opening can form nano wire in subsequent technique.
In other embodiments, after described first opening 205 of formation, thermal oxidation technology is adopted to form oxide layer (not shown) at the sidewall of described first opening 205, when the material of described semiconductor layer 203 is silicon, the material of described oxide layer is silica, when the material of described semiconductor layer 203 is germanium, the material of described oxide layer is germanium oxide; Described oxide layer can protect the sidewall of described first opening 205 injury-free in the wet-etching technology of the second follow-up anisotropic.
Please refer to Fig. 9, after formation first opening 205, remove described mask layer 204(as shown in Figure 8);
The technique of described mask layer 204 is dry etching, wet etching or CMP (Chemical Mechanical Polishing) process, is preferably wet etching; Adopt the advantage of wet-etching technology for etching thoroughly, and there is stronger selectivity, semiconductor layer 203 can not be damaged while removal mask layer 204.
Please refer to Figure 10, at the described mask layer 204(of removal as shown in Figure 8), the second anisotropic wet-etching technology is adopted to etch described semiconductor layer 203, form the second opening 206 in semiconductor layer 203 between adjacent first opening 205, described second opening 206 exposes insulating barrier 202 surface.
The formation process of described second opening 206 is identical with the technique forming described first opening 205, and therefore not to repeat here.
The width at described second opening 206 top is 5-100 nanometer; Because anisotropic wet-etching technology is very fast at etch rate that is surperficial perpendicular to Semiconductor substrate 200 and that be parallel in Semiconductor substrate 200 surface direction, and it is the slowest to the etch rate of crystal face (111), the top dimension of described second opening 206 is greater than bottom size, and the sidewall of described second opening 206 and described insulating barrier 202 surface are in 50 degree ~ 60 degree angles.
And, because the etch rate of described second anisotropic wet etch technique to (111) crystal face is the slowest, therefore can not cause too thinning to the sidewall of described first opening 205, therefore in the present embodiment, oxide layer is not formed at described first opening 205 sidewall after formation first opening 205, can Simplified flowsheet, cost-saving.
Please refer to Figure 11 and Figure 12, Figure 12 is the cross-sectional view of Figure 11 on BB ' direction, at formation second opening 206(as shown in Figure 10) after, remove shown in part described insulating barrier 202(Figure 10), form the nano wire 207 be suspended on above substrate 201.
The technique of the insulating barrier 202 between described removal nano wire 207 and substrate 201 is wet etching, and etching liquid is acid solution, comprising: hydrofluoric acid, phosphoric acid, hydrogen fluorine nitric acid or hydrogen fluorine acetic acid; When the etching liquid of described wet etching is acid solution, described wet etching is isotropic wet etching, can remove described insulating barrier 202 up hill and dale.
Described nano wire 207 is circular nano wire for the formation of succeeding cross sections, and the nano wire of described circle can be used as in all-around-gate nano-wire transistor as channel region;
After the first anisotropic wet etching and the second anisotropic wet etching, described first opening 205(is as shown in Figure 10) and the second opening 206 between the cross section of nano wire 207 be isosceles triangle, atom is in higher free energy state in described nano wire 207; If when being leg-of-mutton nano wire 207 as the channel region of transistor using described cross section, easily producing leakage current, therefore need subsequent technique to carry out thermal annealing to nano wire 207, reduce its free energy, make nano wire 207 smooth surface.
It should be noted that, in other embodiments, when the sidewall of described first opening 205 is formed with oxide layer, then described oxide layer and described insulating barrier 202 are removed simultaneously.
Please refer to Figure 12, Figure 12 is the cross-sectional view of Figure 11 on BB ' direction, and after removal insulating barrier 202, the nano wire 207 formed is suspended on above substrate 201, described nano wire 207 two ends are communicated with remaining semiconductor layer 203 simultaneously, and are supported by remaining insulating barrier 202.
Please refer to Figure 13, after removal insulating barrier 202, thermal annealing is carried out to described nano wire 207, makes the cross section of described nano wire 207a become circle.
The annealing temperature of described thermal annealing is 650 DEG C ~ 1150 DEG C, and the described thermal annealing time is 5 seconds to 5 hours, and air pressure is 0 ~ 760Torr, and the protective gas of described thermal annealing is the one in inert gas or hydrogen, and described inert gas is argon gas, helium or neon.
Through thermal annealing, the smooth surface of described nano wire 207a, in nano wire 207a, the free energy of atom drops to minimum, and the shape of cross section becomes circle, and the diameter of described circle is 5-50 nanometer; The diameter of described circular cross section is by mask layer 204(in front road technique as shown in Figure 8) width determined, and the region that single mask layer 204 covers can form two nano wires, be prior art form the twice of number of nanowires, when not reducing the size of mask layer 204, the size of formed nano wire 207a is reduced, is conducive to the microminiaturization of semiconductor device and integrated.
It should be noted that, described nano wire 207a can be used in the channel region forming all-around-gate nano-wire transistor; When the channel region of described nano wire 207a as transistor, while the channel region dimensions of transistor can be made to reduce, reduce the generation of leakage current.
In the formation method of semiconductor device described in the present embodiment, with mask layer 204 for mask, adopt the first anisotropic wet-etching technology to etch described semiconductor layer 203, and form the first opening 205; After the described mask layer 204 of removal, adopt semiconductor layer 203 described in the second anisotropic wet etching, and form the second opening 206 in original semiconductor layer 203 part covered by described mask layer; Because the formation process of described first opening and the second opening is anisotropic wet etching, it is leg-of-mutton nano wire 207 that the semiconductor layer 203 therefore between described first opening and the second opening forms cross section; After after removal insulating barrier 202 and thermal annealing, described cross section is that circular nano wire 207a is suspended on above substrate 201; Therefore, by the wet-etching technology of twice anisotropic, when not changing mask layer size, semiconductor layer 203 region covered by described mask layer can form two nano wires, thus reduce the size of nano wire, be conducive to the microminiaturization of semiconductor device and integrated.
Second embodiment
Be described below with reference to the formation method of accompanying drawing to the transistor of the embodiment of the present invention, Figure 14, Figure 16 and Figure 17 are the cross-sectional view of the forming process of the semiconductor device of the present embodiment, Figure 15 is the cross-sectional view of Figure 14 on CC ' direction, and the direction of Figure 17 and Figure 15 is consistent.
Please refer to Figure 14 and Figure 15, Figure 15 is the cross-sectional view of Figure 14 on CC ' direction, Semiconductor substrate 300 is provided, described Semiconductor substrate 300 is semiconductor-on-insulator, and described semiconductor-on-insulator comprises: the insulating barrier 302 on substrate 301, substrate 301 surface and the semiconductor layer 303 on insulating barrier 302 surface; Form the nano wire 304 be suspended on above substrate 301, the cross section of described nano wire 304 is circular.
The formation process of described nano wire 304 is identical with the formation method of semiconductor device described in the first embodiment, and therefore not to repeat here.
Please refer to Figure 15, described nano wire 304 two ends are communicated with semiconductor layer 303, and are supported by insulating barrier 302 and be suspended on above substrate 301.
Please refer to Figure 16, form gate dielectric layer 305 on described nano wire 304 surface; Gate electrode layer 306 is formed on described gate dielectric layer 305 surface.
The material of described gate dielectric layer 305 is silica, silicon nitride or hafnium; Described hafnium comprises: hafnium oxide, zirconia, hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide; When the material of described gate dielectric layer 305 be silica or silicon nitride time, the material of described gate electrode layer 306 is polysilicon; When the material of described gate dielectric layer 305 is hafnium, the material of described gate electrode layer 306 is metal.
In one example, when the material of described gate dielectric layer 305 be silica or silicon nitride time, the formation method of described gate dielectric layer 305 is have the chemical vapor deposition method of good step spreadability, atom layer deposition process, thermal oxidation technology or tropical resources technique, and the formation method of described gate electrode layer 306 is chemical vapor deposition method or the atom layer deposition process with good step spreadability.
In another example, when the material of described gate dielectric layer 305 is hafnium, the formation method of described gate dielectric layer 305 and described gate electrode layer 306 is the chemical vapor deposition method or atom layer deposition process with good step spreadability.
It should be noted that, after formation gate electrode layer 306, around described gate electrode layer 306, and substrate 201 surface coverage insulating material, until described gate electrode layer 306 is covered.
Please refer to Figure 17, the direction of Figure 17 and Figure 15 is consistent, and with described gate electrode layer 306 for mask, in the Semiconductor substrate 300 at described nano wire 304 two ends, doping forms source/drain region 307.
In one example, when needs form p-type transistor, then described semiconductor layer 303 is through the doping of n trap, and with gate electrode layer 306 for mask, carry out p-type ion implantation at described nano wire 304 two ends, the ion of described ion implantation comprises: boron ion and indium ion.
In another example, when needs form n-type transistor, then described semiconductor layer 203 is through the doping of p trap, and with gate electrode layer 306 for mask, carry out N-shaped ion implantation at described nano wire 304 two ends, the ion of described ion implantation comprises phosphonium ion and arsenic ion.
In the formation method of transistor described in the present embodiment, because described nano wire 304 is formed by twice anisotropic wet etching and thermal anneal process, and the region covered by mask layer in preorder technique can form two nano wires 304; When not reducing mask layer size, nano wire 304 size formed reduces, thus the corresponding reduction of the size of the transistor formed, the integrated level of described transistor is higher.
In sum, in the formation method of described semiconductor device, take mask layer as mask, adopt the semiconductor layer in Semiconductor substrate described in the first anisotropic wet etching, form the first opening; After removal mask layer, adopt the second anisotropic wet etching semiconductor layer, make described semiconductor layer be formed the second opening by the part that described mask layer covers; Because the formation process of described first opening and the second opening is anisotropic wet etching, therefore the sidewall of described first opening and the second opening tilts relative to surface of insulating layer, and the top dimension of described first opening and the second opening is greater than bottom size, thus the semiconductor layer between the first adjacent opening and the second opening can form nano wire in subsequent technique; Therefore, the part that described semiconductor layer is covered by mask layer can form two nano wires, and formed nanowire size is reduced, and the integrated level of the semiconductor device formed improves further.
In the formation method of transistor described in the present embodiment, the part that described semiconductor layer is covered by mask layer can form two nano wires, therefore formed nanowire size reduces, and the corresponding reduction of the size of the transistor formed, the integrated level of described transistor is higher.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (18)
1. a formation method for semiconductor device, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises: the insulating barrier of substrate, substrate surface and the semiconductor layer of surface of insulating layer;
Form mask layer at described semiconductor substrate surface, described mask layer exposes part semiconductor substrate surface;
With described mask layer for mask, adopt the first anisotropic wet-etching technology to etch described semiconductor layer, in described semiconductor layer, form the first opening, described first opening exposes surface of insulating layer;
After formation first opening, remove described mask layer;
After the described mask layer of removal, adopt the second anisotropic wet-etching technology to etch described semiconductor layer, form the second opening in the semiconductor layer between adjacent first opening, described second opening exposes surface of insulating layer;
After formation second opening, remove the described insulating barrier of part, form the nano wire be suspended on above substrate;
After removal insulating barrier, thermal annealing is carried out to described nano wire, makes the cross section of described nano wire become circle.
2. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the width of described first open top is 5-100 nanometer.
3. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the top dimension of described first opening or the second opening is greater than bottom size.
4. the formation method of semiconductor device as claimed in claim 3, it is characterized in that, the sidewall of described first opening or the second opening and described surface of insulating layer are 50 ~ 60 degree of angles.
5. the formation method of semiconductor device as claimed in claim 1, is characterized in that, also comprise: after formation first opening, forms oxide layer at the sidewall of described first opening; Described oxide layer was removed before thermal anneal process.
6. the formation method of semiconductor device as claimed in claim 5, it is characterized in that, the formation process of described oxide layer is thermal oxidation technology.
7. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the nanowire cross-section formed after removing insulating barrier is triangle.
8. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the width of described mask layer is 5-100 nanometer.
9. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the thickness of described semiconductor layer is 20 ~ 1000 nanometers.
10. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the material of described semiconductor layer is silicon or germanium.
The formation method of 11. semiconductor device as claimed in claim 1, it is characterized in that, the etching liquid of described first anisotropic wet-etching technology or the second anisotropic wet-etching technology is tetramethylphosphonihydroxide hydroxide base amine, NaOH, potassium hydroxide, lithium hydroxide or ammoniacal liquor.
The formation method of 12. semiconductor device as claimed in claim 1, it is characterized in that, the time of described thermal anneal process is 5 seconds ~ 5 hours; temperature is 650 DEG C ~ 1150 DEG C; protective gas is hydrogen or inert gas, and air pressure is 0 ~ 760Torr, and described inert gas is argon gas, helium or neon.
The formation method of 13. semiconductor device as claimed in claim 1, it is characterized in that, after thermal anneal process, the diameter of described nano wire circular cross section is 5 nanometer-50 nanometers.
The formation method of 14. semiconductor device as claimed in claim 1, it is characterized in that, the technique of described removal mask layer is dry etching, wet etching or chemico-mechanical polishing.
The formation method of 15. semiconductor device as claimed in claim 1, it is characterized in that, the material of described insulating barrier is silica.
The formation method of 16. semiconductor device as claimed in claim 15, it is characterized in that, the technique of described removal insulating barrier is wet etching, and described etching liquid is hydrofluoric acid, phosphoric acid, hydrogen fluorine nitric acid or hydrogen fluorine acetic acid.
The formation method of 17. semiconductor device as claimed in claim 1, it is characterized in that, the material of described mask layer is silicon nitride, silica or silicon oxynitride.
The formation method of 18. 1 kinds of transistors, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises: the insulating barrier of substrate, substrate surface and the semiconductor layer of surface of insulating layer;
Form some mask layers at described semiconductor substrate surface, described mask layer exposes part semiconductor substrate surface;
With described mask layer for mask, adopt the first anisotropic wet-etching technology to etch described semiconductor layer, in described semiconductor layer, form the first opening, described first opening exposes surface of insulating layer;
After formation first opening, remove described mask layer;
After the described mask layer of removal, adopt the second anisotropic wet-etching technology to etch described semiconductor layer, form the second opening in the semiconductor layer between adjacent first opening, described second opening exposes surface of insulating layer;
After formation second opening, remove partial insulative layer, form the nano wire be suspended on above substrate;
After removal insulating barrier, thermal annealing is carried out to described nano wire, makes the cross section of described nano wire become circle;
After thermal annealing, form gate dielectric layer in described nanowire surface;
Gate electrode layer is formed on described gate dielectric layer surface;
With described gate electrode layer for mask, in the Semiconductor substrate at described nano wire two ends, doping forms source/drain region.
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