CN103632717A - Digital static CMOS (Complementary Metal-Oxide-Semiconductor Transistor) element - Google Patents
Digital static CMOS (Complementary Metal-Oxide-Semiconductor Transistor) element Download PDFInfo
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Abstract
The invention discloses a digital static CMOS (Complementary Metal-Oxide-Semiconductor Transistor) element which works on voltage as low as possible in an off-position, and keeps levels of a register of a component and an internal state.
Description
Technical field:
The present invention relates to numeral and static CMOS integrated circuit, it is applied to microprocessor etc., and particularly for example integrated circuit by applying one in off-position, reduce a lot of supply voltages and reduce power consumption.
Background technology:
In high performance microprocessor is basic computer system, microprocessor is with higher clock speed work.Yet, conventionally and microprocessor carry out communication circuit, storer, peripherals, bus and input/output line with much lower speed operation.Generally, microprocessor remains on idle state, and the clock of processor keeps identical high work clock speed.Due to the direct relevant power consumption of clock frequency, work by this way and can consume energy very much.
When microprocessor is during in waiting status, some microprocessors are by entering power-down state limit dissipation power amount.Under off-position, integrated circuit component un-activation, but maintained the internal state of storer and element.Because for the time of the high-performance computer system in great majority application, microprocessor work is in off-position, an important current drain parameter is the consumption figures of power-off.Therefore, be necessary to reduce the current drain of power-off.Use three kinds of technology to realize the electric current storage of power-off: (1) is the clock signal of activation of microprocessor not, (2) stop the power supply of idle microprocessor, (3) reduce voltage level, its voltage level by idle microprocessor is reduced to minimum operational voltage level.
Use the first technology, when the activity of monitoring meets predefined level, to the activity of a cmos element monitor and inactive element in clock signal.Because frequency of operation has an important impact to power consumption, this technology has reduced power consumption effectively.Yet, even if work as frequency, be reduced to 0Hz, due to pull-up resistor, power is with the form consumption of standby leakage current or DC current.
The second technology, stops providing power to element, stops consuming alap power consumption to reach completely.Unfortunately, when power breakdown, comprise that the value of the storer of state variable is lost, storer and state variable must reset when power flash-up.The element that is reset to previous duty need to consume some times from element internal memory read value.In many application, the time of recovery can not allow.
Lower voltage to the 3rd technology of minimum operational voltage level prevents some power consumptions really, but because V
cCreference voltage level can not be reduced to and be less than about 3V, so saving amount is minimum.Because exterior I/O normal voltage is Transistor-Transistor Logic level, so the level of 3V is necessary, wherein, the output signal of integrated circuit should have the level of a 2.4V at high logic state.The cmos element of a standard has to operate at the voltage level of a standard, due to voltage drop and noise effect, its scope approximately from 3V to 3.6V, thereby drive Transistor-Transistor Logic level standard.
Therefore, people need a kind of better mode to reduce leakage current and power consumption.
Summary of the invention:
According in the first embodiment of the present invention, the method of a static cmos element of operation comprises the following steps: at two voltage level places, provide selectively a reference voltage, comprise an operational voltage level and a low reference voltage level, the step that the idle state of the static cmos element detecting and control are supplied with selectively provides low reference voltage in response to detected idle state.Low reference voltage level is lower than operational voltage level substantially, but enough voltage amplitudes keep the register of static cmos element and the level of internal state.
In an electronic system according to a second embodiment of the present invention, comprise that a programmable power supply optionally provides operating voltage and far below the low-voltage of operating voltage.This system also comprises a static cmos element, and it is connected to programmable power supply by a line of electric force that carries selected alternative voltage.This system also comprises a system controller, and its condition line by a power control line and indicator elment state is connected to programmable power supply, and this power control line selects to be applied to the voltage of static cmos element.
Technical solution of the present invention:
The reference voltage applying is reduced to possible minimum, the register of holding element and the level of internal state, thus realize several advantages.An advantage is that reduction voltage provides the extra work time and reduce general power consumption to system user in battery power supply system.Second advantage is that power supply component under off-position is without reset or the initialization of system state.Another advantage is the substandard reference voltage of reference voltage that cmos element is powered in power-off work, causes electric energy conservation, and simultaneous memory, register, trigger and state variable are generally guarded.Another one advantage is, although this system is saved electric energy by reducing lower than the reference voltage level of minimum operational voltage level, the signal with suitable voltage level utilize Transistor-Transistor Logic level stable be fed to input/output circuitry.Utilize these advantages to reach and save battery power supply system and the electric energy in the system of " power consumption rich and influential family " element.
Detailed description in conjunction with the following drawings, invention will be more fully understood.
The mixing SET/CMOS static storage cell 201220068913.3 of contrast patent documentation: CN202454287U based on negative differential resistance characteristic
Accompanying drawing explanation:
Figure 1 shows that the system block diagram of an embodiment of an electronic system, this system is operated in a low-down voltage level between turnoff time.
Figure 2 shows that static cmos element is with a process flow diagram of the method for a low-down voltage status operation.
Fig. 3 shows and determines that static cmos element is with the process flow diagram of the method for a suitable voltage of low-down voltage status operation.
Fig. 4 illustrates an embodiment system block diagram according to the electronic system shown in Fig. 1 programmable power supply.
Fig. 5 illustrates according to the system block diagram of the embodiment of the electronic system shown in Fig. 1 static cmos element.
Fig. 6 illustrates according to the system block diagram of an embodiment of the electronic system shown in Fig. 1 system controller.
Embodiment:
With reference to Fig. 1, the electronic system 100 of a system block diagram demonstration is applicable to being operated in low-down voltage level between turnoff time.Electronic system 100 comprises a programmable power supply 110, static cmos element piece 120 and a system controller 130.
Programmable power supply 110 comprises a circuit (not shown), and its output voltage signal arranging on power lead 112 changes along be applied to the function of a digital input signals of power control line 132 by system controller 130.Programmable power supply 110 comprises that several such voltage selecting circuits are independent of each other alternatively.Independently voltage selecting circuit is connected respectively to the several independent current source lines in power lead 112.It is not shown that several independent current source lines in power lead 112 are connected respectively to cmos element piece 120() several cmos elements, cause the system controller 130 can be individually and control independently the supply voltage of several cmos elements.
In certain embodiments, static cmos element piece 120 comprises a single cmos element, and it has the work energy that the single power supply line in power lead 112 provides.In other embodiments, static cmos element piece 120 comprises several cmos elements, and all the single power supply line in power lead 112 is supplied with work energy, and power lead 112 is for all element power supplies are so that identical voltage is applied to each element.In other embodiments, several cmos elements that static cmos element piece 120 comprises, its a plurality of power leads in power lead 112 provide operating power.In the embodiment of some a plurality of elements, a plurality of line of electric force, each element provides an independent power lead independently.In other a plurality of elements, a plurality of power lead embodiment, some power leads are shared between specific a plurality of element.In a further embodiment, all a plurality of static cmos elements have all adopted independent and independent power lead 112, and it powers and the voltage that independent power lead 112 applies is set independently of one another from programmable power supply 110.
The embodiment of a plurality of static cmos elements is passable, for example, comprises a CPU (central processing unit), as a microprocessor and an i/o controller.Because when service voltage is during lower than 3V, any digital element is embodied as the static cell that can work completely, so utilize static cmos element.Therefore,, during element off-position, utilize complete static cmos element the power supply of element can be brought down below to 3V.Element clock line 134, element input line 136, element output line 136 and idle state line 140 independent utility are to each static cmos element.
Therefore,, in different embodiment, one or more static cmos elements are connected to the various voltage selecting circuits in programmable power supply 110 by the various power leads in power lead 112.Voltage selecting circuit and power lead are different sharing, or independent use the between element.Each static cmos element is connected to system controller 130 by clock line 134, element input line 136 and the element output line 138 of an idle condition line 140, an element, it is independent of from the circuit of other element of a plurality of cmos elements, cause the control of each element in a plurality of static cmos elements to be independent of other static cmos element, even if power supply is to share between element.
With reference to the process flow diagram shown in Fig. 2, together with the circuit theory diagrams shown in Fig. 1, the method illustrating is the work that system controller 130 is controlled an element of static cmos element piece 120.System controller 130 is selectively for element provides an operational voltage level or low-voltage.Low voltage level is lower than operational voltage level substantially, but is enough to maintain the register of element and the level of internal state.In monitoring step 210, system controller 130 is monitored the activity of each element in static cmos element by detecting the idle state line 140 of each cmos element.After idle state is determined, system controller 130 determines whether the information of (not shown) on external bus is directed to an element, by the element in these element input line 136 monitoring input steps 212.Therefore, system controller 130 detects the idle state of a static cmos element, it is by determining whether the external bus (not shown) at static cmos element provides new information, and whether leave unused detected state by determining that the state of static cmos element is current, when fresh information, externally unavailable and static cmos element is current in bus while being idle state, and the state of static cmos element is divided into idle state.When static cmos element being detected and be idle state, in timeing closing step 214, system controller 130 is closed the timing signal of static cmos element and is controlled programmable power supply 110, in reducing voltage steps 216, gradually the voltage that is applied to idle static cmos element is reduced to low voltage level from operational voltage level.Voltage gradually reduce to avoid the ringing effect in element.When the voltage in output signal step 218 reduces, system controller 130 blocks signal on the output pin of static cmos element and in closing input signal step 220, forces signal on the input pin of static cmos element in idle state.
When lower voltage, signal on the output pin of static cmos element be prevented from and the input pin of static cmos element on signal be forced disarmed state, therefore, do not attempt driving outside Transistor-Transistor Logic level input/output driver circuit with the voltage that is less than 2.4V.In addition, a kind of cmos element technology from outside Transistor-Transistor Logic level I/O driving circuit isolation power-off relates to a lower voltage and moves inner cmos element and for example, move outside Transistor-Transistor Logic level I/O driving circuit with higher level (2.4V).Yet this technology utilizes two voltage sources or internal voltage regulator independently for inner cmos circuit and outside Transistor-Transistor Logic level input/output circuitry provide reference voltage.In addition, this technical disadvantages is to revise all elements of system 100.
In certain embodiments or under certain situation, low voltage level is defined by a system designer.In other embodiments, the low reference voltage of automatic calibration, thus for specific static cmos element, find a suitable low reference voltage.With reference to Fig. 3, show a kind of method for the low reference voltage of automatic calibration.In order to calibrate low voltage level, system controller 130 is controlled programmable power supply 110, thereby changes the voltage that is applied to static cmos element in the step 310 that changes voltage.In checking the step 312 of element function, system controller 130 checks the function of static cmos element for the voltage level of the specific various voltages that apply.More particularly, in some element, system controller 130 is controlled programmable power supply 110 and is changed and be applied to the voltage of static cmos element and check that for the voltage level of the specific various voltages that apply storer or the data in register in static cmos element retain.In circulation step 314, system controller 130 is branched off into the step 310 that changes voltage, unless found specific functional conditions.When finding the low-voltage structure condition of the specific definitions of an element, in the step 316 of next cmos element, system controller 130 checks a plurality of elements.If in the time of need to testing extra element, in the step 318 of initialization voltage, system controller 130 utilizes the operating voltage of new element and is branched off into the step 310 that changes voltage.If while there is no extra element test, system controller exits calibration steps in end step 320.The indivedual of different cmos elements allow different elements to work in different low power consumption voltages with independently calibrating, thereby make all idle elements in complete idle state, but suitably for all elements provide the voltage that can keep storer, register value and other functions.In system bootstrap routine work, system controller 130 is the low reference voltage of calibration conventionally.
With reference to Fig. 4, an embodiment of programmable power supply 110 comprises a reference voltage generator 410, voltage stabilizer 420 and a digital analog converter (DAC) 430.The National Semiconductor in the three-terminal voltage regulator ，Zhe Shiyou Santa Clara city that suitable voltage stabilizer 420 is LM117H/LM317HV manufactures.Reference voltage generator 410, for example the generator of 5 volts, provides the V of input voltage to voltage stabilizer 420
iN terminal.Voltage stabilizer 420 is at V
oUTterminal place provides output voltage, and it is connected to one or more electric wire in power lead 112.Illustrative DAC430 comprises npn bipolar transistor 432 and resistor R.Each npn bipolar transistor 432 is connected in series to resistance R and polynary transistor-resistor to being parallel between ground wire and node 434.This node 434 is connected to the V that voltage stabilizer 420 is adjusted terminal and is connected to voltage stabilizer 420 by a resistor R1
oUTterminal.Polynary transistor-resistor is to being also parallel to resistor R2.The base terminal of each transistor 432 is coupled to the dedicated line of the power control line 132 of system controller 130.In the polynary voltage embodiment of programmable power supply 110, the several circuit shown in Fig. 4 are used to the several threads road of power lead 112 that reference voltage is provided.
With reference to Fig. 5, an embodiment of a static cmos element 120 comprises 486 microprocessors 510, as the microprocessor of these Intel and the manufacture of advanced micro devices company.Microprocessor is at V
cCterminal place receives working power, and it is connected to the single line road of power lead 112 and receives a timing signal at a CLK terminal place, and it is connected to element clock line 134.From microprocessor 510, to system controller 130, produce idle state line 140, for example,, by an internal memory/input-output (M/IO#) pin of microprocessor 510, data/control (D/C#) pin and a Writing/Reading (W/R#) pin being connected to one three input NOT-AND gate 512.The output terminal of NOT-AND gate 512 is connected to idle state line 140.
With reference to Fig. 6, an embodiment of system controller 130 comprises a mode controller 610, recording controller 620, voltage controller 630 and a bus controller 640.This mode controller 610 is connected to idle state line 140.When idle signal is set, mode controller 610 interacts with bus controller 640, determines whether a data bus 650 transmits signals to cmos element.If do not have external data to be applied to cmos element, mode controller 610 is controlled a switch 612, and it disconnects a systematic clock generator 660 from element clock line 134.Then, this mode controller 610 interacts with voltage controller 630, in mode progressively, reduces the voltage that is applied to cmos element.The numerical coding that voltage controller 630 is applied to power control line 132 by change is carried out this process.This mode controller 610 interacts with recording controller 620, thereby makes the signal activation on element output line 138, and signal can not be placed on data bus 650 like this.In addition, mode controller 610 interacts with recording controller 620, thereby the signal being arranged on element input line 136 is inactive level signal.
It is illustrative rather than restriction that the description of some embodiment of the present invention is intended to.For those skilled in the art, many other embodiment are apparent, within all these is included in broad range of the present invention.Apparatus and method according to the present invention are not limited to the application program of microprocessor, but are also applicable to driving circuit and similar circuit that other various cmos elements comprise storer, interface, I/O controller, device.
Claims (8)
1. a digital still cmos element, it is characterized in that: the method for moving static cmos element comprises following steps: at two voltage level places, provide selectively a reference voltage, it comprises operational voltage level and far below the low reference voltage of operational voltage level, but is enough to keep register and the internal state level of static cmos element; Detect the idle state of static cmos element; Control supplying step selectively, thereby provide low reference voltage and in response to the detection of idle state; Calibration be included in a system in the relevant low reference voltage of static cmos element in the child-operation that operates of guiding; Method is further comprising the steps: the timing signal of the static cmos element of stopping using, in response to the idle state of the static cmos element detecting; This control step comprises the following steps: control supplying step selectively, thereby voltage is reduced to low voltage level from operational voltage level, arrive subsequently timing signal and activate step; Method is further comprising the steps of: block the signal on the output pin of static cmos element, thus the idle state of the static CMOS that response detects, simultaneously lower voltage.
2. a kind of digital still cmos element according to claim 1, is characterized in that: the method is further comprising the steps of: block the signal on the output pin of static cmos element, thus the idle state of the static CMOS that response detects; Force signal on the input pin of static cmos element in idle state, in response to the idle state of the static cmos element detecting; The step of described detection idle state comprises the following steps: determine that externally whether bus is available to the information on static cmos element; Determine that whether static cmos element is at present in idle state; When new information is when externally unavailable and static cmos element is idle at present in bus, by the state classification of static cmos element, be idle state; Wherein, calibrating low reference voltage comprises the following steps: change the voltage that is applied to static cmos element; Specific voltage level for different voltages, checks the reservation of data in the storer in static cmos element.
3. a kind of digital still cmos element according to claim 2, is characterized in that: calibrate low reference voltage and comprise the following steps: change the voltage that is applied to static cmos element; For the specific voltage level of different voltages, check the function of static cmos element; Wherein, the supply of multi-component static cmos element, detection and control step are independently to carry out; The method is further comprising the steps: calibration and each relevant low reference voltage in multi-component static cmos element, and it is independent of each corresponding static cmos element; An electronic system, it comprises: static cmos element; A programmable power supply is coupled to static cmos element by a wire, and programmable power supply provides operating voltage to selectively static cmos element and far below the low-voltage of operating voltage, but is enough to keep register and the internal state level of static CMOS; A system controller is coupled to programmable power supply by power control line, for selecting provided voltage and the condition line by an indicator elment state to be coupled to static cmos element, system controller calibration be included in a system in the relevant low reference voltage of static cmos element in the child-operation that operates of guiding; Wherein, described system controller is further coupled to static cmos element by an element clock line, and it is cmos element supply timing signal; Described system controller is coupled to static cmos element by an element input line and an element output line, and it is respectively from system controller to cmos element and from cmos element to system controller signal transmission; In described system, static cmos element is the first element in multi-component static cmos element; Wherein, described multi-component static cmos element comprises a CPU (central processing unit) (CPU) and an i/o controller.
4. a kind of digital still cmos element according to claim 1, it is characterized in that: described static cmos element is the first element of multi-component static cmos element, each static cmos element is coupled to programmable power supply by a power lead, power lead and each static cmos element that this power lead is independent of other elements of multi-component static cmos element pass through a condition line, an element clock line, an element input line and an element output line are coupled to system controller, cause each in multi-component static cmos element to be independent of the controlled and power supply of other static cmos element, the static cmos element of described system also comprises: a detecting device, for monitoring the idle indication of static cmos element, the system controller of described system also comprises: a mode controller, for optionally activating and not activating the timing signal of static cmos element, a voltage controller, for selecting the power signal of an application between operating voltage and the low-voltage far below operating voltage, a recording controller, for blocking signal response on the output pin of static cmos element in the idle state of the static cmos element detecting, a recording controller, for forcing signal on the input pin of static cmos element in idle state, in response to the idle state of the static cmos element detecting.
5. a kind of digital still cmos element according to claim 1, it is characterized in that: the method for moving a static cmos element comprises following steps: at polynary voltage level place, optionally provide a reference voltage, comprise an operational voltage level and far below the low reference voltage of operational voltage level, but be enough to keep the register of static cmos element and the level of internal state; Detect the idle state of static cmos element; Control the step of supplying with selectively, it provides low reference voltage in response to the idle state detecting; By providing low reference voltage to keep the register of static cmos element and the level of internal state; Calibration be included in a system in the relevant low reference voltage of static cmos element in the child-operation that operates of guiding.
6. a kind of digital still cmos element according to claim 1, is characterized in that: a kind of electronic system, comprising: static cmos element; A programmable power supply is coupled to static cmos element by a wire, programmable power supply provides operating voltage to selectively static cmos element and far below the low-voltage of operating voltage, but is enough to keep register and the internal state level of static cmos element; A system controller is coupled to programmable power supply by power control line, for selecting provided voltage and the condition line by an indicator elment state to be coupled to static cmos element, this system controller comprises: steering logic is by selecting low-voltage far below operating voltage in response to the idle state on condition line, this low-voltage is enough to keep the register of static cmos element and the level of internal state, the calibration of this steering logic be included in a system in the relevant low reference voltage of static cmos element in the child-operation that operates of guiding.
A kind of digital still cmos element according to claim 1 under power-down mode with the method and apparatus of a low-down voltage mode job, it is characterized in that: the method for moving a static CMOS processor comprises the following steps: at polynary voltage level place, optionally supply with a reference voltage, comprise an operational voltage level and far below the low reference voltage of operational voltage level, but be enough to keep the register of static CMOS processor and the level of internal state; Detect the idle state of static CMOS processor; Control the step of supplying with selectively, provide low reference voltage in response to the idle state detecting; By providing low reference voltage to keep the register of static CMOS processor and the level of internal state; Calibration be included in a system in the relevant low reference voltage of static CMOS processor in the child-operation that operates of guiding.
8. a kind of digital still cmos element according to claim 1, with the method and apparatus of a low-down voltage mode job under power-down mode, is characterized in that: a kind of electronic system, comprising: a static CMOS processor; A programmable power supply is coupled to static CMOS processor by a wire, programmable power supply provides operating voltage to selectively static CMOS processor and far below the low-voltage of operating voltage, but is enough to keep the register of static CMOS processor and the level of internal state; A system controller is coupled to programmable power supply by power control line, for selecting provided voltage and the condition line by an indicator elment state to be coupled to static cmos element, this system controller comprises: steering logic is by selecting low-voltage far below operating voltage in response to the idle state on condition line, this low-voltage is enough to keep the register of static CMOS processor and the level of internal state, the calibration of this steering logic be included in a system in the relevant low reference voltage of static CMOS processing apparatus in the child-operation that operates of guiding.
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| CN1118530A (en) * | 1994-07-11 | 1996-03-13 | 美国3M公司 | Overvoltage protection circuit |
| US5852737A (en) * | 1995-04-24 | 1998-12-22 | National Semiconductor Corporation | Method and apparatus for operating digital static CMOS components in a very low voltage mode during power-down |
| CN101842846A (en) * | 2007-12-20 | 2010-09-22 | 莫塞德技术公司 | Dual function compatible non-volatile memory device |
| CN102651237A (en) * | 2011-02-28 | 2012-08-29 | 三星电子株式会社 | Nonvolatile memory device, memory system including the same, and method of operating nonvolatile memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1118530A (en) * | 1994-07-11 | 1996-03-13 | 美国3M公司 | Overvoltage protection circuit |
| US5852737A (en) * | 1995-04-24 | 1998-12-22 | National Semiconductor Corporation | Method and apparatus for operating digital static CMOS components in a very low voltage mode during power-down |
| CN101842846A (en) * | 2007-12-20 | 2010-09-22 | 莫塞德技术公司 | Dual function compatible non-volatile memory device |
| CN102651237A (en) * | 2011-02-28 | 2012-08-29 | 三星电子株式会社 | Nonvolatile memory device, memory system including the same, and method of operating nonvolatile memory device |
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