CN103618543A - High-speed CMOS buffer with TTL level input - Google Patents

Abstract

Disclosed is a high-speed CMOS buffer with TTL level input. A CMOS integrated circuit is made compatible with a TTL input signal. A voltage stabilizer makes a CMOS gate work in an array slightly lower than a supply voltage. A voltage stabilizer sensing circuit responds to a working gate and a TTL offset reference. Therefore, changes of surrounding environment conditions and production changes can be compensated for by the voltage stabilizer, and accordingly a gate array device can reliably responds to a TTL level switch signal.

Description

A kind of high-speed cmos buffer of Transistor-Transistor Logic level input

Technical field

The present invention relates to complementary metal oxide semiconductors (CMOS) (CMOS) structure, a large amount of door that particularly those relate to is made into a single integrated circuit (IC) chip.

Background technology

Such array door is used for making logic gates, thereby door wherein interconnects, realizes required logic function.The problem of a puzzlement is that such array is the changeability as the function of environmental condition and the door performance in manufacture process.

Summary of the invention

An object of the present invention is to set up a control circuit to CMOS integrated circuit, wherein said door causes responding TTL signal.A further object of the present invention is the supply voltage changing on CMOS integrated circuit, it is characterized in that, all door response TTL logic levels, and no matter the variation in environmental condition or manufacture.A further object of the present invention is on the power line of CMOS integrated circuit, to use a pressurizer, and pressurizer is in response to a typical gate biasing of TTL logic level operation.Technical solution of the present invention:

Being achieved as follows of these and other objects.A typical gate in array provides reference input voltage, and it is that TTL compatibility is selected.The output of door must the supply voltage of this reference input 1/2nd in operation.Series connection breakover element is coupling between the power line and power input of integrated circuit, and its conductivity is relevant with typical door output.When the output of typical gate surpasses

, conductive device presents poor conductivity, thereby has reduced array power supply voltage.When output is less than , conducting presents good conductivity, thereby has improved array power supply voltage.This negative feedback arrangement has been determined typical gate output, even in the large variation in the face of in environment and manufacturing process.

We have found that the above-mentioned adjusting at the such array that conventionally runs into the variation in CMOS manufacture of compensation is effectively, and have at least at array power supply voltage ± 10% variation.Although emphasis is gate array, the present invention is equally applicable to any CMOS integrated circuit (IC) system, the system of its access TTL compatible, and accept input from such TTL system.

Contrast patent documentation: CN1054850A has low-power, the Transistor-Transistor Logic level CMOS input buffer 90110236.9 of retardation.

Accompanying drawing explanation:

Figure 1 shows that the schematic diagram of primary element of the present invention.

Figure 2 shows that the present invention only uses the schematic diagram of another embodiment of MOS active device.

Figure 3 shows that the schematic diagram of another alternate embodiments of the present invention.

Figure 4 shows that the schematic diagram of another alternate embodiments of the present invention.

Figure 5 shows that the schematic diagram of the typical circuit adopting in the amplifier 24 of Fig. 4.

Figure 6 shows that foundation

the schematic diagram of circuit of reference voltage.

Another that Figure 7 shows that all MOS of the present invention adopts the schematic diagram of the alternate embodiments of P trap CMOS structure.

Figure 8 shows that the schematic diagram of the N-trap CMOS that realizes Fig. 7 embodiment of the present invention.

Embodiment:

Fig. 1 shows basic circuit of the present invention.A shared power supply v _ccbe coupling between positive terminal 10 and earth terminal 11.The level of a minimizing offer array 12, it represents a large amount of gates, and it can find in a gate array.Such a door is shown in dotted outline.But should be understood that, while being applied to gate array in a preferred embodiment, the present invention can be used for the construction that any TTL of needs inputs compatible CMOS integrated circuit.

Door 13 is typical doors and be coupled and formed as a CMOS inverter gate by p channel transistor 14 and N-channel transistor 15 in array.Node 17 keeps anti-phase logic state with respect to the logic state of terminal 16.Yet this reference or switch level can be different.Generally, the reference level of CMOS is

.Logical one approaches + v _cc and logical zero is current potential closely.In TTL, it generally designates the power supply for being operated in 5 volts, and input logic " 1 " normally surpasses 2 volts and logical zero and is less than 0.8 volt.The switch reference value of the centre between these values is 1.4 volts.In the circuit of Fig. 1, if a DC reference voltage v _rEF be coupled to terminal 16, install 14 and 15 conduction and can be adjusted at node 17 places

thereby the performance level of circuit is set.For example, when TTL compatibility needs, use 1.4 volts v _rEF and installing 19 and 20 formed inverters is in the region of a high-gain.The object of design inverter gate 18 is to provide a level shift, thus one of node 21 places input slightly lower than v _ccthe output of 2.5 volts.This can be by realizing p channel transistor 19 substantially than the easier conducting of N-channel transistor 20.

The structure of ambipolar NPN transistor 22 is used cmos element, is known in the art, and as a variable, transmits device.Its conduction is by from terminal 10 v _ccby electric current, arrive node 23

.Substantially at any voltage at node 21 places,

to be lower than it one v _bE .Semiconductor 22 is as the emitter follower changing with a diode drop.Therefore with TTL logic and v _ccat 5 volts, approximately 4.9 volts of node 21 operating voltages, be about 4.2 volts.Normally,

keep efficient and practical, to improve to greatest extent the speed of door in array.

Can find out, the reason that node 23 regulates is that it is comprised in a high-gain negative feedback loop.Inverter 18 provide reversion and it there is higher gain.Transistor 22 has current gain and homophase as emitter follower.This circuit will take to set the voltage levvl of node 23, and making node 17 is the trip point places at door, for TTL supply level normally

or approximately 2.5 volts.

Due to

transistor 22 is used in acquisition v _bE , pressurizer output is by the temperature coefficient that shows approximately 2 millivolts every degree Celsius.Therefore, the circuit of Fig. 1 can automatically will

adjust the variation of compensation surrounding environment condition of work.This circuit will compensate to change processes cmos device, conventionally the trigger point of transfer gate.Therefore, cmos gate array can with TTL compatible.If necessary, can adopt some other selected logics configuration and set up one suitable v _rEF level.

Fig. 2 illustrates a kind of alternative circuit embodiments.The bipolar transistor 22 of Fig. 1 is replaced and connects as source follower by N-channel transistor 25.Thereby it only need to make transistor 25 enough greatly by

by required electric current, offer input gates all in array.

Fig. 3 illustrates the second alternate embodiments, and in this embodiment, the output of inverter 18 provides power supply.The emitter follower of Fig. 1 and the source follower of Fig. 2 are omitted.The node 21 of Fig. 1 and Fig. 2 is to be directly connected to

.Because P-channel transistor 19 need to provide gate array electric current, thereby it needs enough to meet greatly total current requirement.In this configuration, it may omit transistor 20.

Fig. 4 shows a more complicated alternative circuit embodiments.Here adopted differential operational amplifier (op amp) 24.Terminal 25 places second or v _rEF be applied to noninverting input.Selected output node 21 conventionally approach lower than v _cc a P raceway groove threshold value, it is directly coupled to the base stage of transistor 22.In TTL compatible configuration, v _cc power supply can supply resistor 26-28, and it is because essence adds washability dotted line.If these resistors are made into respectively the definite value of 25K, 11K, 14K ohm, v _rEF be 1.4 volts and v _rEF2 to be 2.5 volts.These resistors will consume 500 milliwatts and flow into the electric current of approximately 100 microamperes.This circuit is adjusted to voltage

(node 23) thus make the anti-phase input of operational amplifier 24 and homophase input equates.Due to operational amplifier 24, can make and have very high gain, such circuit is quite stable.

Figure 5 shows that the cmos circuit being suitable for as Fig. 4 operational amplifier 24.The N-channel transistor 29 of coupling is connected with 30 as a differential pair, and its end current is provided by N-channel transistor 31.The bias voltage that is coupled to terminal 32 will make transistor 31 by required end current.Transistor 33 and 34 is the P-raceway groove load equipments that are connected in current mirror configuration, and it can provide a Single-end output at node 21 places.The input 35 of this circuit forms in-phase input end, and terminal 36 forms inverting input.

Fig. 6 still comprises another embodiment of the present invention.This configuration is similar to the embodiment of Fig. 4, but the in-phase input end of operational amplifier 24 obtains from an inverter gate 37.Output and input that this inverter gate has connect together, and it is approaching like this

the work of trigger point place.This means, as long as at terminal 16 places v _rEF be 1.4 volts, circuit is TTL compatible; Otherwise this circuit function can be worked in the roughly the same mode of Fig. 4.

Fig. 7 illustrates another alternate embodiments of the present invention, uses the layout that is similar to Fig. 2.Cmos device is that structure and the N-channel transistor 25 of P trap is adjusted in the electromotive force at node 23 places as source follower.Transistor 38 is as a current mirror of node 39, and it is

Power supply.If transistor 25 and 39 couplings, node 23 and 39 is at identical current potential.This configuration is useful especially, wherein at 12 places, has many doors to be controlled.In fact, transistor 38 is controlled as a fan-out.

Fig. 8 is N-trap CMOS construction drawing version conventional in Fig. 7.The door at N- channel transistor 40 and 41 back sides accesses ground in this embodiment, and it is the substrate terminal of integrated circuit.

Several alternative embodiment of the present invention has been described.Obviously, within the scope of the principle of the invention and object, those skilled in the art, after reading above-mentioned explanation, also have other alternative scheme and equivalent.For example, although Fig. 4 and Fig. 6 have shown, use an ambipolar turn-on transistor, obviously, it may be a N-channel transistor as shown in Figure 2, P-channel transistor as shown in Figure 3.Therefore, the scope of application of the present invention is only by the restriction of claims.

Claims (9)

1. the high-speed cmos buffer of Transistor-Transistor Logic level input, it is characterized in that: in a kind of CMOS integrated circuit, to have a door at least be design the conversion of a predetermined output reference level and and other a large amount of Men Yi multiple power sources in work, improved compensation will be worked in voltage stabilizing current potential separated in described Men Cong multiple power source and be different from the variation of working temperature and process parameter, and the described input terminal being had by the electromotive force of the definite adjusting of representative operation door is coupled to the reference potential of a TTL compatible.

2. the high-speed cmos buffer that a kind of Transistor-Transistor Logic level according to claim 1 is inputted, it is characterized in that: described voltage stabilizing current potential obtains from voltage regulator circuit, it comprises: variable breakover element, is coupling in the switch level that described public power and described door can change described door thus; And for the different electricity of described breakover element, lead the variation that represents the difference between cleaning door and the output potential of described reference level current potential in response to described.

3. the high-speed cmos buffer of a kind of Transistor-Transistor Logic level input according to claim 2, is characterized in that: describedly for changing, comprise the second operation door and typical operation door cascade coupled and have a large amount of amplifications.

4. the high-speed cmos buffer of a kind of Transistor-Transistor Logic level input according to claim 3, is characterized in that: the active device that described the second operation door has produces a large amount of level shifts, thereby produces the level that approaches described public power supply ratio v _cC specified output high level.

5. the high-speed cmos buffer that a kind of Transistor-Transistor Logic level according to claim 2 is inputted, it is characterized in that: wherein said modifying device, for the method changing, comprise a differential operational amplifier, its output having is coupled to described variable breakover element, and an inverting input is coupled to described typical output and a non-inverting input that moves door and is coupled to an output potential that represents the operation level of required operation door.

6. the high-speed cmos buffer of a kind of Transistor-Transistor Logic level input according to claim 5, is characterized in that: described variable-conductance breakover element is a NPN bipolar transistor.

7. the high-speed cmos buffer of a kind of Transistor-Transistor Logic level input according to claim 5, is characterized in that: described variable-conductance breakover element is the field-effect transistor of a N-raceway groove.

8. the high-speed cmos buffer of a kind of Transistor-Transistor Logic level input according to claim 5, is characterized in that: the logical element of described variable-conductance is the field-effect transistor of a P raceway groove.

9. the high-speed cmos buffer of a kind of Transistor-Transistor Logic level input according to claim 1, is characterized in that: described structure comprises a gate array, and wherein the threshold value of a plurality of manufactures and a plurality of switches is to be subordinated to described representational operation door.

Images