CN103616840A - Speed self-adaptive measuring device based on FPGA (Field Programmable Gata Array) - Google Patents
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Abstract
The invention discloses a speed self-adaptive measuring device based on FPGA (Field Programmable Gata Array). An FPGA chip at least comprises a quadruplicated frequency unit, a frequency divider A, a delay unit, a counter, a zero speed detection unit, a latch A, a self-adaptive controller, a latch B and a bus interface unit, wherein the frequency divider A carries out 2Pe frequency division on a quadruplicated frequency signal Mul; a frequency division coefficient index Pe and the counting clock signal Dclock of the counter are obtained by coding the time count value output by the counter through the self-adaptive controller. The speed self-adaptive measuring device disclosed by the invention can be used for self-adaptively changing the speed measurement period and the frequency of the counting clock signal Dclock through the self-adaptive controller according to different speed by using the quadruplicated frequency signal Mul as the detection signal of speed measurement, can effectively shorten the response time of low speed measurement and reduce the power consumption of a system under the precondition of ensuring speed measuring accuracy, can be applied to the measurement of low speed, medium speed and high speed, is simple and flexible in circuit and is especially suitable for a control system with a very high instantaneity requirement and a low power consumption requirement.
Description
Technical field
The present invention relates to the velocity survey field of servo driving and control system, relate in particular a kind of speed based on incremental optical-electricity encoder and detect and the speed adaptive measurement mechanism based on FPGA.
Background technology
At present, incremental optical-electricity encoder is widely applied in many fields such as industrial automation, aviation, automobile, numerically-controlled machine, machining center, navigational system, robots, and it is used to do the measurement of speed feedback and position feedback.At present, processing photoelectric encoder signal is realized speed measurement method and is mainly contained T method, M method, M/T method.T ratio juris is the time interval of measuring adjacent two feedback pulses; M ratio juris is the feedback pulse number of measuring unit in the time interval; M/T method principle is to measure the time under an integer umber of pulse in specific time interval internal feedback umber of pulse and this time interval simultaneously.T method is applicable to low speed and measures occasion, and M method is applicable to measure occasion at a high speed, and M/T method has good accuracy in the whole range of speeds.But M/T method is longer detection time during low speed, cannot meet the requirement of the fast dynamic response of speed detection system, and while adopting above-mentioned 3 kinds of methods to carry out velocity survey can not according to different speed adaptives change measuring period.
In order to make the velocity survey cycle can be according to friction speed adaptively modifying, researchist have carried out large quantity research to the velocity survey based on incremental optical-electricity encoder both at home and abroad.China Patent Publication No. CNl02680726A, open day on 09 19th, 2012, the name of innovation and creation is called a kind of high-accuracy self-adaptation device for motor speed measurement, this application discloses the motor speed self-adapting measuring method based on FPGA, and the method is by estimating the adaptively modifying tachometric survey cycle in cycle of orthogonal signal; < < High-Performance Position Detection and Velocity Adaptive Measurement for Closed-Loop Position Control > > (1998 08 month the 47th the 4th phase of volume) and the < < Adaptive High-Performance Velocity Evaluation Based on a High-Resolution Time-to-Digital Converter > > (2008 09 month the 57th the 9th phase of volume) of the TRANSACTIONS ON INSTRUMENTATIONAND MEASUREMENT of IEEE-USA (IEEE) disclose a kind of speed adaptive measuring method based on FPGA, the method is by estimating the adaptively modifying velocity survey cycle in cycle of orthogonal signal, the < < Accurate velocity evaluation using adaptive sampling interval > > of Microprocessors and Microsystems the 24th volume of Elsevier Science discloses a kind of speed adaptive measuring method based on FPGA, the method carries out by the high M position to time counter the initial value that decoding obtains the impulse meter in next velocity survey cycle, thus the adaptively modifying velocity survey cycle.Above-mentioned document has following common weak point:
(1) the velocity survey cycle long, when low speed is measured, all more than a few tens of milliseconds, while measuring at a high speed, be all more than several milliseconds.And the speed control cycle of some high real-time systems only has several milliseconds (such as the speed ring cycle of servo-driver), therefore existing speed adaptive measuring method can not meet the requirement of high real-time system far away.
(2) near velocity survey cycle saltus step critical velocity of existing speed adaptive measuring method, makes near the speed of critical velocity detect unstable.
(3), in prior art, for the high-frequency clock frequency of Measuring Time, remain unchanged always.Meeting under the prerequisite of measuring accuracy requirement, the high-frequency clock frequency that suitably reduces low speed segment can reduce the power consumption of system.
Summary of the invention
The present invention seeks near the problem for solve long, velocity survey cycle in velocity survey cycle the high-frequency clock frequency of saltus step and Measuring Time remains unchanged critical velocity always, thereby proposed a kind of speed adaptive measurement mechanism based on FPGA.
Technical scheme of the present invention is summarized as follows:
A speed adaptive measurement mechanism based on FPGA, at least comprises crystal oscillating circuit 1, encoder interfaces and modulate circuit 2, fpga chip 3 and microprocessor 4; Described fpga chip 3 at least comprises quadruple unit 31, frequency divider A32, delay unit 33, counter 34, zero velocity detecting unit 35, latch A36, adaptive controller 37, latch B38 and Bus Interface Unit 39; Described adaptive controller 37 at least comprises code translator A371, arbiter 372, code translator B373, frequency divider B374 and latch C375.
The time counting value Tn of described latch A36 output is input to respectively adaptive controller 37 and Bus Interface Unit 39; The divide ratio indices P e of described adaptive controller 37 outputs is input to respectively frequency divider A32 and latch B38; The clock division coefficient index Te of described adaptive controller 37 outputs is input to Bus Interface Unit 39; The clock signal Dclock of described adaptive controller 37 outputs is input to the input end clk of counter 34; The divide ratio indices P n of described latch B38 output is input to respectively adaptive controller 37 and Bus Interface Unit 39.
The divide ratio indices P n that the input end of the code translator A371 of described adaptive controller 37 is exported with time counting value Tn, the latch B38 of latch A36 output is respectively connected with the clock division coefficient index Te of latch C375 output; The input end of described arbiter 372 is connected with the latch signal Lat of frequency divider A32 output with the output terminal of code translator A371, the reset signal Clr of delay unit 33 outputs respectively; The input end of described code translator B373 is connected with the divide ratio indices P e of arbiter 372 outputs; The latch signal Lat that the input end of described frequency divider B374 is exported with clock division coefficient index D e, the frequency divider A32 of code translator B373 output is respectively connected with the clock signal C lock of crystal oscillating circuit 1 output; The input end of described latch C375 is connected with the latch signal Lat of frequency divider A32 output with the clock division coefficient index D e of code translator B373 output respectively; The signal of described arbiter 372 outputs is divide ratio indices P e; The signal of described code translator B373 output is clock division coefficient index D e; The signal of described latch C375 output is clock division coefficient index Te; The signal of described frequency divider B374 output is clock signal Dclock.
When the latch signal Lat of described frequency divider 32 outputs is effective, latch A36 is latched as the zero velocity marking signal Vz of the time counting value of counter 34 outputs and 35 outputs of zero velocity detecting unit the time counting value Tn of latch A36 output, latch B38 is latched as the divide ratio indices P e of the arbiter of adaptive controller 37 372 outputs the divide ratio indices P n of latch B38 output, and latch C375 is latched as the clock division coefficient index D e of code translator B373 output the clock division coefficient index Te of latch C375 output; The most significant digit of the time counting value Tn of latch A36 output is the zero velocity marking signal Vz of zero velocity detecting unit 35 outputs; By latch signal Lat synchronously latch processing, guaranteed that divide ratio indices P n, time counting value Tn, clock division coefficient index Te and zero velocity marking signal Vz are under the jurisdiction of the measured value in same measuring period.
The orthogonal signal of the incremental optical-electricity encoder output of the 31 pairs of inputs in quadruple unit of described fpga chip 3 are carried out quadruple processing, obtain quadruple signal Mul.
The frequency divider A32 of described fpga chip 3 carries out 2 to the quadruple signal Mul of input
pefrequency division, Pe is natural number, Pe is by arbiter 372 outputs of adaptive controller 37.
Described code translator A371 carries out after right-shift operation other position except most significant digit the time counting value Tn of latch A36 output, then carries out decoded operation; The divide ratio indices P n that the figure place that the time counting value Tn of the 371 couples of latch A36 of described code translator output carries out right-shift operation equals latch B38 output adds the maximal value De of the clock division coefficient index D e of code translator B373 output
maxdeduct again the clock division coefficient index Te of latch C375 output.
The arbiter 372 of described adaptive controller 37 is the decoding value of the code translator A371 output of former and later two measuring periods relatively, if the decoding value of the code translator A371 of former and later two measuring periods output is equal, the divide ratio indices P e of arbiter 372 outputs equals the decoding value of code translator A371 output; If former and later two measuring periods, the decoding value of code translator A371 output was unequal, the divide ratio indices P e of arbiter 372 outputs remains unchanged.
Described code translator B373 carries out decoded operation to the divide ratio indices P e of arbiter 372 outputs, obtains the clock division coefficient index D e of frequency divider B374, and De is natural number.
Described frequency divider B374 carries out 2 to the clock signal C lock of crystal oscillating circuit 1 output
defrequency division, obtains clock signal Dclock; When the latch signal Lat of frequency divider A32 output is effective, the frequency divider B374 reset zero clearing of described adaptive controller 37.
Described microprocessor 4 reads the time counting value Tn of divide ratio indices P n, latch A36 output of latch B38 output, the zero velocity marking signal Vz of the clock division coefficient index Te of adaptive controller 37 outputs and 35 outputs of zero velocity detecting unit from fpga chip 3 by Bus Interface Unit 39, and according to following formula (1-1) computing velocity value V.
In formula (1-1), V is speed, and unit is rpm (r/min) or millimeter per minute (mm/min); M is that scrambler Xian Shuo， unit is line/turn or line/mm; T
clkfor the cycle of clock signal C lock, unit is second (s).
The beneficial effect that the present invention compared with prior art has:
(1) the present invention uses the quadruple signal of orthogonal signal of increment photoelectric coding output as the detection signal of velocity survey, the velocity survey time in the time of can effectively reducing low speed, improves the real-time of velocity survey.
(2) the present invention does not need the cycle of the orthogonal signal of increment photoelectric coding output just to estimate and can, according to the friction speed adaptively modifying velocity survey cycle, realize the continuous coverage of velocity survey.
(3) the present invention uses arbiter to make near not saltus step critical velocity of velocity survey cycle, and near speed critical velocity detects reliable and stable.
(4) clock frequency of Measuring Time of the present invention can change with different speed intervals, meeting under the prerequisite of measuring accuracy requirement, low speed segment is used low-speed clock Measuring Time, and high regime is used high-frequency clock Measuring Time, can reduce the requirement of system power dissipation.
Accompanying drawing explanation
Fig. 1 is a kind of speed adaptive testing circuit technical scheme the general frame based on FPGA
Fig. 2 is the technical scheme figure of adaptive controller of the present invention and implements illustration
Fig. 3 is the schematic diagram that is related between clock signal C lock, the orthogonal signal A of the embodiment of the present invention and B, quadruple signal Mul
Fig. 4 is the schematic diagram that is related between the quadruple signal Mul, latch signal Lat, reset signal Clr of the embodiment of the present invention
Fig. 5 is the schematic diagram that is related between the clock signal C lock of the embodiment of the present invention and clock signal Dclock
Fig. 6 is the schematic diagram that is related between the latch signal Lat of the embodiment of the present invention and clock signal Dclock
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
With reference to figure 1, a kind of speed adaptive measurement mechanism based on FPGA of the embodiment of the present invention, at least comprises crystal oscillating circuit 1, encoder interfaces and modulate circuit 2, fpga chip 3 and microprocessor 4; Described fpga chip 3 at least comprises quadruple unit 31, frequency divider A32, delay unit 33, counter 34, zero velocity detecting unit 35, latch A36, adaptive controller 37, latch B38 and Bus Interface Unit 39; The time counting value Tn of latch A36 output is input to respectively adaptive controller 37 and Bus Interface Unit 39; The divide ratio indices P e of adaptive controller 37 outputs is input to respectively frequency divider A32 and latch B38; The clock division coefficient index Te of adaptive controller 37 outputs is input to Bus Interface Unit 39; The clock signal Dclock of adaptive controller 37 outputs is input to the input end clk of counter 34; The divide ratio indices P n of latch B38 output is input to respectively adaptive controller 37 and Bus Interface Unit 39.
As shown in Figure 2, adaptive controller 37 at least comprises code translator A371, arbiter 372, code translator B372, frequency divider B374 and latch C375; The divide ratio indices P n that the input end of code translator A371 is exported with time counting value Tn, the latch B38 of latch A36 output is respectively connected with the clock division coefficient index Te of latch C375 output; The input end of arbiter 372 is connected with the latch signal Lat of frequency divider A32 output with the output terminal of code translator A371, the reset signal Clr of delay unit 33 outputs respectively; The input end of code translator B373 is connected with the divide ratio indices P e of arbiter 372 outputs; The latch signal Lat that the input end of frequency divider B374 is exported with clock division coefficient index D e, the frequency divider A32 of code translator B373 output is respectively connected with the clock signal C lock of crystal oscillating circuit 1 output; The input end of latch C375 is connected with the latch signal Lat of frequency divider A32 output with the clock division coefficient index D e of code translator B373 output respectively; The signal of arbiter 372 outputs is divide ratio indices P e; The signal of code translator B373 output is clock division coefficient index D e; The signal of latch C375 output is clock division coefficient index Te; The signal of frequency divider B374 output is clock signal Dclock.34 couples of clock signal Dclock of counter count processing.
Be illustrated in figure 3 the schematic diagram that is related between clock signal C lock, the orthogonal signal A of the embodiment of the present invention one and B, quadruple signal Mul.The orthogonal signal A of 31 pairs of quadruple unit encoder interfaces and modulate circuit 2 outputs and B carry out quadruple and process acquisition quadruple signal Mul.If the line number of incremental optical-electricity encoder is M, unit is line/mm or line/turn, one millimeter of the every movement of incremental optical-electricity encoder or revolve the orthogonal signal A of the output of turning around and the pulse number of the quadruple signal Mul that B export behind quadruple unit 31 is that 4 * M is individual.
Be illustrated in figure 4 the schematic diagram that is related between the quadruple signal Mul, latch signal Lat, reset signal Clr of the embodiment of the present invention.In Fig. 4, the cycle of the clock signal C lock of crystal oscillating circuit 1 output is T
clk, unit is second (s); Between adjacent two pulses of quadruple signal Mul, be spaced apart P, frequency divider A32 carries out 2 to the quadruple signal Mul of input
pefrequency division, is spaced apart 2 between adjacent two pulses of the latch signal Lat of frequency divider A32 output
pe* P, frequency divider A32 carries out 2 to quadruple signal Mul
pefrequency division; The reset signal Clr of delay unit 33 output is than the lagged behind period T of a clock signal C lock of latch signal Lat
clk, object is to wait for that latch signal Lat has latched rear ability to counter 34 clear operation that resets by the time measured value of counter 34 outputs.Interval between interval between adjacent two pulses of latch signal Lat or adjacent two pulses of reset signal Clr is the measuring period of velocity survey.
Be illustrated in figure 5 the schematic diagram that is related between the clock signal C lock of the embodiment of the present invention and clock signal Dclock.Frequency divider B374 carries out 2 to the clock signal C lock of crystal oscillating circuit 1 output
defrequency division, obtains clock signal Dclock, so the cycle of clock signal Dclock is 2
de* T
clk, unit is second.
Be illustrated in figure 6 the schematic diagram that is related between the latch signal Lat of the embodiment of the present invention and clock signal Dclock.When the latch signal Lat of frequency divider A32 output is effective, the frequency divider B374 reset zero clearing of described adaptive controller 37, has guaranteed that the cycle of the clock signal Dclock in each measuring period is the same.
Code translator A371 in the embodiment of the present invention carries out after right-shift operation other position except most significant digit the time counting value Tn of latch A36 output, then carries out decoded operation; The code translator A371 divide ratio indices P n that other figure place of carrying out right-shift operation except most significant digit equals latch B38 output to the time counting value Tn of latch A36 output adds the maximal value De of the clock division coefficient index D e of code translator B373 output
maxdeduct again the clock division coefficient index Te of latch C375 output.
As showing the decoding relation table that 1-1 is depicted as code translator B373 and arbiter 372, code translator B373 carries out decoded operation to the divide ratio indices P e of arbiter 372 outputs, obtains the clock division coefficient index D e of frequency divider B374.
Table 1-1
In table 1-1, tested speed is risen in process at a high speed by low speed, the divide ratio 2 that frequency divider A32 carries out quadruple signal Mul
pebecome gradually large, and the clock division coefficient 2 that frequency divider B374 carries out the clock signal C lock of crystal oscillating circuit 1 output
dediminish gradually; Tested speed is by dropping at a high speed in the process of low speed, the divide ratio 2 that frequency divider A32 carries out quadruple signal Mul
pediminish gradually, and the clock division coefficient 2 that frequency divider B374 carries out the clock signal C lock of crystal oscillating circuit 1 output
debecome gradually large.Frequency division B374 carries out 2 according to the divide ratio index D e of code translator B373 output to the clock signal C lock of crystal oscillating circuit 1 output
defrequency division, thereby the counting clock signal Dclock of acquisition counter 34.Guaranteeing, under the prerequisite that measuring accuracy requires, in the time of can realizing low speed by code translator B373 and frequency divider B374, to use low-speed clock signal Measuring Time, and using high-speed clock signal Measuring Time during high speed.The reduction of clock signal frequency, can effectively reduce the power consumption of system.For meeting different measuring accuracy requirements, can show the code translator B373 of 1-1 and the decoding relation table of arbiter 372 by modification.Known from table 1-1, the maximal value De of the clock division coefficient index D e of the code translator B373 output in the embodiment of the present invention
max=8.
Microprocessor 4 reads the zero velocity marking signal Vz of the time counting value Tn of divide ratio indices P n, the latch A36 output of latch B38 output, the clock division coefficient index Te of adaptive controller 37 outputs and 35 outputs of zero velocity detecting unit from fpga chip 3 by Bus Interface Unit 39, and according to formula (1-1) computing velocity value V, that is:
In formula (1-1), V is speed, and unit is rpm (r/min) or millimeter per minute (mm/min); M is that scrambler Xian Shuo， unit is line/turn or line/mm; T
clkfor the cycle of clock signal C lock, unit is second (s).
In this instructions, it should be pointed out that above embodiment is only two object lessons of the present invention.Obviously, the present invention is not limited to above-mentioned specific embodiment, can also make various modifications, conversion and distortion.Therefore, instructions and accompanying drawing are regarded in an illustrative, rather than a restrictive.Any simple modification that every foundation technical spirit of the present invention is done above embodiment and equivalent variations and modification, all should think and belong to protection scope of the present invention.
Claims (6)
1. the speed adaptive measurement mechanism based on FPGA, at least comprises crystal oscillating circuit (1), encoder interfaces and modulate circuit (2), fpga chip (3) and microprocessor (4); Described fpga chip (3) at least comprises quadruple unit (31), frequency divider A (32), delay unit (33), counter (34), zero velocity detecting unit (35), latch A (36), adaptive controller (37), latch B (38) and Bus Interface Unit (39); It is characterized in that: described adaptive controller (37) at least comprises code translator A (371), arbiter (372), code translator B (373), frequency divider B (374) and latch C (375).
2. a kind of speed adaptive measurement mechanism based on FPGA according to claim 1, is characterized in that: the time counting value Tn of described latch A (36) output is input to respectively adaptive controller (37) and Bus Interface Unit (39); The divide ratio indices P e of described adaptive controller (37) output is input to respectively frequency divider A (32) and latch B (38); The clock division coefficient index Te of described adaptive controller (37) output is input to Bus Interface Unit (39); The clock signal Dclock of described adaptive controller (37) output is input to the input end clk of counter (34); The divide ratio indices P n of described latch B (38) output is input to respectively adaptive controller (37) and Bus Interface Unit (39).
3. a kind of speed adaptive measurement mechanism based on FPGA according to claim 1, is characterized in that: the divide ratio indices P n that the input end of described code translator A (371) is exported with time counting value Tn, the latch B (38) of latch A (36) output is respectively connected with the clock division coefficient index Te of latch C (375) output; The input end of described arbiter (372) is connected with the latch signal Lat of frequency divider A (32) output with the output terminal of code translator A (371), the reset signal Clr of delay unit (33) output respectively; The input end of described code translator B (373) is connected with the divide ratio indices P e of arbiter (372) output; The latch signal Lat that the input end of described frequency divider B (374) is exported with clock division coefficient index D e, the frequency divider A (32) of code translator B (373) output is respectively connected with the clock signal C lock of crystal oscillating circuit (1) output; The input end of described latch C (375) is connected with the latch signal Lat of frequency divider A (32) output with the clock division coefficient index D e of code translator B (373) output respectively; The signal of described arbiter (372) output is divide ratio indices P e; The signal of described code translator B (373) output is clock division coefficient index D e; The signal of described latch C (375) output is clock division coefficient index Te; The signal of described frequency divider B (374) output is clock signal Dclock.
4. a kind of speed adaptive measurement mechanism based on FPGA according to claim 1, it is characterized in that: the code translator A (371) of described adaptive controller (37), described code translator A (371) carries out after right-shift operation other position except most significant digit the time counting value Tn of latch A (36) output, then carries out decoded operation; The divide ratio indices P n that the figure place that described code translator A (371) carries out right-shift operation to the time counting value Tn of latch A (36) output equals latch B (38) output adds the maximal value De of the clock division coefficient index D e of code translator B (373) output
maxdeduct again the clock division coefficient index Te of latch C (375) output.
5. a kind of speed adaptive measurement mechanism based on FPGA according to claim 1, it is characterized in that: the code translator B (373) of described adaptive controller (37), described code translator B (373) carries out decoded operation to the divide ratio indices P e of arbiter (372) output, obtains the clock division coefficient index D e of frequency divider B (374).
6. a kind of speed adaptive measurement mechanism based on FPGA according to claim 1, it is characterized in that: the frequency divider B (374) of described adaptive controller (37), described frequency divider B (374) carries out 2 to the clock signal C lock of crystal oscillating circuit (1) output
defrequency division, obtains clock signal Dclock; When the latch signal Lat of frequency divider A (32) output is effective, frequency divider B (374) the reset zero clearing of described adaptive controller (37).
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| CN112305256A (en) * | 2020-10-12 | 2021-02-02 | 江苏吉泰科电气股份有限公司 | Self-adaptive MT transition speed measurement method |
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