CN103579035B - Defect concentration method of calculation - Google Patents

Abstract

Does the present invention disclose a kind of defect concentration method of calculation, comprises the following steps: S1, the product yield Wafer calculating chip in wafer production line? Yield; S2, the area DieArea calculating the single chip of described product; S3, according to device detection project coefficient Device? Test? Bin, photoetching coefficient Litho? Coefficient and Technology coefficient T echnology? Coefficient calculates the complexity coefficient N of the chip manufacturing proces of described product; S4, product yield Wafer according to chip? Yield, area Die? Area and complexity coefficient N calculates defect concentration D₀. The present invention is by device detection project coefficient B, photoetching coefficient L and Technology coefficient T computation complexity coefficient N, defect concentration size is calculated by the N after revising, reducing the error of defect concentration with actual silicon wafer process ability, these method of calculation and technical process simultaneously can not produce extra cost.

Description

Defect concentration method of calculation

Technical field

The present invention relates to technical field of semiconductors, particularly relate to a kind of defect concentration method of calculation.

Background technology

At present, simultaneously semiconductor manufacturing operation first grows several hundred thousands of identical chips on wafer, whole processing procedure complete after wafer be also called nude film. By qualified chip is picked out in the test of nude film, and cut and it is packaged into product. Usually, to the method for calculation of certain product yield WaferYield of a wafer production line it is, first the nude film some (quantity can change) of this kind of product that same bar wafer production line is produced is selected immediately according to the condition of production, then the whole chips on all nude films selected are tested, by the calculation formula of WaferYield:

WaferYield=qualified chip quantity/chip count

Obtain the product yield WaferYield of certain product.

But, owing to a wafer production line can produce different products, and for variant production, owing to its chip design is different with manufacturing process, product yield WaferYield also can be different. Therefore, the product yield WaferYield of certain product just can not reflect the ability of wafer production line. In order to address this problem, introduce the index representing wafer production line ability: defect concentration (Defectdensity) D₀, unit is defect number every square inch, defect concentration D₀Can calculate by product yield WaferYield.

The pass of the product yield and defect concentration that widely use defect concentration certain product of formulation at present is:

$\mathrm{WaferYield}=\frac{1}{{(1+\mathrm{DieArea}\×D_0)}^N}$

Wherein, WaferYield represents the product yield of certain product, and DieArea represents the area (unit: square inch) of the single chip of certain product, D₀Representing defect concentration (unit: defect number every square inch), N represents the complexity coefficient of the chip manufacturing proces of certain product.

Converted by stdn, by D simultaneously₀It is converted into FD₀, and then obtain FD₀With the relation of WaferYield. Wherein FD₀For factory is taking 800 tube cores as industry benchmark, GDPW (GrossDiePerWafer) is the total tube core number of former of a slice.

In theory, defect concentration FD₀Represent wafer production ability, it should the impact being only subject in wafer production line random defect is a stable value, the inherent defect density FD that namely a wafer production line is produced₀. Therefore, by inherent defect density FD₀The product yield WaferYield of production line can be obtained by above-mentioned formula.

In above-mentioned model calculation formula, N represents complexity coefficient, only carrys out the value of computation complexity coefficient N in existing algorithm by the photoetching number of plies, but does not consider that different device detection project coefficients and different Technologies etc. are to defect concentration D₀The impact caused, the defect concentration D therefore calculated₀There is very big error.

Therefore, for above-mentioned technical problem, it is necessary to provide a kind of new defect concentration method of calculation.

Summary of the invention

In view of this, it is an object of the invention to provide one more rationally, more accurate defect concentration method of calculation.

In order to realize above-mentioned purpose, the technical scheme that the embodiment of the present invention provides is as follows:

A kind of defect concentration method of calculation, described method comprises the following steps:

S1, the product yield WaferYield calculating chip in wafer production line;

S2, the area DieArea calculating the single chip of described product;

S3, the complexity coefficient N calculating the chip manufacturing proces of described product according to device detection project coefficient DeviceTestBin, photoetching coefficient LithoCoefficient and Technology coefficient T echnologyCoefficient;

S4, product yield WaferYield, area DieArea according to chip and complexity coefficient N calculate defect concentration D₀。

As a further improvement on the present invention, in described step S3 complexity coefficient N be the product of device detection project coefficient DeviceTestBin, photoetching coefficient LithoCoefficient and Technology coefficient T echnologyCoefficient three divided by three's sum, namely

$N=\frac{\mathrm{DeviceTestBin}\×\mathrm{LithoCoefficient}\×\mathrm{Techno}\log \mathrm{yCoefficient}}{\mathrm{DeviceTestBin}+\mathrm{LithoCoefficient}+\mathrm{Techno}\log \mathrm{yCoefficient}}.$

As a further improvement on the present invention, described photoetching coefficient LithoCoefficient is calculated by the DUV number of plies and the I-LINE number of plies and is obtained, the DUV number of plies that equals photoetching coefficient LithoCoefficient is multiplied by 1 adds the I-LINE number of plies and is multiplied by 0.5, i.e. LithoCoefficient=DUVlayers*1+I-LINElayers*0.5.

As a further improvement on the present invention, the numerical value of described device detection project DeviceTestBin is the sum of required test event.

As a further improvement on the present invention, described chip comprises logical device, mixed signal devices, flash memories and static RAM, and Technology comprises 0.5 μm, 0.35 μm, 0.18 μm and 0.13 μm of technique.

As a further improvement on the present invention, described Technology coefficient T echnologyCoefficient is specially:

In mixed signal devices and static RAM 0.5 μm, 0.35 μm, 0.18 μm and 0.13 μm of technique, Technology coefficient T echnologyCoefficient is respectively A, 2A, 4A, 8A;

In logical device and flash memories 0.5 μm, 0.35 μm, 0.18 μm and 0.13 μm of technique, Technology coefficient T echnologyCoefficient is respectively A-B, 2A-B, 4A-B, 8A-B;

Wherein the value of A and B is preset constant.

As a further improvement on the present invention, the value of described A is the value of 0.3, B is 0.2.

As a further improvement on the present invention, in described step S4, product yield WaferYield, area DieArea according to chip and complexity coefficient N calculate defect concentration D₀Formula be:

$\mathrm{WaferYield}=\frac{1}{{(1+\mathrm{DieArea}\×D_0)}^N}.$

As a further improvement on the present invention, also comprise after described step S4: by formula D₀=FD₀+ 0.0001*GDPW-0.08, by D₀Carry out stdn, obtain FD₀Value.

As a further improvement on the present invention, described step S1 is specially:

Select the chip on same bar production line, and the chip picked out is tested;

The value of product yield WaferYield is calculated according to WaferYield=qualified chip quantity/chip count.

The invention has the beneficial effects as follows: the present invention is by device detection project coefficient B, photoetching coefficient L and Technology coefficient T computation complexity coefficient N, defect concentration size is calculated by the N after revising, reducing the error of defect concentration with actual silicon wafer process ability, these method of calculation and technical process simultaneously can not produce extra cost.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, it is briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, the accompanying drawing that the following describes is only some embodiments recorded in the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.

Fig. 1 is the schema of defect concentration method of calculation in the present invention;

Fig. 2 is product yield WaferYield and defect concentration FD in prior art₀Two coordinate diagram;

Fig. 3 is product yield WaferYield and defect concentration FD in an embodiment of the present invention₀Two coordinate diagram.

Embodiment

The present invention discloses a kind of defect concentration method of calculation, comprises the following steps:

S1, the product yield WaferYield calculating chip in wafer production line;

S2, the area DieArea calculating the single chip of product;

S3, the complexity coefficient N calculating the chip manufacturing proces of product according to device detection project coefficient DeviceTestBin, photoetching coefficient LithoCoefficient and Technology coefficient T echnologyCoefficient;

S4, product yield WaferYield, area DieArea according to chip and complexity coefficient N calculate defect concentration D₀。

The present invention is by device detection project coefficient B, photoetching coefficient L and Technology coefficient T computation complexity coefficient N, defect concentration size is calculated by the N after revising, reducing the error of defect concentration with actual silicon wafer process ability, these method of calculation and technical process simultaneously can not produce extra cost.

In order to make those skilled in the art understand the technical scheme in the present invention better, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments. Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, should belong to the scope of protection of the invention.

Wafer-process processing procedure (WaferFabrication, be called for short WaferFab) groundwork for making circuit and electronic package on wafer (such as electric crystal, capacitance body, logic gate etc.), it it is the process that a required technology is complicated and fund input is many, for microprocessor (Microprocessor), treatment step needed for it can reach hundreds of road, and machine table needed for it is advanced and expensive, manufacturing environment needed for it is a temperature, humidity and the dust free chamber (Clean-Room) all needing control containing dirt (Particle), although detailed handling procedure is along with product category is relevant with the technology used, but its base conditioning step normally wafer first after suitable cleaning (Cleaning), then (Oxidation) and deposition is carried out being oxidized, finally carry out micro-shadow, the step repeatedly such as etching and implanted ions, to complete processing and the making of circuit on wafer.

Defect concentration refers on chip, expected results in the middle of non-processing procedure, chip quality and good rate is had to independent zone of pollution or the irregular area of negative impact. The kind of defect is quite a lot of, comprises unexpected factor on processing procedure, and such as micronic dust, scratch, light resistance cover incomplete, block defect (ClusterDefect), metallic pollution etc.

Owing to defect concentration is related to product yield height, in general, product yield is relevant to the defect concentration of the number of metal in silicon wafer process, on average every layer, usually, chip area is more big, metal level number is more many or defect concentration more metropolitan good rate is reduced, therefore, also more highlighting semi-conductor dealer takes wafer monitoring equipment to find out defect area and the importance of in addition automatization classification.

Shown in ginseng Fig. 1, the present invention one preferred implementation provides a kind of defect concentration method of calculation, comprises the following steps:

S1, the product yield WaferYield calculating chip in wafer production line;

S2, the area DieArea calculating the single chip of product;

S3, the complexity coefficient N calculating the chip manufacturing proces of product according to device detection project coefficient DeviceTestBin, photoetching coefficient LithoCoefficient and Technology coefficient T echnologyCoefficient;

S4, product yield WaferYield, area DieArea according to chip and complexity coefficient N calculate defect concentration D₀。

First calculate the value of product yield WaferYield, it be specially:

Select the chip on same bar production line, and the chip picked out is tested;

The value of product yield WaferYield is calculated according to WaferYield=qualified chip quantity/chip count.

Then, the area DieArea calculating the single chip of product can first measure the area of multiple chip and record, is then averaged by measured multiple chip areas, in the hope of mean value calculate as the area DieArea of single chip.

In the present invention, complexity coefficient N and device detection project coefficient DeviceTestBin, photoetching coefficient LithoCoefficient and Technology coefficient T echnologyCoefficient are related, represent and are:

f_(N)∈(DeviceTestBin_B, LithoCoefficient_L, TechnoloyCoefficient_T)

Further, in present embodiment complexity coefficient N be the product of device detection project coefficient DeviceTestBin, photoetching coefficient LithoCoefficient and Technology coefficient T echnologyCoefficient three divided by three's sum, namely

$N=\frac{\mathrm{DeviceTestBin}\×\mathrm{LithoCoefficient}\×\mathrm{Techno}\log \mathrm{yCoefficient}}{\mathrm{DeviceTestBin}+\mathrm{LithoCoefficient}+\mathrm{Techno}\log \mathrm{yCoefficient}}=\frac{B\×L\×T}{B+L+T}.$

Wherein, the numerical value of described device detection project DeviceTestBin is the sum of required test event, device detection project comprises MOS conducting, electric current, voltage, resistance, bridging risk etc., in different technique, the required item number measured is not etc., as being respectively 14,16,19,25 in the item number of embodiment of the present invention required test in 0.5MIX, 0.13SRAM, 0.13FLASH and 0.18LOGIC Technology;

The Technology coefficient T echnologyCoefficient of different chip is different, chip comprises logical device and stores device, specifically comprising logical device, mixed signal devices, flash memories and static RAM etc., Technology comprises 0.5 μm, 0.35 μm, 0.18 μm and 0.13 μm of technique. Technology coefficient T echnologyCoefficient in the present invention is specifically defined as:

In mixed signal devices and static RAM 0.5 μm, 0.35 μm, 0.18 μm and 0.13 μm of technique, Technology coefficient T echnologyCoefficient is respectively A, 2A, 4A, 8A;

In logical device and flash memories 0.5 μm, 0.35 μm, 0.18 μm and 0.13 μm of technique, Technology coefficient T echnologyCoefficient is respectively A-B, 2A-B, 4A-B, 8A-B;

Wherein the value of A and B is preset constant, it may be preferred that in present embodiment, the value of A is the value of 0.3, B is 0.2, and logical device is relative simple because of technique with flash memories, so Technology coefficient having been subtracted constant B in present embodiment;

Photoetching coefficient LithoCoefficient is calculated by the DUV number of plies and the I-LINE number of plies and is obtained. Comprising DUV and I-LINE, DUV in a photolithographic process is that deep ultraviolet 248nm exposes, and is generally used in the processing procedure of less than 0.35 μm, and I-LINE is ultraviolet 365nm exposure, is generally used in the processing procedure of more than 0.35 μm. In the present invention, photoetching coefficient LithoCoefficient equals the DUV number of plies and is multiplied by 1 and adds the I-LINE number of plies and be multiplied by 0.5, i.e. LithoCoefficient=DUVlayers*1+I-LINElayers*0.5.

Finally, according to product yield WaferYield, area DieArea and the complexity coefficient N calculating defect concentration D of chip₀, product yield WaferYield, area DieArea and complexity coefficient N and defect concentration D in the present invention₀Relation adopt Seeds model calculation formula:

$\mathrm{WaferYield}=\frac{1}{{(1+\mathrm{DieArea}\×D_0)}^N}.$

Ginseng table 1 show the data of complexity coefficient N in device detection project coefficient DeviceTestBin, photoetching coefficient LithoCoefficient, Technology coefficient T echnologyCoefficient, prior art and the present invention in the present invention's 0.5 μm of mixed signal devices logical device (0.5MIX), 0.13 μm of static RAM part (0.13SRAM), 0.13 μm of flash storage device (0.13FLASH) and 0.18 μm of logical device (0.18LOGIC) Technology.

Table 1:

In Table 1, in prior art, complexity coefficient N calculates according to different levels, general key level (polycrystalline, metal level) value 1, secondary key level (aperture layer time) value 0.5, non-key level (injection level) value 0.25, is then added numerical value corresponding for all levels, shown in concrete data ginseng table 2.

Table 2:

Technology	General key level	Secondary key level	Non-key level	N (old)
					0.5MIX	4	3	8	7.5
0.13SRAM	8	5	18	15
					0.13FLASH	8	6	14	14.5
0.18LOGIC	6	5	10	11

In the present invention, complexity coefficient N is calculated by device detection project coefficient DeviceTestBin (B), photoetching coefficient LithoCoefficient (L) and Technology coefficient T echnologyCoefficient (T) and obtains, and concrete calculation formula is:

$N=\frac{\mathrm{DeviceTestBin}\×\mathrm{LithoCoefficient}\×\mathrm{Techno}\log \mathrm{yCoefficient}}{\mathrm{DeviceTestBin}+\mathrm{LithoCoefficient}+\mathrm{Techno}\log \mathrm{yCoefficient}}=\frac{B\×L\×T}{B+L+T}.$

Shown in ginseng table 1, as in 0.5 μm of mixed signal devices logical device (0.5MIX) Technology, having obtained device detection project coefficient DeviceTestBin (B) is 14, photoetching coefficient LithoCoefficient (L) is 11, Technology coefficient T echnologyCoefficient (T) is 0.3, then N=(14*11*0.3)/(14+11+0.3)=1.8, in other Technologies, N also can try to achieve by data in table 1 respectively.

In the present invention, photoetching coefficient LithoCoefficient equals the DUV number of plies and is multiplied by 1 and adds the I-LINE number of plies and be multiplied by 0.5, i.e. LithoCoefficient=DUVlayers*1+I-LINElayers*0.5, in present embodiment, shown in the concrete numerical value ginseng table 3 of the calculating of the photoetching coefficient LithoCoefficient of various Technology.

Table 3:

Technology	The DUV number of plies	The I-LINE number of plies	Litho Coefficient(L)
				0.5MIX	4	14	11
0.13SRAM	20	5	22.5
				0.13FLASH	19	10	24
0.18LOGIC	19	6	22

Finally, product yield WaferYield, area DieArea and complexity coefficient N according to chip calculates the defect concentration FD in table 4 respectively₀(old) and FD₀(newly), computation process comprises:

First D is calculated according to product yield WaferYield, area DieArea (unit: square inch) and complexity coefficient N₀The value of (unit: defect number/square inch), formula is as follows:

$\mathrm{WaferYield}=\frac{1}{{(1+\mathrm{DieArea}\×D_0)}^N}$

Meanwhile, by formula D₀=FD₀+ 0.0001*GDPW-0.08, by D₀Carry out stdn, obtain FD₀Value, and then obtain FD₀With the relation of WaferYield.

Table 4:

Technology	N (old)	N (newly)	Die Area	Wafer Yield	FD0(old)	FD0(newly)
							0.5MIX	7.5	1.8	0.49989	95.78%	0.11	0.49
0.13SRAM	15	21.0	0.02676	71.05%	0.79	0.54
							0.13FLASH	14.5	22.2	0.01422	79.25%	0.90	0.53
0.18LOGIC	11	11.5	0.00836	91.52%	0.53	0.52

Wherein, FD in the computation process of present embodiment₀For factory is taking 800 tube cores as industry benchmark, GDPW (GrossDiePerWafer) is the total tube core number of former of a slice, specifically, in 0.5MIX, 0.13SRAM, 0.13FLASH, 0.18LOGIC Technology, the value of GDPW is respectively 844,1413,2892 and 5270.

It is respectively in present embodiment prior art and product yield WafeYield and defect concentration FD in the present invention shown in ginseng Fig. 2, Fig. 3₀Two coordinate diagram, choose based on 0.18 μm of logical device, it illustrates the actual silicon wafer process ability after ignoring plant issue, existing in process about 0.52, such as FD in Fig. 2 and Fig. 3₀Article=0.52 two, shown in perpendicular line. Find out product yield WafeYield and defect concentration FD in above-mentioned data respectively in figs. 2 and 3₀The position corresponding to value, and in the drawings with "+" indicate. By in table 4 and Fig. 2, Fig. 3 it may be seen that the defect concentration in prior art 0.5MIX, 0.13SRAM, 0.13FLASH, 0.18LOGIC Technology is respectively 0.11,0.79,0.90,0.53; And the defect concentration in present embodiment 0.5MIX, 0.13SRAM, 0.13FLASH, 0.18LOGIC Technology is respectively 0.49,0.54,0.53,0.52. Defect concentration FD of the prior art₀Very big skew is had with silicon wafer process ability (defect concentration is 0.52), and defect concentration FD after adopting new algorithm₀Comparatively close with silicon wafer process ability (defect concentration is 0.52).

As can be seen from technique scheme, the present invention is by device detection project coefficient B, photoetching coefficient L and Technology coefficient T computation complexity coefficient N, defect concentration size is calculated by the N after revising, reducing the error of defect concentration with actual silicon wafer process ability, these method of calculation and technical process simultaneously can not produce extra cost.

To those skilled in the art, it is clear that the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit or the essential characteristic of the present invention, it is possible to realize the present invention in other specific forms. Therefore, no matter from which point, embodiment all should be regarded as exemplary, and right and wrong are restrictive, the scope of the present invention is limited by claims instead of above-mentioned explanation, it is intended that all changes in the implication of the equivalent important document dropping on claim and scope included in the present invention. Any Reference numeral in claim should be considered as the claim involved by limiting.

In addition, it is to be understood that, although this specification sheets is described according to enforcement mode, but not each enforcement mode only comprises an independent technical scheme, this kind of narrating mode of specification sheets is only for clarity sake, those skilled in the art should by specification sheets integrally, and the technical scheme in each embodiment through appropriately combined, can also form other enforcement modes that it will be appreciated by those skilled in the art that.

Claims (9)

1. defect concentration method of calculation, it is characterised in that, described method comprises the following steps:

S1, the product yield WaferYield calculating chip in wafer production line;

S2, the area DieArea calculating the single chip of described product;

S3, the complexity coefficient N calculating the chip manufacturing proces of described product according to device detection project coefficient DeviceTestBin, photoetching coefficient LithoCoefficient and Technology coefficient T echnologyCoefficient;

S4, product yield WaferYield, area DieArea according to chip and complexity coefficient N calculate defect concentration D₀;

In described step S3 complexity coefficient N be the product of device detection project coefficient DeviceTestBin, photoetching coefficient LithoCoefficient and Technology coefficient T echnologyCoefficient three divided by three's sum, namely

$N=\frac{DeviceTestBin\×LithoCoefficient\×Techno\log yCoefficient}{DeviceTestBin+LithoCoefficient+Techno\log yCoefficient}.$

2. defect concentration method of calculation according to claim 1, it is characterized in that, described photoetching coefficient LithoCoefficient is calculated by the DUV number of plies and the I-LINE number of plies and is obtained, the DUV number of plies that equals photoetching coefficient LithoCoefficient is multiplied by 1 adds the I-LINE number of plies and is multiplied by 0.5, i.e. LithoCoefficient=DUVlayers*1+I-LINElayers*0.5.

3. defect concentration method of calculation according to claim 1, it is characterised in that, the numerical value of described device detection project DeviceTestBin is the sum of required test event.

4. defect concentration method of calculation according to claim 1, it is characterized in that, described chip comprises logical device, mixed signal devices, flash memories and static RAM, and Technology comprises 0.5 μm, 0.35 μm, 0.18 μm and 0.13 μm of technique.

5. defect concentration method of calculation according to claim 4, it is characterised in that, described Technology coefficient T echnologyCoefficient is specially:

In mixed signal devices and static RAM 0.5 μm, 0.35 μm, 0.18 μm and 0.13 μm of technique, Technology coefficient T echnologyCoefficient is respectively A, 2A, 4A, 8A;

In logical device and flash memories 0.5 μm, 0.35 μm, 0.18 μm and 0.13 μm of technique, Technology coefficient T echnologyCoefficient is respectively A-B, 2A-B, 4A-B, 8A-B;

Wherein the value of A and B is preset constant.

6. defect concentration method of calculation according to claim 5, it is characterised in that, the value of described A is the value of 0.3, B is 0.2.

7. defect concentration method of calculation according to claim 1, it is characterised in that, in described step S4, product yield WaferYield, area DieArea according to chip and complexity coefficient N calculate defect concentration D₀Formula be:

$WaferYield=\frac{1}{{\left(1+DieArea\×D_0\right)}^N}.$

8. defect concentration method of calculation according to claim 7, it is characterised in that, also comprise after described step S4:

By formula D₀=FD₀+ 0.0001*GDPW-0.08, by D₀Carry out stdn, obtain FD₀Value.

9. defect concentration method of calculation according to claim 1, it is characterised in that, described step S1 is specially:

Select the chip on same bar production line, and the chip picked out is tested;

The value of product yield WaferYield is calculated according to WaferYield=qualified chip quantity/chip count.