CN103578903B - The etch chamber of adjusting electrode spacing and the depth of parallelism - Google Patents
The etch chamber of adjusting electrode spacing and the depth of parallelism Download PDFInfo
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- CN103578903B CN103578903B CN201210249414.9A CN201210249414A CN103578903B CN 103578903 B CN103578903 B CN 103578903B CN 201210249414 A CN201210249414 A CN 201210249414A CN 103578903 B CN103578903 B CN 103578903B
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Abstract
The invention discloses the etch chamber of a kind of adjusting electrode spacing and the depth of parallelism, comprise; One cavity, described cavity is circular cylindrical cavity; One top electrode, is fixedly mounted on the upper end face of described cavity; One bottom electrode, is fixedly mounted on the bottom surface of described cavity; One variable cavity is set in described cavity, for regulating distance between described upper/lower electrode and the depth of parallelism.The present invention both can accomplish the distance variable of upper/lower electrode and the levelness of upper/lower electrode can be allowed to sit suitably adjustment, optimizes inner evenness.Can ensure the interior test point arbitrarily of the wafer of diameter 200mm, uniformity is less than 2%, and etch rate does not have significant change simultaneously, meets the needs of particular product.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacturing equipment, particularly relate to the cavity of a kind of adjusting electrode spacing and the depth of parallelism.
Background technology
As shown in Figure 1, existing etch chamber, comprises a cavity 1, is a circular cylindrical cavity; Top electrode 2, is fixedly mounted on the upper end face of described cavity; Bottom electrode 3, is fixedly mounted on the bottom surface of described cavity; Top electrode 2 and the distance of bottom electrode 3 are fixed and top electrode 2 is always parallel to each other with bottom electrode 3.Ideally etch chamber intermediate ion electricity slurry 4 distribution, as shown in Figure 2.But in actual production process, the position entering cavity due to etching gas is different, the region of radio-frequency power effect is different, the reasons such as the air inlet position difference of molecular pump or dry pump, cavity of the same type can be caused, etching homogeneity has notable difference, if when the distance between upper/lower electrode is fixed or is always parallel to each other between upper/lower electrode, reach test point inner evenness be less than 2% requirement (200mm wafer) more difficult.Ion-conductance slurry 4 distribution under existing etch chamber virtual condition, as shown in Figure 3.
Summary of the invention
Technical problem to be solved by this invention is to provide the etch chamber of a kind of adjusting electrode spacing and the depth of parallelism, both can accomplish the distance variable of upper/lower electrode and the levelness of upper/lower electrode can be allowed to sit suitably adjustment, optimizing inner evenness.
For solving the problems of the technologies described above, the etch chamber of a kind of adjusting electrode spacing provided by the invention and the depth of parallelism, comprises;
One cavity, described cavity is circular cylindrical cavity;
Top electrode, is fixedly mounted on the upper end face of described cavity;
One bottom electrode, is fixedly mounted on the bottom surface of described cavity;
One variable cavity is set in described cavity, for regulating distance between described upper/lower electrode and the depth of parallelism.
Further, described variable cavity is a bellows chamber.
Further, described bellows chamber comprises: bellows, a bolt hole pedestal, an adjustable bolt and a sealing ring; Wherein, described adjustable bolt is for regulating bellows chamber height.
Further, the regulative mode of described adjustable bolt is manual adjustments.
Further, the regulative mode of described adjustable bolt is automatically regulate.
Further, described bolt hole pedestal is distributed with multiple bolt hole.
Further, described number of bolt hole increases and decreases as required.
Further, described etch chamber is used for the etching of 200mm wafer.
The present invention both can accomplish the distance variable of upper/lower electrode and the levelness of upper/lower electrode can be allowed to sit suitably adjustment, optimizes inner evenness.Can ensure the interior test point arbitrarily of the wafer of diameter 200mm, uniformity is less than 2%, and etch rate does not have significant change simultaneously, meets the needs of particular product.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of existing etch chamber;
Fig. 2 is existing etch chamber ideally ion-conductance slurry distribution map;
Fig. 3 is ion-conductance slurry distribution map under existing etch chamber virtual condition;
Fig. 4 is the structural representation of etch chamber of the present invention;
Fig. 5 is the structural representation of bellows chamber of the present invention;
Fig. 6 is A-A position cutaway view in Fig. 5;
Fig. 7 is ion-conductance slurry distribution map under etch chamber virtual condition of the present invention.
Main element symbol description is as follows:
Cavity 1 top electrode 2
Bottom electrode 3 ion-conductance slurry 4
Cavity 41 top electrode 42
Bottom electrode 43 variable cavity 44
Bellows 51 bolt hole pedestal 52
Adjustable bolt 53 sealing ring 54
Bolt hole 61
Embodiment
For enabling your auditor have a better understanding and awareness object of the present invention, feature and effect, below coordinate accompanying drawing describe in detail as after.
As shown in Figure 4, etch chamber of the present invention comprises a cavity 41, is a circular cylindrical cavity; One top electrode 42, is fixedly mounted on the upper end face of described cavity; One bottom electrode 43, is fixedly mounted on the bottom surface of described cavity; One variable cavity 44, described variable cavity 44 is arranged in described cavity 41, for regulating the Distance geometry depth of parallelism between described top electrode 42 and bottom electrode 43.Described variable cavity 44 can be a bellows cavity.
As shown in Figure 5, bellows chamber of the present invention comprises bellows 51, bolt hole pedestal 52, adjustable bolt 53, and for regulating bellows chamber height, its regulative mode can be manually adjustment, also automatically can be regulated by control assemblies such as motors, realize each step variable uniformity in technique; One sealing ring 54, for seal bellows chamber, makes to keep low pressure in chamber.Described bellows chamber is arranged in described cavity 41.
As shown in Figure 6, be the cutaway view of A-A position in Fig. 5, shown bolt hole pedestal 52 is distributed with multiple bolt hole 61, and its quantity can increase and decrease according to actual needs.
As shown in Figure 7, by the correction of bellows chamber, under etch chamber virtual condition of the present invention, the distribution of ion-conductance slurry is close to perfect condition.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (7)
1. an etch chamber for adjusting electrode spacing and the depth of parallelism, comprising:
One cavity, described cavity is circular cylindrical cavity;
One top electrode, is fixedly mounted on the upper end face of described cavity;
One bottom electrode, is fixedly mounted on the bottom surface of described cavity;
It is characterized in that: the partial sidewall of described cavity is set to variable cavity, for regulating distance between described upper/lower electrode and the depth of parallelism;
Described variable cavity is a bellows chamber.
2. the etch chamber of adjusting electrode spacing as claimed in claim 1 and the depth of parallelism, it is characterized in that, described bellows chamber comprises: bellows, a bolt hole pedestal, an adjustable bolt and a sealing ring; Wherein, described adjustable bolt is for regulating bellows chamber height.
3. the etch chamber of adjusting electrode spacing as claimed in claim 2 and the depth of parallelism, it is characterized in that, the regulative mode of described adjustable bolt is manual adjustments.
4. the etch chamber of adjusting electrode spacing as claimed in claim 2 and the depth of parallelism, is characterized in that, the regulative mode of described adjustable bolt is automatically regulate.
5. the etch chamber of adjusting electrode spacing as claimed in claim 2 and the depth of parallelism, is characterized in that, described bolt hole pedestal is distributed with multiple bolt hole.
6. the etch chamber of adjusting electrode spacing as claimed in claim 5 and the depth of parallelism, it is characterized in that, described number of bolt hole increases and decreases as required.
7. the etch chamber of adjusting electrode spacing as claimed in claim 1 and the depth of parallelism, is characterized in that, described etch chamber is used for the etching of 200mm wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210249414.9A CN103578903B (en) | 2012-07-18 | 2012-07-18 | The etch chamber of adjusting electrode spacing and the depth of parallelism |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210249414.9A CN103578903B (en) | 2012-07-18 | 2012-07-18 | The etch chamber of adjusting electrode spacing and the depth of parallelism |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103578903A CN103578903A (en) | 2014-02-12 |
| CN103578903B true CN103578903B (en) | 2016-02-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210249414.9A Active CN103578903B (en) | 2012-07-18 | 2012-07-18 | The etch chamber of adjusting electrode spacing and the depth of parallelism |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104900473B (en) * | 2015-04-24 | 2017-04-05 | 北京精诚铂阳光电设备有限公司 | Parallelism adjusting device and CVD growth film device |
| CN108565231A (en) * | 2018-04-23 | 2018-09-21 | 武汉华星光电技术有限公司 | Dry etching apparatus |
| CN114446748B (en) * | 2020-10-30 | 2024-05-10 | 中微半导体设备(上海)股份有限公司 | Plasma processing device and working method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6217718B1 (en) * | 1999-02-17 | 2001-04-17 | Applied Materials, Inc. | Method and apparatus for reducing plasma nonuniformity across the surface of a substrate in apparatus for producing an ionized metal plasma |
| CN101370348A (en) * | 2007-08-16 | 2009-02-18 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Inductance coupling plasma apparatus |
| CN101853767A (en) * | 2009-03-30 | 2010-10-06 | 东京毅力科创株式会社 | Substrate processing apparatus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1079350A (en) * | 1996-09-04 | 1998-03-24 | Kokusai Electric Co Ltd | Plasma processor |
| JP3818561B2 (en) * | 1998-10-29 | 2006-09-06 | エルジー フィリップス エルシーディー カンパニー リミテッド | Method for forming silicon oxide film and method for manufacturing thin film transistor |
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2012
- 2012-07-18 CN CN201210249414.9A patent/CN103578903B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6217718B1 (en) * | 1999-02-17 | 2001-04-17 | Applied Materials, Inc. | Method and apparatus for reducing plasma nonuniformity across the surface of a substrate in apparatus for producing an ionized metal plasma |
| CN101370348A (en) * | 2007-08-16 | 2009-02-18 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Inductance coupling plasma apparatus |
| CN101853767A (en) * | 2009-03-30 | 2010-10-06 | 东京毅力科创株式会社 | Substrate processing apparatus |
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| CN103578903A (en) | 2014-02-12 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140114 |
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| C41 | Transfer of patent application or patent right or utility model | ||
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140114 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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