CN103559911A - Method for improving cycle durability of chip - Google Patents
Method for improving cycle durability of chip Download PDFInfo
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- CN103559911A CN103559911A CN201310477570.5A CN201310477570A CN103559911A CN 103559911 A CN103559911 A CN 103559911A CN 201310477570 A CN201310477570 A CN 201310477570A CN 103559911 A CN103559911 A CN 103559911A
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Abstract
The invention provides a method for improving cycle durability of a chip. The method comprises the following steps: pre-programming Block; determining whether each area of Block is uniform; according to the different situations of Block, using different erase methods for erasure; and refreshing programming. Compared with the prior art, the technical scheme provided by the invention has the following advantages: a method comprising first check on situations memory units of the Block and adaptive control of size of the erase block is employed to improve the cycle durability of the chip.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of method that improves chip period permanance.
Background technology
Flash memory (Flash Memory) is the storer of a kind of long-life non-volatile (still can keep stored data message under powering-off state), and it is not that to take single byte as unit but take the block of fixing be unit that data are deleted.Still can save data during due to its power-off, flash memory be usually used to preserve configuration information, input/output routine as basic in the BIOS(at computer), PDA(personal digital assistant), preservation data etc. in digital camera.NOR Flash and NAND Flash are two kinds of main nonvolatile flash memory technology on present market.The feature of NOR Flash is in chip, to carry out (XIP, eXecute In Place), and application program can directly be moved in Flash flash memory like this, needn't code be read in system RAM again.
Nor Flash storage area, in order to save chip area, generally all adopts physical centralization to place, and forms a storage matrix, is then logically divided into a lot of pieces, as shown in Figure 2.Common 1 chip is by a plurality of Block(pieces) form, each Block is by a plurality of Sector(sections) form.Conventionally the order that Nor Flash wipes has three kinds: chip erase (chip erase), piece is wiped (block erase), section is wiped (sector erase), while conventionally chip being carried out to bulk erase operation, adopt piecemeal to wipe one by one, this piecemeal is unit in order to save the general Block of employing of erasing time conventionally, namely 16 Sector carry out erase operation together, just because of this selection mode, brought the problem of chip period permanance, general chip requires the cycle permanance of 100,000 times, if but adopt mode of operation together, conventionally be difficult to reach the requirement of the cycle permanance of 100,000 times.
Feature due to Nor Flash memory cell self, when memory cell is through after repeatedly erasable, this memory cell can be slack-off, for example, it is erasable that we carry out 100,000 cycles to Sector0, the erasable speed in all unit in this Sector is slack-off, but other storage unit still keeps original erasable speed, when if we do piece erase operation to the large Block at Sector0 place like this, just there will be after by the time this sector has wiped, the Sector of other of this block the inside " has crossed and has wiped ", chip needs again to correct these and " crosses and wipe " storage unit, plenty of time need to be expended, if " cross and wipe " serious, have no idea to correct and come, cause wiping unsuccessfully.
Therefore, wish to propose a kind of method that solves current Nor Flash chip period endurance issues.
Summary of the invention
The invention provides a kind of can solution to the problems described above, comprise the following steps:
A) to Block pre-programmed;
B) judge that whether each region of Block is even;
C) according to the even situation in each region of Block, use different method for deleting to wipe;
D) refresh programming.
Compared with prior art, adopt technical scheme tool provided by the invention to have the following advantages: by adopting the situation that first checks Block internal storage unit, self-adaptation regulates the method for erase block sizes, improves chip period permanance.
Accompanying drawing explanation
By reading the detailed description that non-limiting example is done of doing with reference to the following drawings, it is more obvious that other features, objects and advantages of the present invention will become.
Fig. 1 is for improving according to an embodiment of the invention the method flow diagram of chip period permanance;
Fig. 2 is Nor Flash storage area schematic diagram.
Embodiment
Describe embodiments of the invention below in detail.
The example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Below by the embodiment being described with reference to the drawings, be exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific technique the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.
The invention provides a kind of method that improves chip period permanance.Below, in connection with Fig. 1 and Fig. 2, by one embodiment of the present of invention, the method is specifically described.As shown in Figure 1, method provided by the present invention comprises the following steps:
In step S101, to Block pre-programmed.
Because the information of cell stores in the current block wiping may be " 1 ", also may be " 0 ", in the present embodiment, by pre-programmed, the information of " 1 " is all programmed to " 0 ", in this block, all storage information has all become " 0 " like this, guarantee that like this, when wiping whole block, all state of memory cells are basically identical, consistent erasing speed difference is little.Guarantee can not cause because state of memory cells is different the inconsistent of erasing speed.Also can select in other embodiments information to be all programmed to " 1 ".
Specific algorithm comprises: from first byte(byte of block address) start to verify, if there is the bit(bit of " 1 ") exist, just all " 1 " bit of current byte are programmed to " 0 ", after programming successfully, address adds 1 automatically, carry out checking and the programming operation of the 2nd bit, operation in whole Block above circulation, until last byte of current block, so the whole storage information of this block all become programming state entirely for " 0 ", just completed the pre-programmed to Block.
In step S102, judge that whether each region of Block is even.
Concrete determination methods comprises: first this block is carried out to bulk and wipe.Wipe a bulk region, the mode that conventionally adopts a plurality of erasing pulses slowly to wipe.Because the erasing speed of different storage unit may be inconsistent, therefore, after each pulsed erase, also need the automatic correction of carrying out wiping to operate, object is to correct erasing speed ratio storage unit faster.If certain regional memory cell is programmed/wipes repeatedly, what erasing speed will become is slow, therefore if had in Block region, thisly by the zonule of program/erase repeatedly, existed, storage unit is through after several times erasing pulse and correction afterwards, need the erase unit meeting of crossing of correcting to increase suddenly a lot, each correction needs the time of cost also to increase much simultaneously, by this feature, can judge current Block state.We think inhomogeneous to correct the longer Block of spended time.
In step S103, according to the different situation of Block, use different method for deleting to wipe.
Result according to step S102 to Block judgement.If Block region is even, each region erasing speed is more or less the same, and we wipe Block with regard to the method that adopts conventional bulk to wipe, thereby reduces the time that clashes.
If Block region is inhomogeneous, have the slower region of erasing speed, the mode that we select employing to separate fritter is carried out high reliability and is wiped.In the present embodiment, we are for the Block of 64k, have been divided into the region that 16 every block sizes are 4k and have wiped respectively, have so just avoided bulk to wipe bringing the problem that the mistake in the very fast region of erasing speed is wiped.
After having carried out erase step, can also optionally carry out a step examination, to guarantee that Zone Full wipes end.
In step S104, refresh programming.
Because be connected physically between adjacent Block, its bit line connects together, and information in these block has " 1 " and " 0 ".So when wiping current block, if the Long-term Effect Block around, likely change the information existing in these Block, in order to increase the reliability of whole storage organization, after the erasure task of current block finishes, need to judge whether these information are interfered, and to the information being interfered just a step automatically correct.
Compared with prior art, the present invention has the following advantages: by adopting the situation that first checks Block internal storage unit, self-adaptation regulates the method for erase block sizes, improves chip period permanance.
Although describe in detail about example embodiment and advantage thereof, be to be understood that in the situation that do not depart from the protection domain that spirit of the present invention and claims limit, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should easily understand within keeping protection domain of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technique, mechanism, manufacture, material composition, means, method and the step of the specific embodiment of describing in instructions.From disclosure of the present invention, as those of ordinary skill in the art, will easily understand, for the technique, mechanism, manufacture, material composition, means, method or the step that have existed or be about to develop at present later, wherein they carry out identical function or the identical result of acquisition cardinal principle of corresponding embodiment cardinal principle of describing with the present invention, according to the present invention, can apply them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection domain.
Claims (5)
1. a method that improves chip period permanance, the method comprises the following steps:
A) to Block pre-programmed;
B) judge that whether each region of Block is even;
C), according to the even situation in each region of Block, use different method for deleting to wipe;
D) refresh programming.
2. method according to claim 1, wherein, described in step a) to the method for Block pre-programmed for the information unification of all storage unit in Block being programmed for to " 0 " or unified be programmed for " 1 ".
3. method according to claim 1, wherein, sub-step b) whether described each region of Block that judges evenly comprises the following steps:
Send erasing pulse, Block is carried out to bulk and wipe;
Carried out the automatic correction operation of wiping;
Be cycled to repeat above two step operation several times;
According to now correcting, wiped the length of time used whether each region of Block was evenly judged.
4. method according to claim 1, wherein, the different method for deleting described in step c) is:
If Block region is even, adopt the method that bulk is wiped to wipe Block;
If Block region is inhomogeneous, adopts separately the mode of fritter to carry out high reliability and wipe.
5. method according to claim 1, wherein, the method that refreshes programming described in step d) comprises the following steps:
Whether judgement is interfered with the information that is wiped free of the Block that Block is adjacent;
Disturbed information is corrected automatically.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201310477570.5A CN103559911A (en) | 2013-10-13 | 2013-10-13 | Method for improving cycle durability of chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310477570.5A CN103559911A (en) | 2013-10-13 | 2013-10-13 | Method for improving cycle durability of chip |
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| CN103559911A true CN103559911A (en) | 2014-02-05 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106575256A (en) * | 2014-06-19 | 2017-04-19 | 桑迪士克科技有限责任公司 | Sub-block garbage collection |
| CN106601294A (en) * | 2015-10-16 | 2017-04-26 | 爱思开海力士有限公司 | Data storage device and operating method thereof |
| CN111785316A (en) * | 2020-06-29 | 2020-10-16 | 深圳市芯天下技术有限公司 | Method, system, storage medium and terminal for overcoming erasure interference |
| WO2021109244A1 (en) * | 2019-12-02 | 2021-06-10 | 武汉新芯集成电路制造有限公司 | Storage structure and erase method therefor |
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| US20030039145A1 (en) * | 2001-08-24 | 2003-02-27 | Micron Technology, Inc. | Non-volatile memory with block erase |
| US20070113030A1 (en) * | 2005-11-14 | 2007-05-17 | Sandisk Corporation | Methods for the management of erase operations in non-volatile memories |
| US20070189080A1 (en) * | 2006-02-16 | 2007-08-16 | Macronix International Co., Ltd. | Erase operation for use in non-volatile memory |
| CN101645309A (en) * | 2008-08-05 | 2010-02-10 | 威刚科技（苏州）有限公司 | Non-volatile memory device and control method thereof |
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2013
- 2013-10-13 CN CN201310477570.5A patent/CN103559911A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030039145A1 (en) * | 2001-08-24 | 2003-02-27 | Micron Technology, Inc. | Non-volatile memory with block erase |
| US20070113030A1 (en) * | 2005-11-14 | 2007-05-17 | Sandisk Corporation | Methods for the management of erase operations in non-volatile memories |
| US20070189080A1 (en) * | 2006-02-16 | 2007-08-16 | Macronix International Co., Ltd. | Erase operation for use in non-volatile memory |
| CN101645309A (en) * | 2008-08-05 | 2010-02-10 | 威刚科技（苏州）有限公司 | Non-volatile memory device and control method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106575256A (en) * | 2014-06-19 | 2017-04-19 | 桑迪士克科技有限责任公司 | Sub-block garbage collection |
| CN106575256B (en) * | 2014-06-19 | 2019-10-25 | 桑迪士克科技有限责任公司 | Sub-block garbage collection |
| CN106601294A (en) * | 2015-10-16 | 2017-04-26 | 爱思开海力士有限公司 | Data storage device and operating method thereof |
| WO2021109244A1 (en) * | 2019-12-02 | 2021-06-10 | 武汉新芯集成电路制造有限公司 | Storage structure and erase method therefor |
| CN111785316A (en) * | 2020-06-29 | 2020-10-16 | 深圳市芯天下技术有限公司 | Method, system, storage medium and terminal for overcoming erasure interference |
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Application publication date: 20140205 |