CN103545210B - Deepdepletion slot field-effect transistor and preparation method thereof - Google Patents
Deepdepletion slot field-effect transistor and preparation method thereof Download PDFInfo
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- CN103545210B CN103545210B CN201210243573.8A CN201210243573A CN103545210B CN 103545210 B CN103545210 B CN 103545210B CN 201210243573 A CN201210243573 A CN 201210243573A CN 103545210 B CN103545210 B CN 103545210B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 238000002353 field-effect transistor method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 239000000463 material Substances 0.000 claims description 64
- 238000000034 method Methods 0.000 claims description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 230000005669 field effect Effects 0.000 claims description 27
- 238000002347 injection Methods 0.000 claims description 18
- 239000007924 injection Substances 0.000 claims description 18
- 230000008021 deposition Effects 0.000 claims description 17
- 239000000377 silicon dioxide Substances 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 59
- 238000000151 deposition Methods 0.000 description 14
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 235000021485 packed food Nutrition 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
Abstract
The invention discloses a kind of deepdepletion slot field-effect transistor and preparation method thereof, this transistor comprises: substrate; Be arranged in the Vt setting district of described substrate; Be arranged in the spill undoped region of described Vt setting district; Be formed at the gate dielectric layer in described undoped region; To be formed on described gate dielectric layer and to extend the grid of substrate surface; Be positioned at the offset side wall of described grid both sides; Be positioned at the master wall outside the offset side wall of described grid both sides; Be arranged in described grid both sides substrate, and the source/drain region connected with the top outer of described undoped region.In the present invention, the undoped region being positioned at gate bottom is spill, and the source/drain region formed connects with the top of this undoped region, and then the conducting channel formed is the conducting channel of a spill, thus the conducting channel extended between source and drain, and then reduce further the short-channel effect of transistor, and spill undoped region can reduce incidental impurities fluctuation further, to avoid the variation of transistor Vt.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly a kind of deepdepletion slot field-effect transistor and preparation method thereof.
Background technology
All the time, FET(FieldEffectTransistor, field-effect transistor) be all for the manufacture of dedicated IC chip, SRAM(StaticRandomAccessMemory, static random access memory) etc. the main semiconductor device of product.Along with the small of semiconductor device, FET short-channel effect is more serious, and short-channel effect will cause the increase of the threshold voltage (Vt) of FET, and then increases the power consumption of device; In addition, by the impact of short-channel effect, any slight impurity difference all can cause the threshold voltage of FET to occur variation (variation), and then reduces the static noise margin (StaticNoiseMargin, SNM) based on the SRAM of FET technology.
In order to solve the problem, propose for reducing device power consumption in prior art, solve the DDC(DeeplyDepletedChannel of FET threshold voltage variation, deepdepletion raceway groove) transistor technology (as AdvancedchannelEngineeringAchievingAggressiveReductionof VTVariationforUltra-Low-PowerApplications ", K.Fujita, Y.Torii, M.Hori, FujitsuSemiconductorLtd, IEDM2011), it can form DDC after grid applies voltage, with reducing of the CMOS size realizing continuing.
Typical DDC field-effect transistor structure as shown in Figure 1, comprises Semiconductor substrate 10, is arranged at the grid structure 60 on substrate 10, is arranged at the source/drain region 70 in Semiconductor substrate 10; Wherein, include in substrate 10 formed successively to surface direction by substrate 10 inside puncture block area 20, blind zone 30 and Vt setting district 40; Wherein puncture block area 20 for preventing substrate 10 puncturing (sub-channelpunch-through) to raceway groove; Blind zone 30 is for shielded packaged food and the setting depletion layer degree of depth; Vt setting district 40 does not affect carrier mobility for setting transistor threshold voltage Vt, can improve the Vt distribution of conventional transistor yet, thus reduce Vt, and improve carrier mobility to increase effective current.In addition, substrate 10 is also comprised one deck and is not adulterated or slight doped region 50 by epitaxially grown, for exhausting raceway groove except the impurity in dechannelling with Formation Depth, to reduce incidental impurities fluctuation (randomdopingfluctuation), avoids Vt to occur variation; Include in grid structure 60 at the gate dielectric layer do not adulterated or formed successively on slight doped region 50 and polysilicon gate, and be formed at gate dielectric layer and polysilicon gate both sides side wall; Source/drain region 70 is formed in the substrate 10 of grid structure 60 both sides, and the subregion of source/drain region 70 is arranged in the substrate bottom side wall.
Along with the development of integrated circuit technique, expect more high performance device and save production cost, therefore how improving existing DDC field-effect transistor structure and improve performance further and simplify production technology and become problem demanding prompt solution.
Summary of the invention
In view of this, the invention provides a kind of deepdepletion slot field-effect transistor and preparation method thereof, to improve the performance of DDC field-effect transistor further.
The technical scheme of the application is achieved in that
A preparation method for deepdepletion slot field-effect transistor, comprising:
Substrate is provided, and ion implantation is carried out to form Vt setting district to described substrate;
Deposition of sacrificial layer on described Vt setting district, and etch to form groove to described sacrifice layer, the bottom land of described groove is positioned at the surface of Vt setting district;
Offset side wall is formed at the sidewall of described groove;
Partial etching is carried out to the Vt setting district of described groove bottom land, is in described Vt setting district to make the lower trench after partial etching and bottom land;
Epitaxial growth is carried out to the lower trench be in described Vt setting district and bottom land, to form the spill undoped region being arranged in described Vt setting district;
Form gate dielectric layer on described undoped region surface, and in whole groove, deposit gate material layer and described groove is filled up to form grid;
Remove the sacrifice layer being positioned at described grid both sides;
Carry out first time ion implantation to the substrate being positioned at described grid both sides, to form lightly doped drain, described lightly doped drain is arranged in the substrate of described grid both sides, and connects with the top outer of described undoped region;
Master wall is formed outside the offset side wall of described grid both sides;
Second time ion implantation is carried out to the substrate being positioned at described grid both sides, to form the source/drain region being arranged in described grid both sides substrate.
Further, after formation lightly doped drain, before forming master wall, also comprise:
Bag-shaped injection is carried out to the substrate of grid both sides, is positioned on the downside of described lightly doped drain and undoped region joint to be formed, and the bag-shaped injection region between lightly doped drain and undoped region.
Further, form offset side wall at the sidewall of described groove to comprise:
Comprising the whole device surface deposition offset side wall material layer of groove;
Adopt dry etching method, remove the offset side wall material layer being positioned at sacrificial layer surface and being positioned at surface, Vt setting district.
Further, in whole groove, deposit gate material layer and described groove is filled up to form grid comprise:
Comprising the whole device surface deposition gate material layer of groove, and described groove is being filled up;
Carry out cmp to make device surface smooth.
Further, outside the offset side wall of described polysilicon gate both sides, form master wall to comprise:
At the whole device surface deposition master walling bed of material;
Adopt dry etching method, remove the master walling bed of material being positioned at substrate surface and being positioned at top portions of gates.
Further, described substrate is silicon substrate, and described sacrificial layer material is silica, described offset side wall material is silicon nitride, and described undoped region material is silicon, and described gate dielectric layer material is silica, described grid material is polysilicon, and described master wall is the stacked structure of silicon nitride and silica.
A kind of deepdepletion slot field-effect transistor, comprising:
Substrate;
Be arranged in the Vt setting district of described substrate;
Be arranged in the spill undoped region of described Vt setting district;
Be formed at the gate dielectric layer in described undoped region;
To be formed on described gate dielectric layer and to extend the grid of substrate surface;
Be positioned at the offset side wall of described grid both sides;
Be positioned at the master wall outside the offset side wall of described grid both sides;
Be arranged in described grid both sides substrate, and the source/drain region connected with the top outer of described undoped region.
Further, described deepdepletion slot field-effect transistor also comprises:
Be positioned on the downside of described source/drain region and undoped region joint, and the bag-shaped injection region between described source/drain region and undoped region.
Further, described substrate is silicon substrate, and described offset side wall material is silicon nitride, and described undoped region material is silicon, and described gate dielectric layer material is silica, and described grid material is polysilicon, and described master wall is the stacked structure of silicon nitride and silica.
As can be seen from such scheme, in the preparation method of above-mentioned deepdepletion slot field-effect transistor of the present invention and the deepdepletion slot field-effect transistor prepared by the method, the spill undoped region of gate bottom, forms conducting channel when powering up work.Because this undoped region is spill, and the source/drain region formed connects with the top of this undoped region, and then the conducting channel formed is the conducting channel of a spill, thus the conducting channel extended the drain electrode from the source electrode of grid side to grid opposite side, and then reduce further the short-channel effect of transistor, and spill undoped region can reduce incidental impurities fluctuation further, to avoid the variation of transistor Vt.
Accompanying drawing explanation
Fig. 1 is that a kind of exemplary depth of the prior art exhausts slot field-effect transistor structural representation;
Fig. 2 is deepdepletion slot field-effect transistor preparation method flow chart of the present invention;
Fig. 3 is the device change structural representation after forming Vt setting district in the inventive method in the substrate;
Fig. 4 be in the inventive method deposition of sacrificial layer and after forming groove device change structural representation;
Fig. 5 is the device change structural representation after forming offset side wall material layer in the inventive method;
Fig. 6 is the device change structural representation after forming offset side wall in the inventive method;
Fig. 7 carries out the change of the device after partial etching structural representation to the Vt setting district of groove bottom land in the inventive method;
Fig. 8 is the device change structural representation after forming undoped region in the inventive method;
Fig. 9 is the device change structural representation after forming gate dielectric layer and gate material layer in the inventive method;
Figure 10 is the device change structural representation in the inventive method after cmp;
Figure 11 is the device change structural representation after removing sacrifice layer in the inventive method;
Figure 12 is the device change structural representation after forming lightly doped drain in the inventive method;
Figure 13 is the device change structural representation after forming bag-shaped injection region in the inventive method;
Figure 14 is the device change structural representation after depositing the master walling bed of material in the inventive method;
Figure 15 is the device change structural representation after forming master wall in the inventive method;
Figure 16 is the deepdepletion slot field-effect transistor structural representation after forming source/drain region in the inventive method.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in further detail.
As shown in Figure 2, deepdepletion slot field-effect transistor preparation method of the present invention comprises:
Step 1: substrate is provided, and ion implantation is carried out to form Vt setting district to described substrate;
Step 2: deposition of sacrificial layer on described Vt setting district, and etch to form groove to described sacrifice layer, the bottom land of described groove is positioned at the surface of Vt setting district;
Step 3: form offset side wall at the sidewall of described groove;
Step 4: carry out partial etching to the Vt setting district of described groove bottom land, is in described Vt setting district to make the lower trench after partial etching and bottom land;
Step 5: carry out epitaxial growth to the lower trench be in described Vt setting district and bottom land, to form the spill undoped region being arranged in described Vt setting district;
Step 6: form gate dielectric layer on described undoped region surface, and deposit gate material layer and described groove is filled up to form grid in whole groove;
Step 7: remove the sacrifice layer being positioned at described grid both sides;
Step 8: first time ion implantation is carried out to the substrate being positioned at described grid both sides, to form lightly doped drain, described lightly doped drain is arranged in the substrate of described grid both sides, and connects with the top outer of described undoped region;
Step 9: form master wall outside the offset side wall of described grid both sides;
Step 10: carry out second time ion implantation to the substrate being positioned at described grid both sides, to form the source/drain region being arranged in described grid both sides substrate.
Wherein, also can add between step 8 and step 9:
Step 8.5: carry out bag-shaped injection to the substrate of grid both sides, is positioned on the downside of described lightly doped drain and undoped region joint to be formed, and the bag-shaped injection region between lightly doped drain and undoped region.
Below in conjunction with Fig. 3 to Figure 16, deepdepletion slot field-effect transistor preparation method of the present invention is specifically introduced.
Step 1: as shown in Figure 3, provides substrate 100, and carries out ion implantation (as shown by the arrows in Figure 3) to form Vt setting district 101 to described substrate 100.
Wherein, substrate 100 can select silicon substrate, as exemplary depth in prior art exhausts the description of slot field-effect transistor structure, also can include further in substrate 100 formed successively to surface direction by substrate 100 inside puncture block area and blind zone, repeat no more herein.Vt setting district 101 is arranged in substrate 100, and extends to the surface of substrate 100.
Step 2: as shown in Figure 4, deposition of sacrificial layer 102 on described Vt setting district 101, and etch to form groove 103 to described sacrifice layer 102, the bottom land of described groove 103 is positioned at the surface of Vt setting district 101.This step 2 specifically can comprise following process.
Deposition of sacrificial layer 102 on whole Vt setting district 101, the material of sacrifice layer 102 can be silica, by CVD(ChemicalVaporDeposition, chemical vapour deposition (CVD)) etc. common process deposit.Described sacrifice layer 102 applies photoresist to go forward side by side the graphical treatment of the hand-manipulating of needle to groove 103, be stop to etch sacrifice layer 102 afterwards again with photoresist, etching process can adopt dry method or wet etch process to carry out, the sacrifice layer 102 exposed all is removed, until the surface of the Vt setting district 101 of its underpart is exposed.
Step 3: form offset side wall 104 at the sidewall of described groove 103.This step 3 can comprise following process.
Step 31: as shown in Figure 5, comprising the whole device surface deposition offset side wall material layer 104 ' of groove 103, the material of offset side wall material layer 104 ' is as silicon nitride, the deposition of silicon nitride can adopt as LPCVD(LowPressureChemicalVaporDeposition, low-pressure chemical vapor deposition) etc. existing common process realize.
Step 32: as shown in Figure 6, adopts as dry etching method, removes the offset side wall material layer 104 ' being positioned at sacrifice layer 102 surface and being positioned at surface, Vt setting district 101, forms offset side wall 104 with the sidewall at described groove 103.The method of dry etching is adopted mainly to consider the anisotropy of dry etching, intact reservation the offset side wall material layer 104 ' of the sidewall of described groove 103 can be positioned at, to form offset side wall 104 while removing the offset side wall material layer 104 ' being positioned at sacrifice layer 102 surface and be positioned at surface, Vt setting district 101.
Step 4: as shown in Figure 7, carries out partial etching to the Vt setting district 101 of described groove 103 bottom land, is in described Vt setting district 101 to make groove 103 bottom after partial etching and bottom land.
In this step 4, sacrifice layer 102 and offset side wall 104 directly can be utilized as stop, directly partial etching be carried out to the Vt setting district 101 of groove 103 bottom land.It should be noted that and the Vt setting district 101 of groove 103 bottom land all can not be etched removal, the setting effect of the 101 couples of transistor Vt in Vt setting district can be destroyed like this.Can adjust according to actual transistor size and concrete technology the etching depth of the Vt setting district 101 of groove 103 bottom land and the thickness of Vt setting district 101.
Step 5: as shown in Figure 8, carries out epitaxial growth to groove 103 bottom be in described Vt setting district 101 and bottom land, to form the spill undoped region 105 being arranged in described Vt setting district 101.
The substrate 100 of the embodiment of the present invention is silicon substrate, and the Vt setting district 101 after ion implantation is still a part for substrate 100, and its main material ingredient is still silicon, and the material of the undoped region 105 therefore gone out at the Epitaxial growth on this basis is still silicon.In this step 5, only carry out the epitaxial growth of silicon, undoped region 105 is not adulterated.Because undoped region 105 is along groove 103 bottom and bottom land epitaxial growth, so its shape is the spill matched with groove 103 bottom and bottom land.The undoped region 105 of spill is as the use of conducting channel of transistor in future.
Step 6: form gate dielectric layer 106 on described undoped region 105 surface, and deposit gate material layer 107 ' and described groove 103 is filled up to form grid 107 in whole groove 103.This step 6 can comprise following process.
Form gate dielectric layer 106 by the common process such as thermal oxidation or CVD on undoped region 105 surface, the material of gate dielectric layer 106 is as silica.Afterwards, comprising the whole device surface deposition gate material layer 107 ' of groove 103, and utilizing gate material layer 107 ' to be filled up by described groove 103, as shown in Figure 9, the material of gate material layer 107 ' is as polysilicon.After filling up groove 103, in general whole device surface all can deposit one deck gate material layer 107 '.As shown in Figure 10, cmp (CMP) is carried out to make device surface smooth to whole device surface, after cmp, makes device surface expose sacrifice layer 102, the gate material layer 107 ' being arranged in primitive groove groove 103 just exists as grid 107, and its material is as polysilicon.
Step 7: as shown in figure 11, removes the sacrifice layer 102 being positioned at described grid 107 both sides.
The process removing sacrifice layer 102 can adopt the method for conventional dry method or wet etching to carry out.During removal, a silicon nitride hard mask (not shown) can be formed at grid 107 top and be not destroyed to protect grid 107.
Step 8: as shown in figure 12, first time ion implantation is carried out to the substrate 100 being positioned at described grid 107 both sides, to form lightly doped drain 108, described lightly doped drain 108 is arranged in the substrate 100 of described grid 107 both sides, and connects with the top outer of described undoped region 105.
In this step 8, the lightly doped drain 108 formed is physically located in the Vt setting district 101 in substrate 100, and part lightly doped drain 108 is arranged in the substrate 100(Vt setting district 101 bottom offset side wall 104), and connect with the top outer of undoped region 105.Because the undoped region 105 formerly formed is spill and as the use of conducting channel, so on the one hand due to the structure of this spill, on the other hand because the top outer of lightly doped drain 108 with undoped region 105 connects, the source/drain region making lightly doped drain 108(and then formed subsequently) between conducting channel extended in the longitudinal direction of spill.
Step 8.5: as shown in figure 13, carry out bag-shaped (pocket) to the substrate 100 of grid 107 both sides to inject, be positioned on the downside of described lightly doped drain 108 and undoped region 105 joint to be formed, and the bag-shaped injection region 109 between lightly doped drain 108 and undoped region 105.
Carrying out bag-shaped injection to form bag-shaped injection region 109, has been a conventional process in transistor fabrication processes.Form bag-shaped injection region 109, particularly be positioned on the downside of described lightly doped drain 108 and undoped region 105 joint, and bag-shaped injection region 109 part between lightly doped drain 108 and undoped region 105, main purpose be prevent short-channel effect from causing source and drain between puncture.Bag-shaped injection is that a kind of transoid is injected, such as: during preparation N-type transistor, the substrate that substrate 100 adopts P type to adulterate, lightly doped drain 108 and the source/drain region formed subsequently are N-type, then bag-shaped injection region 109 is P type; During preparation P-type crystal pipe, the substrate that substrate 100 adopts N-type to adulterate, lightly doped drain 108 and the source/drain region formed subsequently are P type, then bag-shaped injection region 109 is N-type.
Step 9: form master wall 110 outside the offset side wall 104 of described grid 107 both sides, wherein master wall 110 can be single layer structure, its material generally can be silica, and master wall 110 also can be multilayer lamination structure, and material is generally the alternately stacking of silica and silicon nitride.For stacked structure, the formation of master wall 110 can comprise following process.
As shown in figure 14, at the whole device surface deposition master walling bed of material 110 ', silicon nitride material and silica material layer is comprised.As shown in figure 15, can dry etching method be adopted, remove the master walling bed of material 110 ' being positioned at substrate 100 surface and being positioned at grid 107 top, to form described master wall 110.
Step 10: as shown in figure 16, carries out second time ion implantation to the substrate 100 being positioned at described grid 107 both sides, to form the source/drain region 111 being arranged in described grid 107 both sides substrate 100.
Ion implantation in this step 10 adopts heavy doping mode, after heavy doping, in conjunction with the lightly doped drain 108 formerly formed, be deformed into source/drain region 111, part source/drain region 111 is arranged in the substrate 100 bottom master wall 110 and offset side wall 104, and connects with the top outer of described undoped region 105.
The deepdepletion slot field-effect transistor that the present invention is formed through said method, as shown in figure 16, it comprises: substrate 100; Be arranged in the Vt setting district 101 of described substrate 100; Be arranged in the spill undoped region 105 of described Vt setting district 101; Be formed at the gate dielectric layer 106 in described undoped region 105; To be formed on described gate dielectric layer 106 and to extend the grid 107 on substrate 100 surface; Be positioned at the offset side wall 104 of described grid 107 both sides; Be positioned at the master wall 110 outside described grid 107 both sides offset side wall 104; Be arranged in described grid 107 both sides substrate 100, and the source/drain region 111 connected with the top outer of described undoped region 105; And, be positioned on the downside of described source/drain region 111 and undoped region 105 joint, and the bag-shaped injection region 109 between described source/drain region 111 and undoped region 105.
Wherein, described substrate 100 is silicon substrate, and described offset side wall 104 material is silicon nitride, described undoped region 105 material is silicon, described gate dielectric layer 106 material is silica, and described grid 107 material is polysilicon, and described master wall 110 is the stacked structure of silicon nitride and silica.
In the preparation method of above-mentioned deepdepletion slot field-effect transistor provided by the invention and deepdepletion slot field-effect transistor, the undoped region 105 of the spill bottom grid 107, forms conducting channel when powering up work.Because this undoped region 105 is spill, and the source/drain region 111 formed connects with the top of this undoped region 105, and then the conducting channel formed is the conducting channel of a spill, thus the conducting channel extended the drain electrode from the source electrode of grid 107 side to grid 107 opposite side, and reduce further the short-channel effect of transistor, and spill undoped region 105 also can reduce incidental impurities fluctuation further, to avoid the variation of transistor Vt.
All Alternatives in said method flow process, as deposition, etching, ion implantation etc., those skilled in the art all realize by common technology means, and concrete technology parameter can be determined according to the actual requirements, is not limit the parameter of each technique at this.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (9)
1. a preparation method for deepdepletion slot field-effect transistor, comprising:
Substrate is provided, and ion implantation is carried out to form Vt setting district to described substrate;
Deposition of sacrificial layer on described Vt setting district, and etch to form groove to described sacrifice layer, the bottom land of described groove is positioned at the surface of Vt setting district;
Offset side wall is formed at the sidewall of described groove;
Partial etching is carried out to the Vt setting district of described groove bottom land, is in described Vt setting district to make the lower trench after partial etching and bottom land;
Epitaxial growth is carried out to the lower trench be in described Vt setting district and bottom land, to form the spill undoped region being arranged in described Vt setting district;
Form gate dielectric layer on described undoped region surface, and in whole groove, deposit gate material layer and described groove is filled up to form grid;
Remove the sacrifice layer being positioned at described grid both sides;
Carry out first time ion implantation to the substrate being positioned at described grid both sides, to form lightly doped drain, described lightly doped drain is arranged in the substrate of described grid both sides, and connects with the top outer of described undoped region;
Master wall is formed outside the offset side wall of described grid both sides;
Second time ion implantation is carried out to the substrate being positioned at described grid both sides, to form the source/drain region being arranged in described grid both sides substrate.
2. the preparation method of deepdepletion slot field-effect transistor according to claim 1, is characterized in that, after formation lightly doped drain, before forming master wall, also comprises:
Bag-shaped injection is carried out to the substrate of grid both sides, is positioned on the downside of described lightly doped drain and undoped region joint to be formed, and the bag-shaped injection region between lightly doped drain and undoped region.
3. the preparation method of deepdepletion slot field-effect transistor according to claim 1, is characterized in that, forms offset side wall comprise at the sidewall of described groove:
Comprising the whole device surface deposition offset side wall material layer of groove;
Adopt dry etching method, remove the offset side wall material layer being positioned at sacrificial layer surface and being positioned at surface, Vt setting district.
4. the preparation method of deepdepletion slot field-effect transistor according to claim 1, is characterized in that, deposits gate material layer and described groove is filled up to form grid to comprise in whole groove:
Comprising the whole device surface deposition gate material layer of groove, and described groove is being filled up;
Carry out cmp to make device surface smooth.
5. the preparation method of deepdepletion slot field-effect transistor according to claim 1, is characterized in that, forms master wall and comprise outside the offset side wall of described grid both sides:
At the whole device surface deposition master walling bed of material;
Adopt dry etching method, remove the master walling bed of material being positioned at substrate surface and being positioned at top portions of gates.
6. the preparation method of the deepdepletion slot field-effect transistor according to any one of claim 1 to 5, it is characterized in that: described substrate is silicon substrate, described sacrificial layer material is silica, described offset side wall material is silicon nitride, described undoped region material is silicon, described gate dielectric layer material is silica, and described grid material is polysilicon, and described master wall is the stacked structure of silicon nitride and silica.
7. a deepdepletion slot field-effect transistor, is characterized in that, comprising:
Substrate;
Be arranged in the Vt setting district of described substrate;
Be arranged in the spill undoped region of described Vt setting district;
Be formed at the gate dielectric layer in described undoped region;
To be formed on described gate dielectric layer and to extend the grid of substrate surface;
Be positioned at the offset side wall of described grid both sides;
Be positioned at the master wall outside the offset side wall of described grid both sides;
Be arranged in described grid both sides substrate, and the source/drain region connected with the top outer of described undoped region.
8. deepdepletion slot field-effect transistor according to claim 7, is characterized in that, also comprise:
Be positioned on the downside of described source/drain region and undoped region joint, and the bag-shaped injection region between described source/drain region and undoped region.
9. the deepdepletion slot field-effect transistor according to claim 7 or 8, it is characterized in that: described substrate is silicon substrate, described offset side wall material is silicon nitride, described undoped region material is silicon, described gate dielectric layer material is silica, described grid material is polysilicon, and described master wall is the stacked structure of silicon nitride and silica.
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|---|---|---|---|---|
| US5248893A (en) * | 1990-02-26 | 1993-09-28 | Advanced Micro Devices, Inc. | Insulated gate field effect device with a smoothly curved depletion boundary in the vicinity of the channel-free zone |
| US5808340A (en) * | 1996-09-18 | 1998-09-15 | Advanced Micro Devices, Inc. | Short channel self aligned VMOS field effect transistor |
| CN101071774A (en) * | 2006-05-12 | 2007-11-14 | 联华电子股份有限公司 | Metal oxide semiconductor field effect transistor and its manufacturing method |
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| KR100459872B1 (en) * | 2003-05-07 | 2004-12-03 | 삼성전자주식회사 | Buried channel transistor having trench gate and Method of manufacturing the same |
| WO2006043323A1 (en) * | 2004-10-20 | 2006-04-27 | Fujitsu Limited | Semiconductor device and manufacturing method thereof |
| KR100791342B1 (en) * | 2006-08-09 | 2008-01-03 | 삼성전자주식회사 | Semiconductor devise and method for fabricating the same |
| US8273617B2 (en) * | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5248893A (en) * | 1990-02-26 | 1993-09-28 | Advanced Micro Devices, Inc. | Insulated gate field effect device with a smoothly curved depletion boundary in the vicinity of the channel-free zone |
| US5808340A (en) * | 1996-09-18 | 1998-09-15 | Advanced Micro Devices, Inc. | Short channel self aligned VMOS field effect transistor |
| CN101071774A (en) * | 2006-05-12 | 2007-11-14 | 联华电子股份有限公司 | Metal oxide semiconductor field effect transistor and its manufacturing method |
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