CN103531468B - A kind of MOS transistor and preparation method thereof - Google Patents
A kind of MOS transistor and preparation method thereof Download PDFInfo
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- CN103531468B CN103531468B CN201210225974.0A CN201210225974A CN103531468B CN 103531468 B CN103531468 B CN 103531468B CN 201210225974 A CN201210225974 A CN 201210225974A CN 103531468 B CN103531468 B CN 103531468B
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- 238000000576 coating method Methods 0.000 claims description 71
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- 238000005530 etching Methods 0.000 claims description 22
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 239000011241 protective layer Substances 0.000 claims description 15
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- 238000005516 engineering process Methods 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
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- 238000011049 filling Methods 0.000 claims description 3
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Abstract
The invention discloses a kind of MOS transistor and preparation method thereof.This method includes：a）The first side wall and second sidewall of L-shaped are formed in the semiconductor substrate, the a line of the first side wall and the second sidewall flatly extends in opposite direction respectively in the Semiconductor substrate, the another a line of the first side wall and the second sidewall vertically extends downwardly in the Semiconductor substrate, wherein the first side wall and the second sidewall do not contact the surface of the Semiconductor substrate；b）Grid is formed on the surface of intermediate region between the first side wall and the second sidewall；And c）Source electrode and drain electrode are formed respectively in the Semiconductor substrate in the outside of the first side wall and the second sidewall.The method of the present invention can be isolated source electrode and drain electrode by the first side wall and second sidewall for forming L-type, to prevent source-drain electrode break-through from revealing and suppress short-channel effect.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly to a kind of MOS transistor and preparation method thereof.
Background technology
Fig. 1 is the schematic diagram of existing MOS transistor.As shown in Figure 1, on a semiconductor substrate 100 formed with grid knot
Structure, it includes gate oxide layers 101 and gate material layers 102.Formed in the Semiconductor substrate 100 of gate structure both sides active
Pole 104A and drain electrode 104B.Source electrode 104A and drain electrode 104B further include shallow doped region 103A and 103B respectively.
Continuous with dimensions of semiconductor devices reduces, such as is down to below 100nm, and source electrode 104A is posted with drain electrode 104B's
Raw junction capacity increase.In addition, as the continuous of channel length shortens, source electrode 104A to drain electrode 104B break-through（punch
through）Leakage increase, and the short-channel effect of raceway groove is further deteriorated.
Therefore, it is badly in need of a kind of MOS transistor and preparation method thereof at present, to solve the above problems.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features, do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to solve the problems in the existing technology, the present invention proposes a kind of production method of MOS transistor, wraps
Include：a）The one of the first side wall and second sidewall of formation L-shaped in the semiconductor substrate, the first side wall and the second sidewall
Bar side flatly extends in opposite direction respectively in the Semiconductor substrate, the first side wall and the second sidewall
Another a line vertically extends downwardly in the Semiconductor substrate, wherein the first side wall and the second sidewall do not contact
The surface of the Semiconductor substrate；b）Shape on the surface of intermediate region between the first side wall and the second sidewall
Into grid；And c）Source electrode is formed respectively in the Semiconductor substrate in the outside of the first side wall and the second sidewall
And drain electrode.
Preferably, the Semiconductor substrate include be used for formed the first side wall and the second sidewall substrate and
The coating of the first side wall and the second sidewall and the intermediate region between the two is covered on the substrate,
The method is additionally included in the coating of the grid both sides and forms shallow doped region.
Preferably, a）Step includes：Substrate is provided；Oxide skin(coating) and protective layer are sequentially formed on the substrate；
The protective layer, the oxide skin(coating) and the substrate are performed etching, to form opening；On the side wall of the opening both sides
Sidewall oxide layer is formed respectively；Remove the protective layer；The semi-conducting material for filling up the opening is formed in said opening；
And the coating is formed on the substrate, the coating covers the intermediate region, and also symmetrically covers institute
The oxide skin(coating) of the part of intermediate region both sides is stated, wherein the oxide skin(coating) covered by the coating and the side
Wall oxide skin(coating) forms the first side wall and the second sidewall together.
Preferably, the region for the MOS transistor at least being formed in the substrate is formed by silicon.
Preferably, the sidewall oxide layer is the silicon oxide layer formed using thermal oxidation method.
Preferably, the semi-conducting material filled up in the opening is the silicon formed using epitaxial growth method.
Preferably, the coating is the silicon formed using epitaxial lateral outgrowth method.
Preferably you, the b）Step includes：Gate oxide layers and grid material are sequentially formed on the semiconductor substrate
The bed of material；The gate material layers and the gate oxide layers are performed etching, described in being formed in the surface of the coating
Grid, wherein the width of the grid is less than the width of the coating；And described in removing and not covered by the coating
Oxide skin(coating).
Preferably, the b）Step further includes：Shallow Doped ions injection technology is carried out by mask of the grid, with institute
State and the shallow doped region is formed in the coating of grid both sides.
Preferably, the oxide skin(coating) not covered by the coating and the technique for etching the gate oxide layers are removed
Completed in same etching technics.
Preferably, the source electrode and the drain electrode are respectively in the outside of the first side wall and the second sidewall close to institute
State the first side wall and the second sidewall.
Preferably, the first side wall and the thickness of the second sidewall are 50-5000 angstroms.
Preferably, the method also includes forming metal silicide layer in the grid, the source electrode and the drain electrode
The step of.
The present invention also provides a kind of MOS transistor, including：Semiconductor substrate；The first side wall and second sidewall of L-shaped, institute
The a line for stating the first side wall and the second sidewall flatly extends in opposite direction respectively in the Semiconductor substrate,
The another a line of the first side wall and the second sidewall vertically extends downwardly in the Semiconductor substrate, wherein described
The first side wall and the second sidewall do not contact the surface of the Semiconductor substrate；Grid, the grid are located at first side
The surface of intermediate region between wall and the second sidewall；And source electrode and drain electrode, the source electrode and the drain electrode are distinguished
In the Semiconductor substrate in the outside of the first side wall and the second sidewall.
Preferably, the Semiconductor substrate include be used for formed the first side wall and the second sidewall substrate and
The coating of the first side wall and the second sidewall and the intermediate region between the two is covered on the substrate,
The MOS transistor is additionally included in the shallow doped region formed in the coating of the grid both sides.
Preferably, the region for the MOS transistor at least being formed in the substrate is formed by silicon.
Preferably, the first side wall and the second sidewall are formed by silica.
Preferably, the source electrode and the drain electrode are respectively in the outside of the first side wall and the second sidewall close to institute
State the first side wall and the second sidewall.
Preferably, the first side wall and the thickness of the second sidewall are 50-5000 angstroms.
Preferably, the MOS transistor is further included positioned at the metallic silicon in the grid, the source electrode and the drain electrode
Compound layer.
To sum up shown, method of the invention can be by source electrode and drain electrode by the first side wall and second sidewall for forming L-type
Isolation, to prevent source-drain electrode break-through from revealing and suppress short-channel effect.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.In the accompanying drawings,
Fig. 1 is a kind of schematic diagram of the metal gates of MOS transistor common at present；
Fig. 2 is the process flow chart that MOS transistor is made according to one embodiment of the present invention；
Fig. 3 A-3M make each step in MOS transistor technological process according to one embodiment of the present invention and are obtained
The sectional view of device；And
Fig. 4 is the sectional view according to the MOS transistor of one embodiment of the present invention.
Embodiment
Next, the present invention will be more fully described by with reference to attached drawing, shown in the drawings of the embodiment of the present invention.But
It is that the present invention can be implemented in different forms, and should not be construed as being limited to embodiments presented herein.On the contrary, provide
These embodiments will make disclosure thoroughly and complete, and will fully convey the scope of the invention to those skilled in the art.
In attached drawing, for clarity, the size and relative size in Ceng He areas may be exaggerated.Same reference numerals represent phase from beginning to end
Same element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then there is no element or layer between two parties.
Fig. 2 shows that making semiconductor device technology flow chart, Fig. 3 A-3M are shown according to one embodiment of the present invention
The sectional view of the device that each step is obtained in semiconductor device technology flow is made according to one embodiment of the present invention.Should
It is noted that the part of devices structure in semiconductor devices can be manufactured by CMOS production processes, therefore in the side of the present invention
Before method, among or extra technique can be provided afterwards, and some of which technique only makees simple description herein.Below will knot
Close Fig. 2 and Fig. 3 A-3M and carry out the production method that the present invention will be described in detail.
Step 201 is performed, forms the first side wall and second sidewall of L-shaped, the first side wall and second in the semiconductor substrate
The a line of side wall flatly extends in opposite direction respectively in the semiconductor substrate, and the first side wall and second sidewall is another
A line vertically extends downwardly in the semiconductor substrate, and wherein the first side wall and second sidewall do not contact the table of Semiconductor substrate
Face.
The semiconductor that source electrode and drain electrode can be respectively formed in subsequent technique on the outside of the first side wall and second sidewall of L-shaped
In substrate, to prevent source electrode and drain electrode break-through.The first side wall and second sidewall do not contact the surface of Semiconductor substrate, can be
A certain distance is reserved between the surface of one side wall and second sidewall and Semiconductor substrate, can when being turned on for MOS transistor
Carrier is set to flow to drain electrode from source electrode, to form electric current.
Preferably, Semiconductor substrate can include being used to form the substrate of the first side wall and second sidewall and in substrate
Cover the coating of the first side wall and second sidewall and intermediate region between the two.And method provided by the invention is also wrapped
Include and shallow doped region is formed in the coating of grid both sides, to suppress short-channel effect.
The first side wall of formation L-shaped and the method for second sidewall have a variety of in the semiconductor substrate, and the present invention is with reference to attached drawing
Only describe in detail to one of which preferred embodiment.This method comprises the following steps：
Step 1：Substrate is provided；
As shown in Figure 3A, substrate 300 is provided first.Substrate 300 can be at least one of following material being previously mentioned：
Silicon, silicon-on-insulator（SOI）, be laminated silicon on insulator（SSOI）, be laminated SiGe on insulator（S-SiGeOI）, on insulator
SiGe（SiGeOI）And germanium on insulator（GeOI）Deng.It could be formed with the shallow ridges for isolating active area in substrate 300
Groove is isolated（STI）Can be by silica, silicon nitride, silicon oxynitride, Fluorin doped glass and/or other existing Deng the isolation of, shallow trench
Dielectric materials formed.Certainly, can also be formed with dopant well in substrate 300（It is not shown）Etc..For illustrative simplicity,
Square frame is here used only for represent.
Step 2：Oxide skin(coating) and protective layer are sequentially formed in substrate；
Continue as shown in Figure 3A, oxide skin(coating) 301 and protective layer 302 to be sequentially formed in substrate 300.Oxide skin(coating) 301
It is mainly used for being formed the first side wall and second sidewall of L-shaped together with the sidewall oxide layer that subsequent technique is formed.Oxide skin(coating)
301 material can be with silica etc..The main application of protective layer 302 is：On the one hand, prevent oxide skin(coating) 301 in follow-up work
It is damaged in skill, on the other hand, is also used as subsequent etching oxide skin(coating) 301 and the hard mask layer of substrate 300.The protection
Layer 302 can be formed with nitride material.Further, it is to be appreciated that need to remove the protection when needs are finished in etching technics
During layer 302, protective layer should select have higher etching selection ratio with oxide skin(coating) 301 below.
Step 3：Protective layer, oxide skin(coating) and substrate are performed etching, to form opening；
The photoresist layer with patterns of openings can be formed on the semiconductor device structure shown in Fig. 3 A（It is not shown）, so
Protective layer 302 is performed etching using the photoresist layer as mask afterwards.Then it is mask to oxygen with the photoresist layer and protective layer 302
Compound layer 301 and substrate 300 perform etching, to form opening 303 in substrate 300, as shown in Figure 3B.Mentioned in this specification
Etching technics can be as needed for dry etching or wet etching（Except mentioning otherwise herein）, which kind of quarter no matter selected
Etching method is required to select suitable etching agent according to the material layer etched, this is for those skilled in the art
Know, therefore no longer etching technics is described in detail herein.
Step 4：Sidewall oxide layer is formed on the side wall of opening both sides；
As an example, physical vaporous deposition, chemical vapour deposition technique or magnetron sputtering method etc. can be used in Fig. 3 B institutes
Deposited oxide layer on the semiconductor device structure shown；Then the oxide that dry etch process removes 303 bottoms of opening is performed
Layer, to form sidewall oxide layer 305 only on the side wall of 303 both sides of opening, as shown in Figure 3D.
Preferably, the region for MOS transistor at least being formed in substrate 300 is formed by silicon.By substrate 300 be arranged to
There is silicon materials formation in the region of few MOS transistor for being used to be formed the present invention, can simplify to form the first side wall and second
The processing step of side wall, with cost-effective.In such cases, as shown in Figure 3 C, oxide can be formed using thermal oxidation method
Layer 304, the material of the oxide skin(coating) 304 is silica.Compared with the method for above-mentioned other deposited oxide layers, hot oxygen
The required equipment of change method is simple, and process parameter control is convenient.Thermal oxidation method will can be aoxidized equably exposed to the silicon of outside, because
This can also form oxide skin(coating) 304 in the bottom of opening 303.As such, it is desirable to the oxide skin(coating) 304 of 303 bottom of opening is removed,
To form sidewall oxide layer 305 only on the side wall of 303 both sides of opening, as shown in Figure 3D.Remove the oxidation of 303 bottoms of opening
The method of nitride layer 304 can be dry etching.
Step 5：Due to no longer needing protective layer 302 in subsequent technique, method of the invention further includes removal
The step of protective layer 302, as shown in FIGURE 3 E.
Step 6：The semi-conducting material for filling up the opening is formed in the opening；
As illustrated in Figure 3 F, semi-conducting material is filled up in opening 303.The semi-conducting material can be identical with substrate 300
Material, or different materials.When the region that MOS transistor is at least formed in substrate 300 is formed by silicon,
The semi-conducting material filled up in opening 303 is preferably the silicon formed using epitaxial growth method.Epitaxial growth method can be as far as possible
Ensure that these materials have same or like crystal lattice orientation and lattice parameter with the material in original substrate 300, with to the greatest extent
Amount avoids the influence to semiconductor devices.
Step 7：Coating is formed on a semiconductor substrate, coating covering intermediate region, and also symmetrically cover
The oxide skin(coating) of the part of intermediate region both sides, wherein being made of together the oxide skin(coating) and sidewall oxide layer of coating covering
The first side wall and second sidewall.
The MOS transistor of shallow doped region is formed for needing, coating 307 can be formed in substrate 300（Such as Fig. 3 G institutes
Show）, to form shallow doped region in coating 307.Coating 307 is not only needed between covering two side walls oxide skin(coating) 305
Intermediate region, it is also necessary to symmetrically cover intermediate region both sides portions of oxide layer 301.Coating 307 is in intermediate region
Extend equal distance on the oxide skin(coating) 305 of both sides to both sides.When the region that MOS transistor is at least formed in substrate 300 is
By silicon formed when, it is preferable that coating 307 is to use epitaxial lateral outgrowth method（epitaxy lateral
overgrowth）Formed, to keep the uniformity with the lattice of substrate 300 as much as possible.It is, of course, also possible to using other sides
Method forms coating 307, such as can use physical vaporous deposition, chemical vapour deposition technique, atomic layer deposition method, magnetic control
Sputtering method etc. is initially formed the material layer for covering whole device, then performs etching, to form satisfactory coating 307.
As it can be seen that using epitaxial lateral outgrowth method in addition to having the advantages that to keep lattice coherency, it is also simple with processing step
It is specific.The semi-conducting material 306 that fills up and substrate 300, which together form, in coating 307, opening accommodates the first side wall and the
The Semiconductor substrate of two side walls.
Step 202 is performed, grid is formed in the Semiconductor substrate between the first side wall and second sidewall.
First, as shown in figure 3h, gate oxide layers and gate material layers are sequentially formed on a semiconductor substrate, in order to succinct
Only the double-decker with gate oxide layers and gate material layers is stated with layer 308.Then, as shown in fig. 31, to layer 308
（That is gate material layers and gate oxide layers）Perform etching, to form grid 309, wherein grid in the surface of coating 307
309 width is less than the width of coating 307.The width of grid 309 and the width of intermediate region（That is two side walls oxide skin(coating)
The distance between 305）It is roughly equal.The oxide skin(coating) that uncovered layer 307 covers is removed, to form the first side of L-shaped respectively
The second sidewall of wall and L-shaped.Preferably, the first side wall and the thickness of second sidewall can be 50-5000 angstroms.According to the pass of device
Key size, can select the first side wall and second sidewall of suitable thickness within the range.Preferably, uncovered layer is removed
The oxide skin(coating) 301 of 307 coverings can be completed with etching the technique of gate oxide layers in same etching technics.
Preferably, as shown in figure 3j, shallow Doped ions injection technology is carried out for mask with grid 309, with 309 liang of grid
Shallow doped region 310A and 310B is formed in the coating 307 of side, to suppress short-channel effect to a certain extent.
Step 203 is performed, source electrode and leakage are formed respectively in the Semiconductor substrate in the first side wall and the outside of second sidewall
Pole.
Since source electrode and the formation process of drain electrode are to be known in the art, to be only briefly described.As shown in Fig. 3 K,
The both sides of grid 309 form clearance wall 311 respectively；Then, as described in Fig. 3 L, source-drain electrode ion implantation technology is carried out, with the
Source electrode 312A and drain electrode 312B are formed in Semiconductor substrate on the outside of one side wall and second sidewall respectively.It should be noted that grid
Pole 309 and clearance wall 311 should substantially cover intermediate region, to ensure that source electrode 312A and drain electrode 312B can be respectively formed at the
In Semiconductor substrate on the outside of one side wall and second sidewall.Preferably, source electrode 312A and drain electrode 312B respectively in the first side wall and
The outside of second sidewall is close to the first side wall and second sidewall.
In addition, in order to reduce contact resistance, as shown in fig.3m, this method is additionally included in grid 309, source electrode 312A and drain electrode
The step of metal silicide layer 313 are formed on 312B.The method for forming metal silicide layer 313 is, for example, self-registered technology.By
In the technique to be well known to those skilled in the art, therefore no longer it is described in detail.
In addition, the present invention also provides a kind of MOS transistor, as shown in figure 4, the MOS transistor includes Semiconductor substrate, L
The first side wall 401A and second sidewall 401B of shape, grid 403 and source electrode 404A and drain electrode 404B.The first side wall 401A and
The a line a line of two side wall 401B flatly extends in opposite direction respectively in the semiconductor substrate, wherein the first side wall
401A and second sidewall 401B does not contact the surface of Semiconductor substrate.Grid 403 is located at the first side wall 401A and second sidewall
The surface of intermediate region between 401B.Source electrode 404A and drain electrode 404B are located at the first side wall 401A and second sidewall respectively
In the Semiconductor substrate 400 in the outside of 401B.
Preferably, Semiconductor substrate includes being used to form the substrate 400 of the first side wall and second sidewall and in substrate 400
Upper covering the first side wall 401A and second sidewall 401B and the coating 402 of intermediate region between the two.The MOS transistor
It is additionally included in the shallow doped region 405A and 405B of the shallow doped region formed in the coating 402 of 403 both sides of grid.
Preferably, source electrode 404A and drain electrode 404B are respectively in the outside of the first side wall 401A and second sidewall 401B close to the
One side wall 401A and second sidewall 401B.Preferably, the thickness of the first side wall 401A and second sidewall 401B are 50-5000 angstroms.
Preferably, the region for MOS transistor at least being formed in Semiconductor substrate 400 is formed by silicon.Further preferably
Ground, the first side wall 401A and second sidewall 401B are formed by silica.
In addition, MOS transistor is further included positioned at the metal silicide layer on grid 403, source electrode 404A and drain electrode 404B
406。
Above-mentioned each structure is referred to described above, and which is not described herein again.
To sum up shown, method of the invention can be by source electrode and drain electrode by the first side wall and second sidewall for forming L-type
Isolation, to prevent source-drain electrode break-through from revealing and suppress short-channel effect.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (19)
- A kind of 1. production method of MOS transistor, it is characterised in that including：A) the first side wall and second sidewall of L-shaped are formed in the semiconductor substrate, the first side wall and the second sidewall A line flatly extends in opposite direction respectively in the Semiconductor substrate, the first side wall and the second sidewall Another a line vertically extended downwardly in the Semiconductor substrate, wherein the first side wall and the second sidewall do not connect Touch the surface of the Semiconductor substrate；B) grid is formed on the surface of the intermediate region between the first side wall and the second sidewall；AndC) source electrode and drain electrode are formed respectively in the Semiconductor substrate in the outside of the first side wall and the second sidewall, The first side wall and the second sidewall increase the distance between the source electrode and drain electrode, and isolate the source electrode and drain electrode,Wherein, a) step includes：Substrate is provided；Oxide skin(coating) and protective layer are sequentially formed on the substrate；The protective layer, the oxide skin(coating) and the substrate are performed etching, to form opening；Sidewall oxide layer is formed respectively on the side wall of the opening both sides；Remove the protective layer；The semi-conducting material for filling up the opening is formed in said opening；AndForm coating on the substrate, the coating covers the intermediate region, and also symmetrically cover it is described in Between region both sides part the oxide skin(coating), wherein the oxide skin(coating) and the side wall oxygen that are covered by the coating Compound layer forms the first side wall and the second sidewall together.
- 2. production method as claimed in claim 1, it is characterised in that the method is additionally included in the described of the grid both sides Shallow doped region is formed in coating.
- 3. production method as claimed in claim 1, it is characterised in that the MOS transistor is at least formed in the substrate Region is formed by silicon.
- 4. production method as claimed in claim 1, it is characterised in that the sidewall oxide layer is formed using thermal oxidation method Silicon oxide layer.
- 5. production method as claimed in claim 1, it is characterised in that the semi-conducting material filled up in the opening is to adopt The silicon formed with epitaxial growth method.
- 6. production method as claimed in claim 1, it is characterised in that the coating is to use epitaxial lateral outgrowth method shape Into silicon.
- 7. production method as claimed in claim 1, it is characterised in that the b) step includes：Gate oxide layers and gate material layers are sequentially formed on the semiconductor substrate；The gate material layers and the gate oxide layers are performed etching, to form the grid in the surface of the coating Pole, wherein the width of the grid is less than the width of the coating；AndRemove the oxide skin(coating) not covered by the coating.
- 8. production method as claimed in claim 7, it is characterised in that the b) step further includes：Shallow Doped ions injection technology is carried out by mask of the grid, to be formed in the coating of the grid both sides The shallow doped region.
- 9. production method as claimed in claim 7, it is characterised in that remove the oxide not covered by the coating Layer is completed with etching the technique of the gate oxide layers in same etching technics.
- 10. production method as claimed in claim 1, it is characterised in that the source electrode and the drain electrode are respectively described first The outside of side wall and the second sidewall is close to the first side wall and the second sidewall.
- 11. production method as claimed in claim 1, it is characterised in that the first side wall and the thickness of the second sidewall For 50-5000 angstroms.
- 12. production method as claimed in claim 1, it is characterised in that the method is additionally included in the grid, the source electrode The step of with metal silicide layer is formed in the drain electrode.
- A kind of 13. MOS transistor, it is characterised in that including：Semiconductor substrate；The a line of the first side wall and second sidewall of L-shaped, the first side wall and the second sidewall is served as a contrast in the semiconductor Flatly extend in opposite direction respectively in bottom, the another a line of the first side wall and the second sidewall is partly led described The a line of relatively described the first side wall and the second sidewall vertically extends downwardly in body substrate, wherein described first Side wall and the second sidewall do not contact the surface of the Semiconductor substrate；Grid, the surface of intermediate region of the grid between the first side wall and the second sidewall；AndSource electrode and drain electrode, the source electrode and the drain electrode are respectively positioned at the institute in the first side wall and the outside of the second sidewall State in Semiconductor substrate, the first side wall and the second sidewall increase the distance between the source electrode and drain electrode, and isolate The source electrode and drain electrode.
- 14. MOS transistor as claimed in claim 13, it is characterised in that the Semiconductor substrate includes being used to be formed described The substrate of the first side wall and the second sidewall and cover on the substrate the first side wall and the second sidewall with And the coating of the intermediate region between the two, the MOS transistor are additionally included in the covering of the grid both sides The shallow doped region formed in layer.
- 15. MOS transistor as claimed in claim 14, it is characterised in that the MOS transistor is at least formed in the substrate Region be to be formed by silicon.
- 16. MOS transistor as claimed in claim 15, it is characterised in that the first side wall and the second sidewall be by What silica was formed.
- 17. MOS transistor as claimed in claim 13, it is characterised in that the source electrode and the drain electrode are respectively described the The outside of one side wall and the second sidewall is close to the first side wall and the second sidewall.
- 18. MOS transistor as claimed in claim 13, it is characterised in that the thickness of the first side wall and the second sidewall Spend for 50-5000 angstroms.
- 19. MOS transistor as claimed in claim 13, it is characterised in that the MOS transistor is further included positioned in the grid Metal silicide layer in pole, the source electrode and the drain electrode.
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| CN1922719A (en) * | 2004-02-19 | 2007-02-28 | 皇家飞利浦电子股份有限公司 | Semiconductor device and method of manufacturing a semiconductor device |
| CN101740393A (en) * | 2008-11-27 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
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| TWI259520B (en) * | 2005-07-13 | 2006-08-01 | Promos Technologies Inc | Semiconductor device and manufacturing method thereof |
| CN100536163C (en) * | 2005-07-19 | 2009-09-02 | 茂德科技股份有限公司 | Semiconductor element and its producing method |
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| CN1922719A (en) * | 2004-02-19 | 2007-02-28 | 皇家飞利浦电子股份有限公司 | Semiconductor device and method of manufacturing a semiconductor device |
| CN101740393A (en) * | 2008-11-27 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
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