CN103531249A - Device applied to nonvolatile memory test and method thereof - Google Patents
Device applied to nonvolatile memory test and method thereof Download PDFInfo
- Publication number
- CN103531249A CN103531249A CN201310477361.0A CN201310477361A CN103531249A CN 103531249 A CN103531249 A CN 103531249A CN 201310477361 A CN201310477361 A CN 201310477361A CN 103531249 A CN103531249 A CN 103531249A
- Authority
- CN
- China
- Prior art keywords
- nonvolatile memory
- module
- programming
- clock signal
- driver module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention relates to a device applied to a nonvolatile memory test and a method of the device. The device applied to the nonvolatile memory test comprises a programming driving module, an erasing driving module, a clock inputting module, a programming controlling module and an erasing controlling module, wherein the programming driving module is used for driving a nonvolatile memory to be processed to perform programming operation; the erasing driving module is used for driving the nonvolatile memory to perform erasing operation; the clock inputting module is used for imputing clock signals; the programming controlling module is used for controlling the programming driving module to perform programming operation in a preset period of time on the nonvolatile memory according to the clock signals input by the clock inputting module; the erasing controlling module is used for controlling the erasing module to perform erasing operation in a preset period of time on the nonvolatile memory according to the clock signals input by the clock inputting module. The device, disclosed by the invention, has the beneficial effects of saving time and improving efficiency.
Description
Technical field
The present invention relates to field of non-volatile memory, relate in particular to a kind of device and method for nonvolatile memory test.
Background technology
Before nonvolatile memory chip encapsulation, in order to improve the yield of chip, reject defective products, make " 0 " of storage unit and the distribution curve of " 1 " more closely and make peripheral programming and erase verification circuit reach a more stable state, need to test the nonvolatile memory of chip.This test refers to fast programming and the erase operation of certain number of times.The effect of this fast programming and erase operation is closely related with the electronics sum of turnover floating boom, rather than depends on programming and the degree of wiping.
Especially when the memory capacity of chip is larger, fast programming and the needed time of erase operation of carrying out certain number of times will be very long, consume the more time, and efficiency is lower.
Wherein, the test of non-volatile memory cells comprises programming and wipes two parts.As NOR Flash storage unit, it consists of transistor, and transistor comprises: source S, substrate B, drain D and grid G.
In NOR Flash storage unit, transistorized grid G and word line WL(Word Line) be connected, transistorized drain D and bit line BL(Bit Line) be connected, transistorized source S and source line SL(Source Line) be connected transistorized substrate B and substrate lines SUBL(Substrate Line) be connected.
Specific implementation method to the tradition programming of NOR Flash storage unit is: on word line WL, apply word line program voltage Vwl0, apply bit line program voltage Vbl0 on bit line BL.Source line SL and substrate lines SUBL ground connection.To the programming of NOR flash storage unit be by use mode that channel hot electron injects (Channel Hot Electron Injection) by the electronic injection of source electrode (source) in the middle of floating boom (floating gate), thereby cause the threshold voltage vt h0 of NOR Flash storage unit to increase, be programmed into logical zero, complete the central programming part of test.
The implementation method that tradition is wiped is: on word line WL, apply word line erase voltage Vwl1; Bit line BL is unsettled; On source line SL and substrate lines SUBL, apply source line and substrate lines erasing voltage Vsl1.To wiping of NOR Flash storage unit, be by using the mode of F-N tunnelling that the electronics " suction " in storage unit floating boom (floating gate) is arrived to raceway groove and source terminal, thereby cause the threshold voltage vt h1 of storage unit to reduce, be erased to " 1 ", complete the part of wiping in the middle of testing.
Summary of the invention
The more defect that expends time in while testing for nonvolatile memory of the prior art, the device and method for nonvolatile memory test that provides a kind of and save time, raise the efficiency.
The technical scheme that technical solution problem of the present invention adopts: a kind of device for nonvolatile memory test is provided, comprises:
For driving pending nonvolatile memory to carry out the programming driver module of programming operation,
For driving described nonvolatile memory to carry out the driver module of wiping of erase operation,
For the clock load module of input clock signal,
For controlling described programming driver module according to the clock signal of described clock load module input, described nonvolatile memory is carried out to the programming operation programming Control module of scheduled duration, and
Described in controlling according to the clock signal of described clock load module input, wipe the wipe control module of driver module to the erase operation of described nonvolatile memory execution scheduled duration.
The invention provides a kind of device for nonvolatile memory test, comprising:
For driving described nonvolatile memory to carry out the programming driver module of programming operation,
For driving described nonvolatile memory to carry out the driver module of wiping of erase operation,
For the clock load module of input clock signal,
For detection of the current detection module of the bit line program electric current of described nonvolatile memory,
For current value that described current detection module is detected with described predefined threshold value compares and export the comparator module of a trigger pip according to result relatively,
For control described programming driver module according to described trigger pip, described nonvolatile memory is carried out to the programming Control module of the programming operation of scheduled duration, and
Described in controlling according to the clock signal of described clock load module input, wipe the wipe control module of driver module to the erase operation of described nonvolatile memory execution scheduled duration.
Preferably, described comparator module is voltage comparator, the described device for nonvolatile memory test also comprises for current signal being converted to the modular converter of voltage signal, and described modular converter communication connection is between described current detection module and described comparator module.
The invention provides a kind of method for nonvolatile memory test, described nonvolatile memory is once programmed completely and is respectively T1 and T2 with the time of wiping completely, comprises the steps:
S1: described nonvolatile memory is carried out to the programming operation that duration is t1, and wherein t1 is less than T1;
S2: described nonvolatile memory is carried out to the erase operation that duration is t2, and wherein t2 is less than T2;
S3: alternately repeat successively described programming operation and described erase operation pre-determined number.
Preferably, described step S1 is further: input the first clock signal, according to described the first clock signal, described nonvolatile memory is carried out to the programming operation that duration is t1, wherein t1 is less than T1.
Preferably, described step S1 comprises the following steps:
S1.1: set scheduled duration t1, wherein t1 is less than T1;
S1.2: the threshold value that the bit line program electric current of described nonvolatile memory is set according to t1 correspondence;
S1.3: detect the size of described bit line program electric current, when described bit line program electric current reaches described threshold value, stop the programming operation to described nonvolatile memory.
Preferably, described step S2 is further: input second clock signal, according to described second clock signal, described nonvolatile memory is carried out to the programming operation that duration is t2, and wherein t2 is less than T2.
Preferably, when driving described nonvolatile memory to carry out programming operation, improve programming driving voltage.
Device and method for nonvolatile memory test provided by the invention has following beneficial effect with respect to prior art: the erase operation and the programming operation that nonvolatile memory are carried out to the schedule time, the time of the time of programming operation and erase operation is reduced to and is carried out once in the time of complete programming operation and the time of complete erase operation, to reduce the time of each programming operation and the time of each erase operation, make greatly to reduce at the execution programming operation of pre-determined number and the time of programming operation, have and save time, the beneficial effect of raising the efficiency.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is the theory diagram of the device for nonvolatile memory test in first embodiment of the invention;
Fig. 2 is the theory diagram of the device for nonvolatile memory test in second embodiment of the invention;
Fig. 3 is the FB(flow block) of a kind of method for nonvolatile memory test provided by the invention;
Fig. 4 is the theory diagram more specifically of the device of the nonvolatile memory test in embodiment illustrated in fig. 1;
Fig. 5 is a kind of oscillogram of S0 clock signal and S1 clock signal in Fig. 4;
Fig. 6 is when nonvolatile memory is carried out to programming operation, the comparison diagram of the injection electric charge number of floating boom and the threshold voltage of the nonvolatile memory variation of corresponding time under different program voltages;
Fig. 7 is when nonvolatile memory is carried out to programming operation, the comparison diagram of the variation of corresponding time under different erasing voltages from the electric charge number of floating boom sucking-off and the threshold voltage of nonvolatile memory.
Embodiment
Fig. 1 shows a kind of device for nonvolatile memory test in first embodiment of the invention, comprises programming Control module 10, clock load module 20, wipes control module 30, programming driver module 40, wipes driver module 50.Clock load module 20 is respectively with programming Control module 10 and wipe control module 30 communication connection, and programming Control module 10 and 40 communication connections of programming driver module, wipe control module 30 and wipe driver module 50 communication connections.Programming driver module 40 with wipe driver module 50 and be connected with pending nonvolatile memory 60 respectively.
Wherein, programming driver module 40 is for driving nonvolatile memory 60 to carry out programming operation.Wipe driver module 50 for driving nonvolatile memory 60 to carry out erase operation.Programming driver module 40 and wipe driver module 50 and all adopt common drive circuit to make.
Clock load module 20 is for inputting respectively the first clock signal and second clock signal to programming Control module 10 and wiping control module 30.Clock load module 20 can be clock interface, and this clock interface is for being connected to input respectively the first clock signal and second clock signal to programming Control module 10 and wiping control module 30 with the timer of nonvolatile memory 60.This clock load module 20 can also be timer, and this timer is directly for programming Control module 10 and control module 30 the first clock signal and second clock signal while providing are provided.This first clock signal and second clock signal are what set in advance, it makes nonvolatile memory 60 alternately carry out successively programming operation and erase operation, and the time of each programming operation and erase operation is less than respectively the time of once programming completely and wiping completely.
Programming Control module 10 is for controlling the programming operation that 40 pairs of nonvolatile memories of programming driver module 60 are carried out scheduled duration according to the clock signal of clock load module 20.Wipe control module 30 and wipe for controlling according to the clock signal of clock load module 20 input the erase operation that 30 pairs of nonvolatile memories of driver module 60 are carried out scheduled durations.Programming Control module 10 and wipe and control 30 of moulds and all can be microcontroller.Understandably, clock load module 20 also can be integrated in this microcontroller.
As shown in Figure 3, be the basic procedure block diagram of the method for nonvolatile memory test, in the present embodiment, it comprises the steps:
S0: obtain time T 1 and T2 that pending nonvolatile memory 60 is once programmed completely and wiped completely.
S1: the first clock signal that 20 inputs of clock load module are scheduled to is to programming Control module 10, programming Control module 10 is controlled 40 pairs of nonvolatile memories of programming driver module 60 according to this first clock signal and is carried out the programming operation that duration is t1, and wherein t1 is less than T1.
S2: clock load module 20 is inputted predetermined second clock signal to wiping control module 30, wipe control module 30 and according to this second clock signal controlling, wipe 50 pairs of nonvolatile memories of driver module 60 and carry out the erase operation that duration is t2, wherein t2 is less than T2;
S3: alternately repeat successively described programming operation and described erase operation pre-determined number.This pre-determined number can be determined according to the concrete condition of nonvolatile memory 60, can be 50 times, 100 times, 200 inferior.
Fig. 2 shows the device for nonvolatile memory test in the second embodiment.This embodiment increases current detection module 70, modular converter 80 and comparator module 90 on the basis of above-described embodiment.Current detection module 70 is connected with the bit line program interface of nonvolatile memory 60, and the input end of comparator module 90 is connected with modular converter 80, and the output terminal of comparator module 90 is connected with programming Control module 10.In the present embodiment, 20 of clock load modules need to provide predetermined clock signal for wiping control module 30 in addition, therefore only with wipe control module 30 communication connections.
Bit line program electric current is to reduce gradually along with the carrying out of programming operation, therefore according to the degree of hope programming, select a predetermined programming duration as required, bit line program electric current while obtaining through this predetermined programming duration according to this programming duration calculation or detection, and be threshold current by bit line program current settings now, when bit line program electric current is less than this threshold current, stop programming operation.This comparator module 90 is voltage comparator, its internal condition threshold current is provided with threshold voltage, current signal converts to after voltage signal, with the threshold voltage comparison of setting, when voltage signal reaches this threshold voltage, output trigger pip, to programming Control module 10, makes this programming Control module 10 control programming driver module 40 and drives nonvolatile memory 60 to stop programming operation.
The device for nonvolatile memory test in corresponding the second embodiment, provides a kind of method for nonvolatile memory test, comprises the steps:
S0: obtain time T 1 and T2 that nonvolatile memory 60 is once programmed completely and wiped completely;
S1: programming Control module 10 is controlled programming driver module 40 and driven nonvolatile memory 60 to carry out the programming operation that duration is t1, and wherein t1 is less than T1;
S2: the first clock signal that 20 inputs of clock load module are scheduled to is to wiping control module 30, wipe control module 30 and control and wipe 50 pairs of nonvolatile memories of driver module 60 and carry out the erase operation that duration is t2 according to this predetermined clock signal, wherein t2 is less than T2;
S3: alternately repeat successively programming operation and erase operation pre-determined number.This pre-determined number can be determined according to the concrete condition of nonvolatile memory 60, can be 50 times, 100 times, 200 inferior.
Step S1 comprises the following steps: S1.1: set scheduled duration t1, wherein t1 is less than T1;
S1.2: the threshold value that bit line program electric current is set according to t1 correspondence;
S1.3: current detection module 70 detects the size of described bit line program electric current, when bit line program electric current reaches the threshold value of electric current, stops the programming operation to nonvolatile memory 60.Because current signal is inconvenient to compare, therefore become corresponding voltage signal to compare again threshold current and the bit line program current conversion detecting.
When driving described nonvolatile memory to carry out programming operation, improve programming driving voltage.
The proportionate relationship of the shared T1 of t1 in the present invention determines according to a plurality of factors, can draw a kind of nonvolatile memory by experiment test in advance and can reach best fast programming and the operating effect of wiping in the situation that t1 accounts for a certain number percent of T1.In programming of the present invention and erase operation, enter the electronics sum of floating boom and the electronics sum of sucking-off floating boom at every turn and equate in addition.
Understandably, as shown in Figure 4, the programming driver module 40 in the first embodiment further comprises bit line program driver module and word line program driver module.Bit line program driver module that is to say that for the bit line to nonvolatile memory 60 transistorized drain electrode applies a bit line program voltage, and word line program driver module that is to say that to the word line of nonvolatile memory 60 transistorized grid applies a word line program voltage.Programming Control module is connected with word line program driver module with bit line program driver module respectively.
Wipe driver module 50 and further comprise that word line erase driver module and source line wipe driver module.Word line erase driver module applies a word line erase voltage for the word line to nonvolatile memory 60; Source line is wiped driver module and is applied a source line erasing voltage for the source line to nonvolatile memory 60.
As shown in Figure 5, the first clock signal is S0 clock signal, and second clock signal is S1 clock signal.S0 clock signal and S1 clock signal are respectively that clock load module 20 is input to programming Control module 10 and the clock signal of wiping control module 30.And clock signal S0 and clock signal S1 are complementary, that is to say that clock signal S1 is positioned at low level when clock signal S0 is positioned at high level, and when clock signal S0 is positioned at low level, clock signal S1 is positioned at high level.
In S0 clock signal, when being low level, programming Control module 10 is sent control signal to bit line program driver module and word line program driver module, switch S 0 closure of word line program driver module; The switch S 0 of bit line program driver module is also closed; Control switch S 0 closure between source electrode and ground simultaneously, make source ground, this nonvolatile memory 60 starts to carry out programming operation.
When S1 clock signal is low level, wiping control module 30 sends control signal and wipes driver module to word line erase driver module and source line, the switch S 1 of word line erase driver module and source line are wiped switch S 1 closure of driver module, and this nonvolatile memory 60 starts to carry out erase operation.
Certainly S0 clock signal and S1 clock signal also can only adopt a clock signal, and driving switch S1 and switch S 0 action when its high level and low level respectively, to reach the object of controlling programming operation and erase operation.
In to the programming and erase process of NOR Flash storage unit, the charge number of " injection " or quilt " sucking-off " storage unit floating boom is successively decreased rapidly in time.According to the first row of Fig. 6, can find out, in the programming operation of storage unit test, t1 only has the electric charge of minority to enter into floating boom constantly, that is to say one-time programming a period of time below in the operating cycle, i.e. the programming effect of t time is very little to the effect of storage unit test.Equally, from the first row of Fig. 7, can find out, in the erase operation in test, t2 only has the electric charge of minority from floating boom quilt " suction " to substrate constantly, that is to say a period of time below in erase operation, the scrubbing action of t3 time is very little to the effect of storage unit test.
As shown in Figure 6, in the secondary series of Fig. 6, word line program voltage is 9.5V, bit line program voltage is 3.5V, in the 3rd row and the 4th row, word line program voltage and bit line program voltage have been improved respectively, in identical time t1, improve respectively after word line program voltage or bit line program voltage, the threshold voltage vt h0 of the quantity of electric charge of injection and this storage unit has increased.Improve the effect that word line program voltage or bit line program voltage can strengthen programming operation, that is to say the effect that will reach identical, after word line program voltage or bit line program voltage, the time needing is shorter.As shown in Figure 7, in the secondary series of Fig. 7, source line erasing voltage is 7.7V, and word line erase voltage is-9.5V.In the 3rd row and the 4th row, improve respectively after source line erasing voltage or word line erase voltage, in identical time t2, the amount of charge showed increased of sucking-off from floating boom, that is to say that wiping effect has strengthened.So, needs reach identical wipe effect in, improve source line erasing voltage or word line erase voltage and can reduce the test duration.
Therefore, in the present invention, for driving nonvolatile memory 60 to carry out the programming driver module 40 of programming operation or erase operation and wipe driver module 50 all adopting outside regulated power supply to power, to obtain higher driving voltage.
Should be understood that, for those of ordinary skills, can be improved according to the above description or convert, and all these improvement and conversion all should belong to the protection domain of claims of the present invention.
Claims (7)
1. for a device for nonvolatile memory test, it is characterized in that, comprising:
For driving pending nonvolatile memory (60) to carry out the programming driver module (40) of programming operation,
Be used for driving that described nonvolatile memory (60) carries out erase operation wipes driver module (50),
For the clock load module (20) of input clock signal,
For controlling described programming driver module (40) according to the clock signal of described clock load module (20) input, described nonvolatile memory (60) is carried out to the programming operation programming Control module (10) of scheduled duration, and
For wipe described in controlling according to the clock signal of described clock load module (20) input driver module (50) described nonvolatile memory (60) is carried out scheduled duration erase operation wipe control module (30).
2. for a device for nonvolatile memory test, it is characterized in that, comprising:
Be used for driving described nonvolatile memory (60) to carry out the programming driver module (40) of programming operation,
Be used for driving that described nonvolatile memory (60) carries out erase operation wipes driver module (50),
For the clock load module (20) of input clock signal,
For detection of the current detection module (70) of the bit line program electric current of described nonvolatile memory (60),
For current value that described current detection module (70) is detected with described predefined threshold value compares and export the comparator module (90) of a trigger pip according to result relatively,
For control described programming driver module (40) according to described trigger pip, described nonvolatile memory (60) is carried out to the programming Control module (10) of the programming operation of scheduled duration, and
For wipe described in controlling according to the clock signal of described clock load module (20) input driver module (50) described nonvolatile memory (60) is carried out scheduled duration erase operation wipe control module (30).
3. the device for nonvolatile memory test according to claim 2, it is characterized in that, described comparator module (90) is voltage comparator, the described device for nonvolatile memory test also comprises that, for current signal being converted to the modular converter (80) of voltage signal, described modular converter (80) communicates to connect between described current detection module (70) and described comparator module (90).
4. for a method for nonvolatile memory test, described nonvolatile memory is once programmed completely and is respectively T1 and T2 with the time of wiping completely, it is characterized in that, comprises the steps:
S1: described nonvolatile memory (60) is carried out to the programming operation that duration is t1, and wherein t1 is less than T1;
S2: described nonvolatile memory (60) is carried out to the erase operation that duration is t2, and wherein t2 is less than T2;
S3: alternately repeat successively described programming operation and described erase operation pre-determined number.
5. the method for nonvolatile memory test according to claim 4, it is characterized in that, described step S1 is further: input the first clock signal, according to described the first clock signal, described nonvolatile memory (60) is carried out to the programming operation that duration is t1, wherein t1 is less than T1.
6. the method for nonvolatile memory test according to claim 4, is characterized in that, described step S1 comprises the following steps:
S1.1: set scheduled duration t1, wherein t1 is less than T1;
S1.2: the threshold value that the bit line program electric current of described nonvolatile memory (60) is set according to t1 correspondence;
S1.3: detect the size of described bit line program electric current, when described bit line program electric current reaches described threshold value, stop the programming operation to described nonvolatile memory (60).
7. according to the method for nonvolatile memory test described in claim 5 or 6, it is characterized in that, described step S2 is further: input second clock signal, according to described second clock signal, described nonvolatile memory (60) is carried out to the programming operation that duration is t2, wherein t2 is less than T2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310477361.0A CN103531249B (en) | 2013-10-12 | Device and method for nonvolatile memory test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310477361.0A CN103531249B (en) | 2013-10-12 | Device and method for nonvolatile memory test |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103531249A true CN103531249A (en) | 2014-01-22 |
| CN103531249B CN103531249B (en) | 2016-11-30 |
Family
ID=
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106920577A (en) * | 2015-12-24 | 2017-07-04 | 北京兆易创新科技股份有限公司 | The detection method of memory chip, detection means and detecting system |
| CN111261218A (en) * | 2020-04-27 | 2020-06-09 | 深圳市芯天下技术有限公司 | Method for simultaneously testing multiple Norflash samples |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6076138A (en) * | 1996-12-28 | 2000-06-13 | Hyundai Electronics Industries Co., Ltd. | Method of pre-programming a flash memory cell |
| CN101859606A (en) * | 2009-04-07 | 2010-10-13 | 北京芯技佳易微电子科技有限公司 | Method and equipment for adjusting reference unit threshold parameter and testing system |
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6076138A (en) * | 1996-12-28 | 2000-06-13 | Hyundai Electronics Industries Co., Ltd. | Method of pre-programming a flash memory cell |
| CN101859606A (en) * | 2009-04-07 | 2010-10-13 | 北京芯技佳易微电子科技有限公司 | Method and equipment for adjusting reference unit threshold parameter and testing system |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106920577A (en) * | 2015-12-24 | 2017-07-04 | 北京兆易创新科技股份有限公司 | The detection method of memory chip, detection means and detecting system |
| CN111261218A (en) * | 2020-04-27 | 2020-06-09 | 深圳市芯天下技术有限公司 | Method for simultaneously testing multiple Norflash samples |
| CN111261218B (en) * | 2020-04-27 | 2020-08-21 | 深圳市芯天下技术有限公司 | Method for simultaneously testing multiple Norflash samples |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102422362A (en) | Multiple level program verify in a memory device | |
| CN106128352A (en) | GOA unit, driving method, GOA circuit and display device | |
| US20140204694A1 (en) | Systems and methods for adaptive soft programming for non-volatile memory using temperature sensor | |
| CN101667446A (en) | Memory and reading method thereof | |
| CN103066972B (en) | Power-on reset circuit with global enabling pulse control automatic reset function | |
| CN105741877A (en) | Sensing circuit, memory device and method for operating memory device | |
| CN109584933B (en) | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers | |
| CN110619915A (en) | Novel over-erasing processing method and device for nonvolatile memory | |
| CN103811068A (en) | Method and system for erasing nonvolatile memory | |
| US7428172B2 (en) | Concurrent programming and program verification of floating gate transistor | |
| CN103426472A (en) | Programming system and method of Nor Flash memory | |
| CN101847432A (en) | Power supply structure of memory | |
| CN106486161A (en) | A kind of anti-interference method of NANDFLASH programming | |
| CN103531249A (en) | Device applied to nonvolatile memory test and method thereof | |
| CN103531249B (en) | Device and method for nonvolatile memory test | |
| EP2369593B1 (en) | Channel hot electron injection programming method and related device | |
| EP2498258A1 (en) | Non-volatile memory device with program current clamp and related method | |
| US10109356B2 (en) | Method and apparatus for stressing a non-volatile memory | |
| CN103853637A (en) | Turn-on/turn-off test circuit | |
| CN102800356A (en) | Reference unit programming method and system of nonvolatile memory | |
| CN103000224A (en) | Memory chip erasing method | |
| CN102543198B (en) | A kind of programmed method of MLC memory cell and device | |
| US8391069B2 (en) | Programming method for nonvolatile semiconductor memory device | |
| CN110299172A (en) | A kind of programmed process method shortening FLASH programming time | |
| US20120314507A1 (en) | Reduced voltage nonvolatile flash memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20171218 Address after: 518000 Henggang street, Shenzhen, Guangdong, Henggang street, Longgang Avenue, No. 8288 Da Yun software Town, tenth Building 1 Patentee after: Paragon Technology (Shenzhen) Ltd. Address before: 518057 Nanshan District science and Technology Park, Guangdong science and Technology Park, South Road, Changhong science and technology building, building 10, room 5-8 Patentee before: FREMONT MICRO DEVICES (SHENZHEN) Ltd. |
|
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 518000 Room 101, building 10, Dayun software Town, 8288 Longgang Avenue, he'ao community, Yuanshan street, Longgang District, Shenzhen City, Guangdong Province Patentee after: XTX Technology Inc. Address before: 518000 1st floor, building 10, Dayun software Town, 8288 Longgang Avenue, Henggang street, Longgang District, Shenzhen City, Guangdong Province Patentee before: Paragon Technology (Shenzhen) Ltd. |