CN103530215A - Self-inspection method and device of inter integrated circuit host and host - Google Patents
Self-inspection method and device of inter integrated circuit host and host Download PDFInfo
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Abstract
The invention discloses a self-inspection method and device of an inter integrated circuit host and the host, and belongs to the technical field of communication. The method comprises the steps that the I2C host detects whether an I2C bus is busy; when the I2C bus is busy, data packets transmitted on the I2C bus are received, and whether a link of the I2C host is normal is detected according to the data packets. According to the method, when the I2C bus is busy, the data packets transmitted on the I2C bus are received, whether the link of the I2C host is normal is detected according to the data packets, and therefore it is not necessary to wait to conduct self-inspection of the I2C host when the I2C bus is free, self-inspection can be conducted in real time, and the problem that when the I2C host waits for self-inspection, the I2C host controlling the I2C bus at present breaks down and cannot be replaced by a spare I2C host, and therefore the I2C host controlling the I2C bus is changed repeatedly is solved.
Description
Technical field
The present invention relates to communication technical field, particularly a kind of self checking method of internal integrated circuit main frame, device and main frame.
Background technology
I2C(Inter Integrated Circuit, internal integrated circuit) bus is a kind of bus standard that microelectronics Control on Communication field extensively adopts, for connecting the devices such as I2C main frame, I2C slave.I2C main frame is the device that initialization transmission, clocking and termination send, and can become the device of controlling I2C bus, and I2C slave is by the device of I2C host addressing.
Conventionally in I2C bus, be only provided with a main frame.If be connected with two I2C main frames in I2C bus, one is the I2C main frame of current control I2C bus, and another is standby I2C main frame.The I2C main frame that the I2C main frame of take is current control I2C bus, the 2nd I2C main frame is that standby I2C main frame is example, when an I2C main frame breaks down, the 2nd I2C main frame can replace an I2C host computer control I2C bus.If the 2nd I2C main frame can not be controlled I2C bus, an I2C main frame can replace again the 2nd I2C host computer control I2C bus.Because fault has appearred in an I2C main frame, therefore an I2C main frame can not be controlled I2C bus, the 2nd I2C main frame replaces an I2C host computer control I2C bus again, so repeatedly, causes I2C bus and is connected to the device cisco unity malfunction in I2C bus.
For fear of occurring this problem, when standby I2C main frame is connected with I2C bus, standby I2C main frame can carry out self check, when guaranteeing that I2C main frame (as an I2C main frame) that standby I2C main frame (as the 2nd I2C main frame) replaces current control I2C bus is controlled I2C bus, can control I2C bus.The self checking method of existing I2C main frame comprises: standby I2C main frame at I2C total online application I2C bus resource until this I2C host computer control I2C bus; After this I2C host computer control I2C bus, to I2C slave, send packet; If receive the response signal of I2C slave, judge that this I2C main frame can control I2C bus.
In realizing process of the present invention, inventor finds that prior art at least exists following problem:
Standby I2C main frame only has when I2C bus is idle by the time, could control I2C bus, and only have after this I2C host computer control I2C bus, could send packet to I2C slave, to judge that can this I2C main frame control I2C bus, therefore the self checking method of existing I2C main frame can not carry out in real time.If in the process of standby I2C host waits I2C bus free time, having there is fault in the I2C main frame of current control I2C bus, can not avoid occurring repeatedly changing the problem of the I2C main frame of controlling I2C bus.
Summary of the invention
In order to solve prior art, can not carry out in real time, can not avoid occurring repeatedly changing the problem of the I2C main frame of controlling I2C bus, the embodiment of the present invention provides a kind of self checking method, device and main frame of internal integrated circuit I2C main frame.Described technical scheme is as follows:
On the one hand, the embodiment of the present invention provides a kind of self checking method of internal integrated circuit I2C main frame, and described I2C main frame is connected with I2C bus by the link of described I2C main frame, and described method comprises:
Whether I2C Host Detection I2C bus is busy;
When described I2C bus is busy, receive the packet transmitting in described I2C bus, and whether according to described packet, detect the link of described I2C main frame normal.
In the possible implementation of the first, described I2C main frame comprises main equipment and from equipment, described main equipment is connected with described I2C bus by the link of described I2C main frame, describedly from equipment, is connected with described main equipment, and described method also comprises:
When described I2C bus is busy, control described main equipment from described from equipment reading out data and to described from equipment data writing, whether normal to detect the read-write capability of described I2C main frame;
When the link read-write capability normal and described I2C main frame of described I2C main frame is normal, judge that described I2C main frame can control described I2C bus.
Whether alternatively, the described main equipment of described control is from described from equipment read data and to described from equipment data writing, normal to detect the read-write capability of described I2C main frame, comprising:
Control described main equipment from the described preset data that reads from equipment, when data that described main equipment reads are identical with preset data in described main equipment, judge described I2C main frame to read function normal, when data that described main equipment reads are different from preset data in described main equipment, judge described I2C main frame to read function undesired;
Controlling described main equipment writes the preset data in described main equipment described from equipment, when described in described main equipment writes, the data from equipment are identical with described preset data from equipment, judge described I2C main frame to write function normal, when described main equipment writes described data from equipment when different from described preset data from equipment, judge described I2C main frame to write function undesired.
In the possible implementation of the second, described I2C bus comprises serial time clock line and serial data line, the link of described I2C main frame comprises serial clock link and serial data link, the packet transmitting in the described I2C bus of described reception, and whether normal, comprising if according to described packet, detecting the link of described I2C main frame:
Receive the clock signal on described serial time clock line, whether identically with default standard clock signal detect described clock signal, whether normal to judge described serial clock link;
Receive first response signal after start signal on described serial data line, whether first response signal detecting after described start signal is identical with default normal response signal, to judge that whether described serial data link is normal;
When described serial clock link is normal and described serial data link is normal, judge that the link of described I2C main frame is normal.
Whether alternatively, whether the described clock signal of described detection is identical with default standard clock signal, normal to judge described serial clock link, comprising:
Within the sampling time, using first signal as with reference to signal, described clock signal to be sampled, and record the quantity that sampled result is high level, the frequency of described first signal is n times of described standard clock signal frequency, n >=2 and n are integer;
Whether the high level quantity of detection record is identical with predetermined quantity, and described predetermined quantity is within the described sampling time, usings described first signal as with reference to signal, to the described standard clock signal quantity that the sampled result that obtains is high level of sampling;
When the high level quantity of described record being detected when identical with described predetermined quantity, judge that described serial clock link is normal;
When the high level quantity of described record being detected when different from described predetermined quantity, judge that described serial clock link is undesired.
Alternatively, whether first response signal after the described start signal of described detection is identical with default normal response signal, to judge that whether described serial data link is normal, comprising:
When first response signal after described start signal is low level, judge that described serial data link is normal;
When first response signal after described start signal is high level, judge that described serial data link is undesired.
Further, whether first response signal after the described start signal of described detection is identical with default normal response signal, to judge that whether described serial data link is normal, also comprises:
When second response signal after first response signal after described data direction position, described start signal, described start signal is low level, or,
It is signal after second response signal after low level, described start signal while being stop signal that second response signal after described data direction position and described start signal is first response signal after high level, described start signal, or,
When second response signal after first response signal after described data direction position is high level, described start signal and described start signal is signal after second response signal after low level, described start signal and is not stop signal, judge that described serial data link is normal;
Otherwise, judge that described serial data link is undesired.
In the third possible implementation, described method also comprises:
When described I2C bus is idle, controls described I2C bus, and send preset data bag to I2C slave;
When receiving the response signal that described I2C slave sends, judge that described I2C main frame can control described I2C bus.
On the other hand, the embodiment of the present invention provides a kind of self-checking unit of internal integrated circuit I2C main frame, and described I2C main frame is connected with I2C bus by the link of described I2C main frame, and described device comprises:
Bus detection module, whether busy for detection of I2C bus;
Link detecting module, for when described I2C bus is busy, receives the packet transmitting in described I2C bus, and whether according to described packet, detect the link of described I2C main frame normal.
In the possible implementation of the first, described I2C main frame comprises main equipment and from equipment, described main equipment is connected with described I2C bus by the link of described I2C main frame, describedly from equipment, is connected with described main equipment, and described device also comprises:
Whether read-write capability detection module, for when described I2C bus is busy, controls described main equipment from described from equipment reading out data and to described from equipment data writing, normal to detect the read-write capability of described I2C main frame;
Judge module, when read-write capability normal for the link when described I2C main frame and described I2C main frame is normal, judges that described I2C main frame can control described I2C bus.
Alternatively, described read-write capability detection module comprises:
Read comparing unit, be used for controlling described main equipment and from equipment, read preset data from described, when data that described main equipment reads are identical with preset data in described main equipment, judge described I2C main frame to read function normal, when data that described main equipment reads are different from preset data in described main equipment, judge described I2C main frame to read function undesired;
Write comparing unit, for controlling described main equipment, the preset data of described main equipment is write described from equipment, when described in described main equipment writes, the data from equipment are identical with described preset data from equipment, judge described I2C main frame to write function normal, when described main equipment writes described data from equipment when different from described preset data from equipment, judge described I2C main frame to write function undesired.
In the possible implementation of the second, described I2C bus comprises serial time clock line and serial data line, and the link of described I2C main frame comprises serial clock link and serial data link, and described link detecting module comprises:
Whether whether identical with default standard clock signal serial clock link detecting unit, for receiving the clock signal on described serial time clock line, detect described clock signal, normal to judge described serial clock link;
Serial data link detecting unit, for receiving first response signal after start signal on described serial data line, whether first response signal detecting after described start signal is identical with default normal response signal, to judge that whether described serial data link is normal;
Judging unit, for when described serial clock link is normal and described serial data link is normal, judges that the link of described I2C main frame is normal.
Alternatively, described serial clock link detecting unit comprises:
Sampling subelement, within the sampling time, usings first signal as with reference to signal, described clock signal is sampled, and record the quantity that sampled result is high level, and the frequency of described first signal is n times of described standard clock signal frequency, n >=2 and n are integer;
Quantity detection sub-unit, whether the high level quantity for detection of record is identical with predetermined quantity, described predetermined quantity is within the described sampling time, usings described first signal as with reference to signal, to the described standard clock signal quantity that the sampled result that obtains is high level of sampling; When the high level quantity of described record being detected when identical with described predetermined quantity, judge that described serial clock link is normal; When the high level quantity of described record being detected when different from described predetermined quantity, judge that described serial clock link is undesired.
Alternatively, described serial data link detecting unit is used for,
When first response signal after described start signal is low level, judge that described serial data link is normal;
When first response signal after described start signal is high level, judge that described serial data link is undesired.
Further, described serial data link detecting unit also for,
When second response signal after first response signal after described data direction position, described start signal, described start signal is low level, or,
It is signal after second response signal after low level, described start signal while being stop signal that second response signal after described data direction position and described start signal is first response signal after high level, described start signal, or,
When second response signal after first response signal after described data direction position is high level, described start signal and described start signal is signal after second response signal after low level, described start signal and is not stop signal, judge that described serial data link is normal;
Otherwise, judge that described serial data link is undesired.
In the third possible implementation, described device also comprises:
Host Detection module, when idle for described I2C bus, controls I2C bus, and sends preset data bag to I2C slave;
Judge module, for when receiving the response signal that described I2C slave sends, judges that described I2C main frame can control described I2C bus.
Another aspect, the embodiment of the present invention provides a kind of internal integrated circuit I2C main frame, and described main frame comprises bus interface and processor, and described processor is for the self checking method of above-mentioned I2C main frame.
The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is:
By when I2C bus is busy, receive the packet transmitting in I2C bus, and according to this packet, detect the link of I2C main frame, therefore do not need when I2C bus is idle by the time just can carry out the self check of I2C main frame.The embodiment of the present invention can be carried out in real time, avoided in the process of I2C host waits self check, the I2C main frame of the current control I2C bus existing in appearance prior art breaks down, standby I2C main frame can not replace the I2C host computer control I2C bus of current control I2C bus, and causes the problem that the I2C main frame of I2C bus is changed repeatedly of controlling.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the application scenarios figure of the self checking method of a kind of I2C main frame of providing of the embodiment of the present invention;
Fig. 2 is the process flow diagram of the self checking method of a kind of I2C main frame of providing of the embodiment of the present invention one;
Fig. 3 is the process flow diagram of the self checking method of a kind of I2C main frame of providing of the embodiment of the present invention two;
Fig. 4 is the whether normal process flow diagram of the link of the detection I2C main frame that provides of the embodiment of the present invention two;
Fig. 5 is the process flow diagram of the self checking method of a kind of I2C main frame of providing of the embodiment of the present invention three;
Fig. 6 is the structural representation of the self-checking unit of a kind of I2C main frame of providing of the embodiment of the present invention four;
Fig. 7 is the structural representation of the self-checking unit of a kind of I2C main frame of providing of the embodiment of the present invention five;
Fig. 8 is the hardware structure diagram of a kind of I2C main frame of providing of the embodiment of the present invention six.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
First in conjunction with Fig. 1, simply introduce the application scenarios of the self checking method of the I2C main frame that the embodiment of the present invention provides, this application scenarios is only one of them application scenarios of the embodiment of the present invention, and the present invention is not restricted to this.
I2C bus is twin wire universal serial bus, comprises SCL(Serial Clock, serial clock) line and SDA(Serial Data, serial data) line, be generally used for connecting microcontroller and peripherals thereof.As shown in Figure 1, in order to guarantee the stable control to I2C bus, in I2C bus, be generally connected with primary and backup two I2C main frames, in embodiments of the present invention, be respectively an I2C main frame 1, the 2nd I2C main frame 2, easily know, primary I2C main frame refers to the I2C main frame of current control I2C bus, and standby I2C main frame refers to the I2C main frame of the current I2C of control bus.
In embodiments of the present invention, I2C main frame can be microcontroller, as CPLD (Complex Programmable Logic Device, CPLD), FPGA(Field Programmable Gate Array, field programmable gate array).
In I2C bus, be also connected with several I2C slaves, for example an I2C slave 3, the 2nd I2C slave 4 and the 3rd I2C slave 5.In embodiments of the present invention, I2C slave includes but not limited to LCD(Liquid Crystal Display, liquid crystal display) driver, I/O(Input/Output, I/O) mouthful (as keyboard interface), storer is (as RAM(Random Access Memory, random access memory), EEPROM(Electrically Erasable Programmable Read-Only Memory, EEPROM (Electrically Erasable Programmable Read Only Memo))), data converter, the DTMF(Dual Tone Multi Frequency of the digital tuning of radio and video system and signal processing circuit and voice-frequency dialing phone, dual-tone multifrequency) generator.
It should be noted that, in Fig. 1, the number of I2C main frame and I2C slave is only for giving an example, and the I2C number of host being connected with I2C bus can also increase, and I2C slave number can increase or reduce.
I2C main frame and I2C slave all the I2C link connection by separately in I2C bus 6.Particularly, between the one I2C main frame 1 and I2C bus 6, by the first link 16, connect, between the 2nd I2C main frame 2 and I2C bus 6, by the second link 26, connect, between the one I2C slave 3 and I2C bus 6, by the 3rd link 36, connect, between the 2nd I2C slave 4 and I2C bus 6, by the 4th link 46, connect, between the 3rd I2C slave 5 and I2C bus 6, by the 5th link 56, connect.Easily know, because I2C bus comprises scl line and sda line, so the link that I2C main frame or I2C slave are connected with I2C bus separately also comprises SCL link and two links of SDA link.
Embodiment mono-
The embodiment of the present invention provides a kind of self checking method of I2C main frame, and the method can be carried out when standby I2C main frame and I2C bus connect, and referring to Fig. 2, the method comprises:
Whether step 101:I2C Host Detection I2C bus is busy.
Step 102: when I2C bus is busy, receive the packet transmitting in I2C bus, and whether normal according to the link of this packet detection I2C main frame.
The embodiment of the present invention, by when I2C bus is busy, receives the packet transmitting in I2C bus, and according to this packet, detects the link of I2C main frame, does not therefore need when I2C bus is idle by the time just can carry out the self check of I2C main frame.The embodiment of the present invention can be carried out in real time, avoided in the process of I2C host waits self check, the I2C main frame of the current control I2C bus existing in appearance prior art breaks down, standby I2C main frame can not replace the I2C host computer control I2C bus of current control I2C bus, and causes the problem that the I2C main frame of I2C bus is changed repeatedly of controlling.
Embodiment bis-
The embodiment of the present invention provides a kind of self checking method of I2C main frame, and the method can be carried out when standby I2C main frame and I2C bus connect, and referring to Fig. 3, the method comprises:
Whether step 201:I2C Host Detection I2C bus is busy.
Whether particularly, this step 201 can comprise: detect on scl line and within the cycle of a default standard clock signal, have level to change; If there is level to change on scl line within the cycle of a default standard clock signal, I2C bus is busy; If do not have level to change on scl line within the cycle of a default standard clock signal, I2C bus is idle.
It should be noted that, according to I2C agreement, while carrying out data transmission in I2C bus, be that I2C bus is when busy, the level that there will be height to change on scl line, and cycle of changing of level be the cycle (time interval between two high level is the cycle of default standard clock signal) of default standard clock signal; While not carrying out data transmission in I2C bus, when I2C bus is idle, on scl line, remain high level.Conventionally in each I2C bus, can preset a standard clock signal, each equipment being connected with this I2C bus can get cycle and/or the frequency of the standard clock signal of this I2C bus.Under normal circumstances, the clock signal frequency on scl line is identical with this standard clock signal frequency.
Step 202: when I2C bus is busy, receive the packet transmitting in I2C bus, and whether normal according to the link of this packet detection I2C main frame.
Particularly, referring to Fig. 3, this step 202 can comprise:
Step 2021: receive the clock signal on scl line, whether identically with default standard clock signal detect this clock signal, to judge that whether SCL link is normal.
Alternatively, this step 2021 can comprise: within the sampling time, using first signal as with reference to signal, clock signal is sampled, and record the quantity that sampled result is high level; Whether the high level quantity of detection record is identical with predetermined quantity; When the high level quantity of record being detected when identical with predetermined quantity, judge that SCL link is normal; When the high level quantity of record being detected when different from predetermined quantity, judge that SCL link is undesired.
In the present embodiment, the frequency of first signal is n times of standard clock signal frequency, and n >=2 and n are integer.Predetermined quantity is within the sampling time, usings first signal as with reference to signal, to the standard clock signal quantity that the sampled result that obtains is high level of sampling.
Further, the sampling time can be the cycle of at least one standard clock signal.
Step 2022: receive first response signal after start signal on sda line, whether first response signal detecting after start signal is identical with default normal response signal, to judge that whether SDA link is normal.
Alternatively, this step 2022 can comprise: when first response signal after start signal is low level, judge that SDA link is normal; When first response signal after start signal is high level, judge that SDA link is undesired.
It should be noted that, in I2C agreement, stipulate, on sda line, must take byte as unit transmission data, response signal of each byte heel, but the byte quantity of transmission is unrestricted.Default normal response signal is for showing to receive successful response signal.Generally by low level response signal, show to receive successfully.But when I2C main frame reads the data of I2C slave, I2C main frame reads after the data of last byte of I2C slave, sda line can be remained to high level (because sda line and scl line are all connected to power supply by pull-up circuit, therefore only however operate that can to realize response signal be high level), to show to receive successfully, then I2C main frame sends stop signal (when scl line is high level, sda line switches to high level from low level).Except above-mentioned situation, generally, when response signal is high level, show to take defeat.
According to I2C agreement, while starting data transmission in I2C bus, first by I2C main frame, send start signal (when scl line is high level, sda line switches to low level from high level), then I2C main frame can send seven bit address and the data direction position with the I2C slave of this I2C main-machine communication, this seven bit address is the sign of I2C slave, can determine the I2C slave with I2C main-machine communication according to this address.When this I2C slave receives after seven bit address and data direction position of the transmission of I2C main frame, the level on sda line is dragged down, take and realize response signal as low level, show that I2C slave successfully receives seven bit address and data direction position that I2C main frame sends.Then according to data direction position, " 0 " (low level) represents that I2C main frame writes data into I2C slave, " 1 " (high level) represents that I2C main frame reads the data of I2C slave, between I2C main frame and I2C slave, start to take eight bit data as unit transmission data in I2C bus, after every eight bit data is transmitted, have a response signal, response signal is high level, or the side that low level receives data in I2C main frame and I2C slave determines.After data transmission completes, I2C main frame sends stop signal.
No matter the level of data direction position is high level or low level, and I2C main frame sends behind seven bit address and data direction position, if I2C slave successfully receives, is bound to the level on sda line to drag down, and making response signal is low level.In the process of data transmission, if I2C main frame writes I2C slave by data, I2C slave is every successfully to be received after eight bit data, all the level on sda line can be dragged down, and making response signal is low level; If I2C main frame reads the data of I2C slave, I2C main frame is every successfully to be received after eight bit data, generally also the level on sda line can be dragged down, making response signal is low level, only have and receive after last eight bit data when I2C main frame, just can keep sda line is high level, and response signal is high level.
Whether first response signal (showing whether I2C slave receives the response signal of seven bit address and data direction position) that therefore only need to detect after start signal is low level, be whether response signal is identical with normal response signal, can judge that whether SDA link is normal, determination methods is simple and convenient.The reason of selecting first response signal after start signal to judge, the one, the position of response signal is determined according to start signal, select first response signal to judge more convenient, the 2nd, this response signal only need just judge according to level, whether do not need to consider data direction position and be last bit data of data transmission, judgement is got up fairly simple.
Further, this step 2022 can also comprise: when data direction position, first response signal after start signal, when second response signal after start signal is low level, or second response signal after data direction position and start signal is high level, first response signal after start signal is low level, when the signal after second response signal after start signal is stop signal, or when data direction position is high level, first response signal after start signal and first response signal after start signal are low level, when the signal after second response signal after start signal is not stop signal, judge that SDA link is normal, otherwise, judge that SDA link is undesired.To prevent that first response signal after start signal from being that maloperation due to I2C bus becomes low level signal, by what may abnormal SDA link be mistaken for, improved the reliability detecting, reduced risk.
Easily know, this step 2022 can also according to the 3rd response signal after start signal, the 4th response signal ..., or even last response signal judge SDA link, the present invention to judgement which response signal after start signal, judge that several response signals do not limit, first response signal and second response signal that detect after start signal are just preferred, and the present invention is not restricted to this.
Step 2023: when SCL link being detected normally and SDA link is normal, judge that the link of I2C main frame is normal.
Step 203: when I2C bus is busy, control master(main equipment) from salve(from equipment) whether reading out data to salve data writing is normal to detect the read-write capability of I2C main frame.
In the present embodiment, this step 203 is carried out after step 201, there is no sequencing with step 202.
In the present embodiment, I2C main frame can comprise Controller(controller), master(main equipment), slave(is from equipment), clock counter and ACK(Acknowledgement, confirm) counter.Controller is for controlling the execution of I2C main frame self check and the judgement of self-detection result.Master is for controlling I2C bus and the read-write capability that completes I2C main frame, master can also be for reading preset data from slave, with judge I2C main frame whether read function normal, to slave, write preset data so that slave judge I2C main frame whether write function normal.Clock counter is for realizing the counting of clock signal on scl line, and ACK counter is for realizing the counting of low level response signal on sda line.Master is connected with I2C main frame by the link of I2C main frame, and salve, clock counter, ACK counter are connected with master respectively, and Controller is connected with master, salve, clock counter, ACK counter respectively.Wherein, Controller, master, clock counter, ACK counter can be the components and parts in existing I2C main frame, and salve is the device that the embodiment of the present invention increases in I2C main frame.Salve can be the components and parts identical with I2C slave, as storer, but salve is different from I2C slave, and I2C slave is connected with I2C bus, salve also comprises for the whether identical device of comparing data, as comparer, processor etc. with master connection and salve.
Particularly, this step 203 can comprise: control master and from salve, read preset data, when data that master reads are identical with preset data in master, judge I2C main frame to read function normal, when data that master reads are different from preset data in master, judge I2C main frame to read function undesired; Control master the preset data in master is write to salve, when master writes data in salve when identical with preset data in salve, judge I2C main frame to write function normal, when master writes data in salve when different from preset data in salve, judge I2C main frame to write function undesired.
It should be noted that, preset data is before step 203, is stored in the data in master and salve, and the preset data in master and the preset data in salve are identical.
Step 204: when the link read-write capability normal and I2C main frame of I2C main frame being detected when normal, judge that I2C main frame can control I2C bus.This step 204 is carried out after step 202 and step 203.
In a kind of implementation of the present embodiment, the method can also comprise step 205 and step 206.
Step 205: when I2C bus is idle, control I2C bus, and send preset data bag to I2C slave.This step 205 is carried out after step 201.
Preferably, preset data bag can take the data that I2C bus time is few for a bag, as only includes the packet of seven bit address, data direction position and eight bit data.
Alternatively, I2C slave can be selected arbitrarily, can be also predefined.
Step 206: when receiving the response signal of I2C slave transmission, judgement I2C main frame can be controlled I2C bus.This step 206 is carried out after step 205.
Easily know, before step 202, the method can also comprise step: from I2C pattern, switch to GPIO(General Purpose Input/Output, general input/output port) pattern.
Correspondingly, after step 202, the method also comprises step: from GPIO pattern, switch to I2C pattern.
Wherein, I2C main frame is under GPIO pattern, and the level only detecting in I2C bus changes, and does not carry out data processing.
The embodiment of the present invention is by when I2C bus is busy, receive the packet transmitting in I2C bus, and according to the link of this packet detection I2C main frame, control master from salve reading out data and to salve data writing, whether the read-write capability with detection I2C main frame is normal, and then judge that can this I2C main frame control I2C bus, therefore do not need when I2C bus is idle by the time just can carry out the self check of I2C main frame.The embodiment of the present invention can be carried out in real time, avoided in the process of I2C host waits self check, the I2C main frame of the current control I2C bus existing in appearance prior art breaks down, standby I2C main frame can not replace the I2C host computer control I2C bus of current control I2C bus, and causes the problem that the device of I2C bus is changed repeatedly of controlling.And read-write capability two aspects of the link of I2C main frame and I2C main frame are detected simultaneously, improved the accuracy of testing result.
Embodiment tri-
The embodiment of the present invention provides a kind of self checking method of I2C main frame, is a kind of improvement to embodiment bis-, and the method can be carried out when standby I2C main frame and I2C bus connect, and referring to Fig. 5, the method comprises:
Whether step 301:I2C Host Detection I2C bus is busy.When I2C bus is idle, perform step 302; When I2C bus is busy, perform step 303.
Alternatively, this step 301 can be identical with the step 201 in embodiment bis-, is not described in detail in this.
Step 302: control I2C bus, send preset data bag to I2C slave, and according to whether receiving the response signal that I2C slave sends, can judgement I2C main frame control I2C bus.
Alternatively, this step 302 can comprise: when receiving the response signal of I2C slave transmission, judgement I2C main frame can be controlled I2C bus; When not receiving the response signal of I2C slave transmission, judgement I2C main frame can not be controlled I2C bus.
Step 303: receive the clock signal on scl line, whether identically with default standard clock signal detect the clock signal receiving, and judge that according to the testing result of clock signal whether SCL link is normal.When SCL link is normal, perform step 304; When SCL link is undesired, perform step 305.
Alternatively, this step 303 can be identical with the step 2021 in embodiment bis-, is not described in detail in this.
Step 304: receive first response signal after start signal on sda line, whether first response signal detecting after start signal is identical with default normal response signal, and judges that according to the testing result of first response signal after start signal whether SDA link is normal.When SDA link is normal, perform step 306; When SDA link is undesired, perform step 305.
Alternatively, this step 304 can be identical with the step 2022 in embodiment bis-, is not described in detail in this.
Step 305: judgement I2C main frame can not be controlled I2C bus.
Step 306: control master from salve reading out data and to salve data writing, whether normal to detect the read-write capability of I2C main frame.When the read-write capability of I2C main frame is normal, perform step 307; When the read-write capability of I2C main frame is undesired, perform step 305.
Alternatively, this step 306 can be identical with the step 203 in embodiment bis-, is not described in detail in this.
Step 307: judgement I2C main frame can be controlled I2C bus.
Easily know; the progress of can service marking position Flag indicating the self check of I2C main frame; as Flag 000 shows not carry out self check; Flag 001 shows that the self check of SCL link is by (SCL link is normal); Flag 010 shows that the self check of SDA link is by (SDA link is normal); Flag 100 shows that read-write capability self check is by (read-write capability is normal); Flag 111 shows that all self checks are by (link is normal and read-write capability is normal), and Flag 101 shows that self check is by (link is undesired or read-write capability is undesired).
The embodiment of the present invention is by when I2C bus is busy, receive the packet transmitting in I2C bus, and according to the link of this packet detection I2C main frame, control master from salve reading out data and to salve data writing, whether the read-write capability with detection I2C main frame is normal, and then judge that can this I2C main frame control I2C bus, therefore do not need when I2C bus is idle by the time just can carry out the self check of I2C main frame.The embodiment of the present invention can be carried out in real time, avoided in the process of I2C host waits self check, the I2C main frame of the current control I2C bus existing in appearance prior art breaks down, standby I2C main frame can not replace the I2C host computer control I2C bus of current control I2C bus, and causes the problem that the device of I2C bus is changed repeatedly of controlling.And read-write capability two aspects of the link of I2C main frame and I2C main frame are detected simultaneously, improved the accuracy of testing result.In addition, when detecting the link of I2C main frame when undesired, directly judge that I2C main frame can not judge I2C bus, do not need to continue the read-write capability of I2C main frame to detect, saved and detected time and the resource expending.
Embodiment tetra-
The embodiment of the present invention provides a kind of self-checking unit of I2C main frame, has been applicable to detect I2C main frame firm and that I2C bus connects, and referring to Fig. 6, this device comprises:
Whether link detecting module 402, for when I2C bus is busy, receives the packet transmitting in I2C bus, and normal according to the link of this packet detection I2C main frame.
The embodiment of the present invention, by when I2C bus is busy, receives the packet transmitting in I2C bus, and according to this packet, detects the link of I2C main frame, does not therefore need when I2C bus is idle by the time just can carry out the self check of I2C main frame.The embodiment of the present invention can be carried out in real time, avoided in the process of I2C host waits self check, the I2C main frame of the current control I2C bus existing in appearance prior art breaks down, standby I2C main frame can not replace the I2C host computer control I2C bus of current control I2C bus, and causes the problem that the I2C main frame of I2C bus is changed repeatedly of controlling.
Embodiment five
The embodiment of the present invention provides a kind of self-checking unit of I2C main frame, has been applicable to detect I2C main frame firm and that I2C bus connects, and referring to Fig. 7, this device comprises:
Alternatively, bus detection module 501 can comprise:
Whether level detection unit, for detection of there being level to change on scl line within the cycle of a default standard clock signal;
Bus judging unit, when having level to change on scl line within the cycle of a default standard clock signal, judges that I2C bus is busy; While not having level to change, judge that I2C bus is idle within the cycle of a default standard clock signal on scl line.
In actual applications, level detection unit can be clock counter, and bus judging unit can be Controller.
It should be noted that, according to I2C agreement, while carrying out data transmission in I2C bus, be that I2C bus is when busy, the level that there will be height to change on scl line, and cycle of changing of level be the cycle (time interval between two high level is the cycle of default standard clock signal) of default standard clock signal; While not carrying out data transmission in I2C bus, when I2C bus is idle, on scl line, remain high level.Conventionally in each I2C bus, can preset a standard clock signal, each equipment being connected with this I2C bus can get cycle and/or the frequency of the standard clock signal of this I2C bus.Under normal circumstances, the clock signal frequency on scl line is identical with this standard clock signal frequency.
Alternatively, link detecting module 502 can comprise:
Whether identical with default standard clock signal SCL link detecting unit, for receiving the clock signal on scl line, detect this clock signal, to judge that whether SCL link is normal;
SDA link detecting unit, for receiving the response signal of first after start signal on sda line, whether first response signal detecting after start signal is identical with default normal response signal, to judge that whether SDA link is normal;
Judging unit, for when SCL link is normal and SDA link is normal, judges that the link of I2C main frame is normal.
Particularly, SCL link detecting unit can comprise:
Sampling subelement, within the sampling time, usings first signal as with reference to signal, clock signal is sampled, and record the quantity that sampled result is high level, and the frequency of first signal is n times of standard clock signal frequency, and n >=2 and n are integer;
Quantity detection sub-unit, whether identical with predetermined quantity for detection of the high level quantity of record, predetermined quantity is within the sampling time, usings first signal as with reference to signal, to the standard clock signal quantity that the sampled result of acquisition is high level of sample; When the high level quantity of record being detected when identical with predetermined quantity, judge that SCL link is normal; When the high level quantity of record being detected when different from predetermined quantity, judge that SCL link is undesired.
In actual applications, sampling subelement can be clock counter, and quantity detection sub-unit can be Controller.
Particularly, SDA link detecting unit can be for, when first response signal after start signal is low level, judges that SDA link is normal; When first response signal after start signal is high level, judge that SDA link is undesired.
In actual applications, SDA link detecting unit can be Controller.Judge whether the response signal after start signal is low level, can be completed by ACK counter.
It should be noted that, in I2C agreement, stipulate, on sda line, must take byte as unit transmission data, response signal of each byte heel, but the byte quantity of transmission is unrestricted.Default normal response signal is for showing to receive successful response signal.Generally by low level response signal, show to receive successfully.But when I2C main frame reads the data of I2C slave, I2C main frame reads after the data of last byte of I2C slave, sda line can be remained to high level (because sda line and scl line are all connected to power supply by pull-up circuit, therefore only however operate that can to realize response signal be high level), to show to receive successfully, then I2C main frame sends stop signal (when scl line is high level, sda line switches to high level from low level).Except above-mentioned situation, generally, when response signal is high level, show to take defeat.
According to I2C agreement, while starting data transmission in I2C bus, first by I2C main frame, send start signal (when scl line is high level, sda line switches to low level from high level), then I2C main frame can send seven bit address and the data direction position with the I2C slave of this I2C main-machine communication, this seven bit address is the sign of I2C slave, can determine the I2C slave with I2C main-machine communication according to this address.When this I2C slave receives after seven bit address and data direction position of the transmission of I2C main frame, the level on sda line is dragged down, take and realize response signal as low level, show that I2C slave successfully receives seven bit address and data direction position that I2C main frame sends.Then according to data direction position, " 0 " (low level) represents that I2C main frame writes data into I2C slave, " 1 " (high level) represents that I2C main frame reads the data of I2C slave, between I2C main frame and I2C slave, start to take eight bit data as unit transmission data in I2C bus, after every eight bit data is transmitted, have a response signal, response signal is high level, or the side that low level receives data in I2C main frame and I2C slave determines.After data transmission completes, I2C main frame sends stop signal.
No matter the level of data direction position is high level or low level, and I2C main frame sends behind seven bit address and data direction position, if I2C slave successfully receives, is bound to the level on sda line to drag down, and making response signal is low level.In the process of data transmission, if I2C main frame writes I2C slave by data, I2C slave is every successfully to be received after eight bit data, all the level on sda line can be dragged down, and making response signal is low level; If I2C main frame reads the data of I2C slave, I2C main frame is every successfully to be received after eight bit data, generally also the level on sda line can be dragged down, making response signal is low level, only have and receive after last eight bit data when I2C main frame, just can keep sda line is high level, and response signal is high level.
Whether first response signal (showing whether I2C slave receives the response signal of seven bit address and data direction position) that therefore only need to detect after start signal is low level, be whether response signal is identical with normal response signal, can judge that whether SDA link is normal, determination methods is simple and convenient.The reason of selecting first response signal after start signal to judge, the one, the position of response signal is determined according to start signal, select first response signal to judge more convenient, the 2nd, this response signal only need just judge according to level, whether do not need to consider data direction position and be last bit data of data transmission, judgement is got up fairly simple.
Further, SDA link detecting unit can also be for, when data direction position, first response signal after start signal, when second response signal after start signal is low level, or second response signal after data direction position and start signal is high level, first response signal after start signal is low level, when the signal after second response signal after start signal is stop signal, or when data direction position is high level, second response signal after first response signal after start signal and start signal is low level, when the signal after second response signal after start signal is not stop signal, judge that SDA link is normal, otherwise, judge that SDA link is undesired.
Preferably, judging unit can also be for, when SCL link is undesired, judges that the link of I2C main frame is undesired.
In actual applications, judging unit can be Controller.
In a kind of implementation of the present embodiment, this device can also comprise: read-write capability detection module 503, whether for when I2C bus is busy, master is from salve reading out data and to salve data writing in control, normal to detect the read-write capability of I2C main frame.
In actual applications, read-write capability detection module 503 and judge module 504 can be Controller.
Alternatively, read-write capability detection module 503 can comprise:
Read comparing unit, for controlling master, from salve, read preset data, when data that master reads are identical with preset data in master, judge I2C main frame to read function normal; When data that master reads are different from preset data in master, judge I2C main frame to read function undesired;
Write comparing unit, for controlling master, the preset data of master is write to salve, when master writes data in salve when identical with preset data in salve, judge I2C main frame to write function normal, in master, write data in salve when different from preset data in salve, judge I2C main frame to write function undesired.
In actual applications, whether the data that judgement master reads are identical with the preset data in master, can be completed by master, and whether the data that judgement master writes in salve are identical with the preset data in salve, can be completed by salve.
Further, judge module 504 can also be for, when the link of I2C main frame is undesired, judges that I2C main frame can not control I2C bus.
In the another kind of implementation of the present embodiment, this device can also comprise: Host Detection module 505, and for when I2C bus is idle, control I2C bus, and send preset data bag to I2C slave.
Correspondingly, judge module 504 for, when receiving the response signal that I2C slave sends, judge that I2C main frame can control I2C bus.
In actual applications, Host Detection module 505 can be master.
In another implementation of the present embodiment, this device can also comprise isolation module, and for when device is not accessed I2C bus, spacer assembly and I2C bus, can prevent the maloperation of I2C bus.
The embodiment of the present invention is by when I2C bus is busy, receive the packet transmitting in I2C bus, and according to the link of this packet detection I2C main frame, control master from salve reading out data and to salve data writing, whether the read-write capability with detection I2C main frame is normal, and then judge that can this I2C main frame control I2C bus, therefore do not need when I2C bus is idle by the time just can carry out the self check of I2C main frame.The embodiment of the present invention can be carried out in real time, avoided in the process of I2C host waits self check, the I2C main frame of the current control I2C bus existing in appearance prior art breaks down, standby I2C main frame can not replace the I2C host computer control I2C bus of current control I2C bus, and causes the problem that the device of I2C bus is changed repeatedly of controlling.And read-write capability two aspects of the link of I2C main frame and I2C main frame are detected simultaneously, improved the accuracy of testing result.
Embodiment six
The embodiment of the present invention provides a kind of I2C main frame, and referring to Fig. 8, this I2C main frame 60 generally comprises the parts such as bus interface 61, storer 62 and processor 63.Bus interface 61 comprises the link of I2C main frame, for receiving the packet transmitting in I2C bus or sending packet to I2C bus.This I2C main frame also comprises clock counter 64 and ACK counter 65.Clock counter 64 is for realizing the counting of clock signal on scl line, and ACK counter 65 is for realizing the counting of low level response signal on sda line.It will be understood by those skilled in the art that the structure shown in Fig. 8 does not form the restriction to this I2C main frame 60, this I2C main frame 60 can comprise the parts more more or less than diagram, or combines some parts, or different parts are arranged.
Below in conjunction with Fig. 8, each component parts of I2C main frame 60 is carried out to concrete introduction:
Whether busy program in processor 63 run memories 62, can be used for detecting I2C bus.
Whether particularly, clock counter 64 can be used for, detect on scl line and within the cycle of a default standard clock signal, have level to change.
Correspondingly, processor 63 can be realized, and while having level to change on scl line within the cycle of a default standard clock signal, judges that I2C bus is busy; While not having level to change, judge that I2C bus is idle within the cycle of a default standard clock signal on scl line.
It should be noted that, according to I2C agreement, while carrying out data transmission in I2C bus, be that I2C bus is when busy, the level that there will be height to change on scl line, and cycle of changing of level be the cycle (time interval between two high level is the cycle of default standard clock signal) of default standard clock signal; While not carrying out data transmission in I2C bus, when I2C bus is idle, on scl line, remain high level.Conventionally in each I2C bus, can preset a standard clock signal, each equipment being connected with this I2C bus can get cycle and/or the frequency of the standard clock signal of this I2C bus.Under normal circumstances, the clock signal frequency on scl line is identical with this standard clock signal frequency.
Further, bus interface 61 can be used for, and when I2C bus is busy, receives the packet transmitting in I2C bus.
Correspondingly, processor 63 can be realized, and whether the link that detects I2C main frame according to the packet transmitting in I2C bus is normal.
Particularly, bus interface 61 can be used for, first response signal on the clock signal on reception scl line, sda line after start signal.
Correspondingly, processor 63 can be realized, and whether identically with default standard clock signal detects clock signal, to judge that whether SCL link is normal; Whether first response signal detecting after start signal is identical with default normal response signal, to judge that whether SDA link is normal; When SCL link is normal and SDA link is normal, judge that the link of I2C main frame is normal.
More specifically, clock counter 64 can be used for, within the sampling time, using first signal as with reference to signal, clock signal is sampled, and record the quantity that sampled result is high level, the frequency of first signal is n times of standard clock signal frequency, and n >=2 and n are integer.
Correspondingly, processor 63 can be realized, and whether the high level quantity of detection record is identical with predetermined quantity, and predetermined quantity is within the sampling time, using first signal as with reference to signal, to the standard clock signal quantity that the sampled result that obtains is high level of sampling; When the high level quantity of record being detected when identical with predetermined quantity, judge that SCL link is normal; When the high level quantity of record being detected when different from predetermined quantity, judge that SCL link is undesired.
More specifically, processor 63 can be realized, and when first response signal after start signal is low level, judges that SDA link is normal; When first response signal after start signal is high level, judge that SDA link is undesired.
In actual applications, judge whether the response signal after start signal is low level, can be completed by ACK counter 65.
It should be noted that, in I2C agreement, stipulate, on sda line, must take byte as unit transmission data, response signal of each byte heel, but the byte quantity of transmission is unrestricted.Default normal response signal is for showing to receive successful response signal.Generally by low level response signal, show to receive successfully.But when I2C main frame reads the data of I2C slave, I2C main frame reads after the data of last byte of I2C slave, sda line can be remained to high level (because sda line and scl line are all connected to power supply by pull-up circuit, therefore only however operate that can to realize response signal be high level), to show to receive successfully, then I2C main frame sends stop signal (when scl line is high level, sda line switches to high level from low level).Except above-mentioned situation, generally, when response signal is high level, show to take defeat.
According to I2C agreement, while starting data transmission in I2C bus, first by I2C main frame, send start signal (when scl line is high level, sda line switches to low level from high level), then I2C main frame can send seven bit address and the data direction position with the I2C slave of this I2C main-machine communication, this seven bit address is the sign of I2C slave, can determine the I2C slave with I2C main-machine communication according to this address.When this I2C slave receives after seven bit address and data direction position of the transmission of I2C main frame, the level on sda line is dragged down, take and realize response signal as low level, show that I2C slave successfully receives seven bit address and data direction position that I2C main frame sends.Then according to data direction position, " 0 " (low level) represents that I2C main frame writes data into I2C slave, " 1 " (high level) represents that I2C main frame reads the data of I2C slave, between I2C main frame and I2C slave, start to take eight bit data as unit transmission data in I2C bus, after every eight bit data is transmitted, have a response signal, response signal is high level, or the side that low level receives data in I2C main frame and I2C slave determines.After data transmission completes, I2C main frame sends stop signal.
No matter the level of data direction position is high level or low level, and I2C main frame sends behind seven bit address and data direction position, if I2C slave successfully receives, is bound to the level on sda line to drag down, and making response signal is low level.In the process of data transmission, if I2C main frame writes I2C slave by data, I2C slave is every successfully to be received after eight bit data, all the level on sda line can be dragged down, and making response signal is low level; If I2C main frame reads the data of I2C slave, I2C main frame is every successfully to be received after eight bit data, generally also the level on sda line can be dragged down, making response signal is low level, only have and receive after last eight bit data when I2C main frame, just can keep sda line is high level, and response signal is high level.
Whether first response signal (showing whether I2C slave receives the response signal of seven bit address and data direction position) that therefore only need to detect after start signal is low level, be whether response signal is identical with normal response signal, can judge that whether SDA link is normal, determination methods is simple and convenient.The reason of selecting first response signal after start signal to judge, the one, the position of response signal is determined according to start signal, select first response signal to judge more convenient, the 2nd, this response signal only need just judge according to level, whether do not need to consider data direction position and be last bit data of data transmission, judgement is got up fairly simple.
Further, bus interface 61 can be used for, the data direction position on reception sda line and second response signal after start signal.
Correspondingly, processor 63 can be realized, when data direction position, first response signal after start signal, when second response signal after start signal is low level, or second response signal after data direction position and start signal is high level, first response signal after start signal is low level, when the signal after second response signal after start signal is stop signal, or when data direction position is high level, first response signal after start signal and first response signal after start signal are low level, when the signal after second response signal after start signal is not stop signal, judge that SDA link is normal, otherwise, judge that SDA link is undesired.To prevent that first response signal after start signal from being that maloperation due to I2C bus becomes low level signal, by what may abnormal SDA link be mistaken for, improved the reliability detecting, reduced risk.
Preferably, processor 63 can also be realized, and when SCL link is undesired, judges that the link of I2C main frame is undesired.
In a kind of implementation of the present embodiment, I2C main frame comprises a plurality of storeies 62, wherein, has at least a storer 62 to belong to master, has at least a storer 62 to belong to salve.Master also comprises at least one processor, for realizing, from slave, read preset data, with judge I2C main frame whether read function normal, to slave, write preset data, so that slave judge I2C main frame whether write function normal, salve also comprises the device (Fig. 8 is not shown) for comparing data, as comparer, processor etc.
Whether processor 63 can be realized, and when I2C bus being detected when busy, controls master from salve reading out data and to salve data writing, normal to detect the read-write capability of I2C main frame; When read-write capability normal when the link of I2C main frame and I2C main frame is normal, judge that I2C main frame can control I2C bus.
Particularly, processor 63 can be realized, control master and from salve, read preset data, when data that master reads are identical with preset data in master, judge I2C main frame to read function normal, when data that master reads are different from preset data in master, judge I2C main frame to read function undesired; Control master the preset data in master is write to salve, when master writes data in salve when identical with preset data in salve, judge I2C main frame to write function normal, when master writes data in salve when different from preset data in salve, judge I2C main frame to write function undesired.
Preferably, processor 63 can also be realized, and when the link of I2C main frame is undesired, judges that I2C main frame can not control I2C bus.
In the another kind of implementation of the present embodiment, processor 63 can also be realized, and when I2C bus is idle, controls I2C bus, and sends preset data bag to I2C slave.
Correspondingly, processor 63 can be realized, and when receiving the response signal of I2C slave transmission, judgement I2C main frame can be controlled I2C bus.
The embodiment of the present invention is by when I2C bus is busy, receive the packet transmitting in I2C bus, and according to the link of this packet detection I2C main frame, control master from salve reading out data and to salve data writing, whether the read-write capability with detection I2C main frame is normal, and then judge that can this I2C main frame control I2C bus, therefore do not need when I2C bus is idle by the time just can carry out the self check of I2C main frame.The embodiment of the present invention can be carried out in real time, avoided in the process of I2C host waits self check, the I2C main frame of the current control I2C bus existing in appearance prior art breaks down, standby I2C main frame can not replace the I2C host computer control I2C bus of current control I2C bus, and causes the problem that the device of I2C bus is changed repeatedly of controlling.And read-write capability two aspects of the link of I2C main frame and I2C main frame are detected simultaneously, improved the accuracy of testing result.
It should be noted that: the self-checking unit of the I2C main frame that above-described embodiment provides is when the self check of I2C main frame, only the division with above-mentioned each functional module is illustrated, in practical application, can above-mentioned functions be distributed and by different functional modules, completed as required, the inner structure that is about to device is divided into different functional modules, to complete all or part of function described above.In addition, the self checking method of the I2C main frame that above-described embodiment provides and the self-checking unit embodiment of I2C main frame belong to same design, and its specific implementation process refers to embodiment of the method, repeats no more here.
The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.
One of ordinary skill in the art will appreciate that all or part of step that realizes above-described embodiment can complete by hardware, also can come the hardware that instruction is relevant to complete by program, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium of mentioning can be ROM (read-only memory), disk or CD etc.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (17)
1. a self checking method for internal integrated circuit I2C main frame, described I2C main frame is connected with I2C bus by the link of described I2C main frame, it is characterized in that, and described method comprises:
Whether I2C Host Detection I2C bus is busy;
When described I2C bus is busy, receive the packet transmitting in described I2C bus, and whether according to described packet, detect the link of described I2C main frame normal.
2. method according to claim 1, is characterized in that, described I2C main frame comprises main equipment and from equipment, described main equipment is connected with described I2C bus by the link of described I2C main frame, describedly from equipment, is connected with described main equipment, and described method also comprises:
When described I2C bus is busy, control described main equipment from described from equipment reading out data and to described from equipment data writing, whether normal to detect the read-write capability of described I2C main frame;
When the link read-write capability normal and described I2C main frame of described I2C main frame is normal, judge that described I2C main frame can control described I2C bus.
3. whether method according to claim 2, is characterized in that, the described main equipment of described control is from described from equipment read data and to described from equipment data writing, normal to detect the read-write capability of described I2C main frame, comprising:
Control described main equipment from the described preset data that reads from equipment, when data that described main equipment reads are identical with preset data in described main equipment, judge described I2C main frame to read function normal, when data that described main equipment reads are different from preset data in described main equipment, judge described I2C main frame to read function undesired;
Controlling described main equipment writes the preset data in described main equipment described from equipment, when described in described main equipment writes, the data from equipment are identical with described preset data from equipment, judge described I2C main frame to write function normal, when described main equipment writes described data from equipment when different from described preset data from equipment, judge described I2C main frame to write function undesired.
4. according to the method described in claim 1-3 any one, it is characterized in that, described I2C bus comprises serial time clock line and serial data line, the link of described I2C main frame comprises serial clock link and serial data link, the packet transmitting in the described I2C bus of described reception, and whether normal, comprising if according to described packet, detecting the link of described I2C main frame:
Receive the clock signal on described serial time clock line, whether identically with default standard clock signal detect described clock signal, whether normal to judge described serial clock link;
Receive first response signal after start signal on described serial data line, whether first response signal detecting after described start signal is identical with default normal response signal, to judge that whether described serial data link is normal;
When described serial clock link is normal and described serial data link is normal, judge that the link of described I2C main frame is normal.
5. whether method according to claim 4, is characterized in that, whether the described clock signal of described detection is identical with default standard clock signal, normal to judge described serial clock link, comprising:
Within the sampling time, using first signal as with reference to signal, described clock signal to be sampled, and record the quantity that sampled result is high level, the frequency of described first signal is n times of described standard clock signal frequency, n >=2 and n are integer;
Whether the high level quantity of detection record is identical with predetermined quantity, and described predetermined quantity is within the described sampling time, usings described first signal as with reference to signal, to the described standard clock signal quantity that the sampled result that obtains is high level of sampling;
When the high level quantity of described record being detected when identical with described predetermined quantity, judge that described serial clock link is normal;
When the high level quantity of described record being detected when different from described predetermined quantity, judge that described serial clock link is undesired.
6. method according to claim 4, is characterized in that, whether first response signal after the described start signal of described detection is identical with default normal response signal, to judge that whether described serial data link is normal, comprising:
When first response signal after described start signal is low level, judge that described serial data link is normal;
When first response signal after described start signal is high level, judge that described serial data link is undesired.
7. method according to claim 6, is characterized in that, whether first response signal after the described start signal of described detection is identical with default normal response signal, to judge that whether described serial data link is normal, also comprises:
When second response signal after first response signal after described data direction position, described start signal, described start signal is low level, or,
It is signal after second response signal after low level, described start signal while being stop signal that second response signal after described data direction position and described start signal is first response signal after high level, described start signal, or,
When second response signal after first response signal after described data direction position is high level, described start signal and described start signal is signal after second response signal after low level, described start signal and is not stop signal, judge that described serial data link is normal;
Otherwise, judge that described serial data link is undesired.
8. according to the method described in claim 1-3 any one, it is characterized in that, described method also comprises:
When described I2C bus is idle, controls described I2C bus, and send preset data bag to I2C slave;
When receiving the response signal that described I2C slave sends, judge that described I2C main frame can control described I2C bus.
9. a self-checking unit for internal integrated circuit I2C main frame, described I2C main frame is connected with I2C bus by the link of described I2C main frame, it is characterized in that, and described device comprises:
Bus detection module, whether busy for detection of I2C bus;
Link detecting module, for when described I2C bus is busy, receives the packet transmitting in described I2C bus, and whether according to described packet, detect the link of described I2C main frame normal.
10. device according to claim 9, it is characterized in that, described I2C main frame comprises main equipment and from equipment, described main equipment is connected with described I2C bus by the link of described I2C main frame, describedly from equipment, be connected with described main equipment, described device also comprises:
Whether read-write capability detection module, for when described I2C bus is busy, controls described main equipment from described from equipment reading out data and to described from equipment data writing, normal to detect the read-write capability of described I2C main frame;
Judge module, when read-write capability normal for the link when described I2C main frame and described I2C main frame is normal, judges that described I2C main frame can control described I2C bus.
11. devices according to claim 10, is characterized in that, described read-write capability detection module comprises:
Read comparing unit, be used for controlling described main equipment and from equipment, read preset data from described, when data that described main equipment reads are identical with preset data in described main equipment, judge described I2C main frame to read function normal, when data that described main equipment reads are different from preset data in described main equipment, judge described I2C main frame to read function undesired;
Write comparing unit, for controlling described main equipment, the preset data of described main equipment is write described from equipment, when described in described main equipment writes, the data from equipment are identical with described preset data from equipment, judge described I2C main frame to write function normal, when described main equipment writes described data from equipment when different from described preset data from equipment, judge described I2C main frame to write function undesired.
12. according to the device described in claim 9-11 any one, it is characterized in that, described I2C bus comprises serial time clock line and serial data line, and the link of described I2C main frame comprises serial clock link and serial data link, and described link detecting module comprises:
Whether whether identical with default standard clock signal serial clock link detecting unit, for receiving the clock signal on described serial time clock line, detect described clock signal, normal to judge described serial clock link;
Serial data link detecting unit, for receiving first response signal after start signal on described serial data line, whether first response signal detecting after described start signal is identical with default normal response signal, to judge that whether described serial data link is normal;
Judging unit, for when described serial clock link is normal and described serial data link is normal, judges that the link of described I2C main frame is normal.
13. devices according to claim 12, is characterized in that, described serial clock link detecting unit comprises:
Sampling subelement, within the sampling time, usings first signal as with reference to signal, described clock signal is sampled, and record the quantity that sampled result is high level, and the frequency of described first signal is n times of described standard clock signal frequency, n >=2 and n are integer;
Quantity detection sub-unit, whether the high level quantity for detection of record is identical with predetermined quantity, described predetermined quantity is within the described sampling time, usings described first signal as with reference to signal, to the described standard clock signal quantity that the sampled result that obtains is high level of sampling; When the high level quantity of described record being detected when identical with described predetermined quantity, judge that described serial clock link is normal; When the high level quantity of described record being detected when different from described predetermined quantity, judge that described serial clock link is undesired.
14. devices according to claim 12, is characterized in that, described serial data link detecting unit is used for,
When first response signal after described start signal is low level, judge that described serial data link is normal;
When first response signal after described start signal is high level, judge that described serial data link is undesired.
15. devices according to claim 14, is characterized in that, described serial data link detecting unit also for,
When second response signal after first response signal after described data direction position, described start signal, described start signal is low level, or,
It is signal after second response signal after low level, described start signal while being stop signal that second response signal after described data direction position and described start signal is first response signal after high level, described start signal, or,
When second response signal after first response signal after described data direction position is high level, described start signal and described start signal is signal after second response signal after low level, described start signal and is not stop signal, judge that described serial data link is normal;
Otherwise, judge that described serial data link is undesired.
16. according to the device described in claim 9-11 any one, it is characterized in that, described device also comprises:
Host Detection module, when idle for described I2C bus, controls I2C bus, and sends preset data bag to I2C slave;
Judge module, for when receiving the response signal that described I2C slave sends, judges that described I2C main frame can control described I2C bus.
17. 1 kinds of internal integrated circuit I2C main frames, is characterized in that, described main frame comprises bus interface and processor, and described processor is for executing claims the self checking method of the I2C main frame described in 1-8 any one.
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