CN103515297B - A kind of manufacture method of semiconductor device - Google Patents

A kind of manufacture method of semiconductor device Download PDF

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Publication number
CN103515297B
CN103515297B CN201210219550.3A CN201210219550A CN103515297B CN 103515297 B CN103515297 B CN 103515297B CN 201210219550 A CN201210219550 A CN 201210219550A CN 103515297 B CN103515297 B CN 103515297B
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layer
copper
silicon material
doping carbon
connection metal
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CN103515297A (en
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张海洋
张城龙
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided; Form the silicon material layer of an etching stopping layer, an interlayer dielectric layer and one first doping carbon on the semiconductor substrate successively; Form groove and the through hole for filling copper-connection metal; One first barrier layer is formed at the sidewall of described groove and through hole and bottom; Form a copper-connection metal level, to fill up described groove and through hole; Grind described copper-connection metal level, to expose the silicon material layer of described first doping carbon; Described copper-connection metal level is formed a CuSiN layer; Form the silicon material layer of one second doping carbon, to cover the silicon material layer of described CuSiN layer and described first doping carbon.According to the present invention, the diffusion effect of copper-connection metal more reliably can be stoped.

Description

A kind of manufacture method of semiconductor device
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of formation method of copper-connection metal diffusion barrier layer.
Background technology
When the manufacturing process node of CMOS reaches 45nm and be following, low k/ ultra low k material is used to form interlayer dielectric layer to reduce RC delay at wiring stage.Form copper metal interconnecting wires in described interlayer dielectric layer before, need on described interlayer dielectric layer, to form Ta/TaN barrier layer to prevent the diffusion in interlayer dielectric layer described in the metal interconnected alignment of copper.But, described Ta/TaN barrier layer can only stop the diffusion in the downward layer interlayer dielectric layer of copper metal interconnecting wires, therefore, also need to form barrier layer with the silicon of the silicon of doping carbon or doping carbon and nitrogen on described copper metal interconnecting wires and prevent the diffusion of copper metal interconnecting wires upwards in layer interlayer dielectric layer.
Using after dual damascene process forms through hole for filling copper-connection metal and groove in described interlayer dielectric layer, deposit described Ta/TaN barrier layer, copper-connection metal respectively successively; Then, described copper-connection metal level is ground to expose described interlayer dielectric layer.Because the mechanical strength of the described interlayer dielectric layer of low k/ ultra low k material formation is very poor, in the process of above-mentioned grinding, described interlayer dielectric layer can by destruction to a certain extent.Meanwhile, because described Ta/TaN barrier layer can not stop the diffusion of copper-connection metal upwards in layer interlayer dielectric layer, its reliability remains to be further improved.
Therefore, need to propose a kind of method, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided; Form the silicon material layer of an etching stopping layer, an interlayer dielectric layer and one first doping carbon on the semiconductor substrate successively; Form groove and the through hole for filling copper-connection metal; One first barrier layer is formed at the sidewall of described groove and through hole and bottom; Form a copper-connection metal level, to fill up described groove and through hole; Grind described copper-connection metal level, to expose the silicon material layer of described first doping carbon; Described copper-connection metal level is formed a CuSiN layer; Form the silicon material layer of one second doping carbon, to cover the silicon material layer of described CuSiN layer and described first doping carbon.
Further, chemical vapor deposition method is adopted to form the silicon material layer of described etching stopping layer, described interlayer dielectric layer and described first doping carbon.
Further, the material of described etching stopping layer is SiCN or SiC.
Further, the constituent material of described interlayer dielectric layer is the material with low k/ ultra low k.
Further, the silicon material layer of described first doping carbon is SiC layer.
Further, dual damascene process is adopted to form described groove and through hole.
Further, the order of described dual damascene process forms groove after first forming through hole.
Further, described dual damascene process is integrated etch process.
Further, described one etch process comprises the steps: to form a passivation layer and a metal hard mask layer successively on the silicon material layer of described first doping carbon; Described metal hard mask layer is formed the figure for etching described through hole; The metal hard mask layer of described patterning forms an interlayer dielectric layer again; This layer of interlayer dielectric layer forms photoresist, and on described photoresist, forms the figure for etching described groove; Perform a plasma dry etch process, to form described groove and through hole.
Further, the constituent material of described passivation layer is TEOS.
Further, the constituent material of described metal hard mask layer is TiN or BN.
Further, argon ion sputtering technique is adopted to remove the etching stopping layer being positioned at described via bottoms.
Further, physical gas-phase deposition is adopted to form described first barrier layer.
Further, described first barrier layer is made up of the metal Ta layer stacked gradually from bottom to top and alloy CuMn layer.
Further, electroplating technology is adopted to form described copper-connection metal level.
Further, after described grinding terminates, the thickness of the silicon material layer of residual described first doping carbon is 100-200 dust.
Further, the step forming described CuSiN layer comprises: use SiH 4and NH 3semiconductor substrate described in the mist process formed; Use NH again 3plasma does further process to the described CuSiN layer formed.
Further, chemical vapor deposition method is adopted to form the silicon material layer of described second doping carbon.
Further, described depositing operation carries out under the condition of 400 DEG C.
Further, in the silicon that uses of described depositing operation and carbon-source gas containing the oxygen of 5%.
Further, described first oxidized formation one second barrier layer, barrier layer of part.
According to the present invention, the diffusion effect of copper-connection metal more reliably can be stoped.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 G is the schematic cross sectional view of each step of the formation method of the copper-connection metal diffusion barrier layer that the present invention proposes;
Fig. 2 is the flow chart of the formation method of the copper-connection metal diffusion barrier layer that the present invention proposes.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the formation method of the copper-connection metal diffusion barrier layer that the present invention proposes.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Below, the detailed step of the formation method of the copper-connection metal diffusion barrier layer that the present invention proposes is described with reference to Figure 1A-Fig. 1 G and Fig. 2.
With reference to Figure 1A-Fig. 1 G, illustrated therein is the schematic cross sectional view of each step of the formation method of the copper-connection metal diffusion barrier layer that the present invention proposes.
First, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) etc. doped with impurity.Exemplarily, in the present embodiment, Semiconductor substrate 100 selects single crystal silicon material to form.In Semiconductor substrate 100, be formed with isolation structure, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Semiconductor substrate 100 is divided into nmos area and PMOS district by isolation structure.Various trap (well) structure is also formed in described Semiconductor substrate 100.
Described Semiconductor substrate 100 is formed with active device layer.Described active device layer comprises grid structure, and as an example, described grid structure can comprise the gate dielectric, gate material layers and the grid hard masking layer that stack gradually from bottom to top.In described Semiconductor substrate 100, the both sides be positioned at immediately below described grid structure are formed with source/drain region, are channel region between source/drain region; Described grid structure and source/drain region are formed with self-aligned silicide.In order to simplify, described Semiconductor substrate 100 is only shown in diagram.
Next, chemical vapor deposition method is adopted in described Semiconductor substrate 100, to form an etching stopping layer 101, preferred SiCN or SiC of material of described etching stopping layer 101.Damage to described active device layer when described etching stopping layer 101 can prevent subsequent etch for filling groove and the through hole of copper-connection metal.
Then, adopt chemical vapor deposition method to form an interlayer dielectric layer 102 on described etching stopping layer 101, the constituent material of described interlayer dielectric layer is the material with low k/ ultra low k.This material with low k/ ultra low k can be selected from the common various low k-value dielectric materials in this area, include but not limited to that k value is the silicate compound (HydrogenSilsesquioxane of 2.5-2.9, referred to as HSQ), k value be 2.2 methane-siliconic acid salt compound (MethylSilsesquioxane, be called for short MSQ), k value be the HOSP of 2.8 tM(advanced low-k materials of the mixture based on organic substance and Si oxide that Honeywell company manufactures) and k value are the SiLK of 2.65 tM(a kind of advanced low-k materials that DowChemical company manufactures) etc.
Next, chemical vapor deposition method is adopted on described interlayer dielectric layer 102, to form the silicon material layer 103 of one first doping carbon, such as SiC layer.The effect of the silicon material layer 103 of described first doping carbon causes damage to described interlayer dielectric layer 102 when being the copper metal interconnecting layer preventing follow-up grinding from being formed.
Then, as shown in Figure 1B, groove 104 and the through hole 105 of dual damascene process formation for filling copper-connection metal is adopted.Described dual damascene process forms the process sequence of groove after can selecting first to form through hole, also can select one etch process.Described one etch process comprises the steps: to be formed successively a passivation layer and a metal hard mask layer on the silicon material layer 103 of described first doping carbon (for simplicity, not shown), the constituent material of described passivation layer can be chosen as TEOS, composition is silicon dioxide mainly, is with Si (OC 2h 5) 4for primary raw material reaction generate, the constituent material of described metal hard mask layer can be chosen as TiN or BN; Described metal hard mask layer is formed the figure for etching described through hole; The metal hard mask layer of described patterning forms an interlayer dielectric layer again; This layer of interlayer dielectric layer forms photoresist, and on described photoresist, forms the figure for etching described groove; Perform a plasma dry etch process, to form described groove and through hole.
Above-mentioned etching process ends at described etching stopping layer 101.Next, argon ion sputtering technique is adopted to remove the etching stopping layer 101 being positioned at described via bottoms, to realize the connection with described active device layer.
Then, as shown in Figure 1 C, form one first barrier layer 106 at the sidewall of described groove 104 and through hole 105 and bottom, described first barrier layer 106 is made up of the metal Ta layer stacked gradually from bottom to top and alloy CuMn layer.Physical gas-phase deposition is adopted to form described first barrier layer 106.
Described metal Ta layer plays the effect of the diffusion effect of the copper-connection metal preventing follow-up formation.Cu in described alloy CuMn layer can play the effect of Cu Seed Layer, and the Mn in described alloy CuMn layer can as the raw material sources on follow-up formation second barrier layer.
Then, as shown in figure ip, adopt electroplating technology (ECP) to form a copper-connection metal level 107, described copper-connection metal level 107 fills up described groove 104 and through hole 105.
Then, as referring to figure 1e, adopt chemical mechanical milling tech to grind described copper-connection metal level 107, to expose the silicon material layer 103 of described first doping carbon, and continue to perform described process of lapping until the thickness of silicon material layer 103 of residual described first doping carbon is 100-200 dust.
Then, as shown in fig. 1f, described copper-connection metal level 107 forms a CuSiN layer 108.The step forming described CuSiN layer 108 comprises: use SiH 4and NH 3semiconductor substrate 100 described in the mist process formed, described SiH 4and NH 3there is thermal chemical reaction with the Cu in described alloy CuMn layer, form described CuSiN layer at the top of described copper-connection metal level 107; Use NH again 3plasma does further process to described CuSiN layer, makes the structure of described CuSiN layer more stable.Tack between alloy CuMn layer in described CuSiN layer and described first barrier layer 106 combines and can to strengthen with described interlayer dielectric layer 102.
Then, as shown in Figure 1 G, under the condition of 400 DEG C, chemical vapor deposition method is adopted to form the silicon material layer 109 of one second doping carbon, to cover the silicon material layer 103 of described CuSiN layer 108 and the first doping carbon.Containing the oxygen of 5% in the silicon that described depositing operation uses and carbon-source gas, described oxygen makes the Mn in the alloy CuMn layer in described first barrier layer 106 be converted into Mn oxide, thus the interface of the interface of metal Ta layer in described copper-connection metal level 107 and described first barrier layer 106 and the silicon material layer 109 of described second doping carbon and described copper-connection metal level 107 forms the second barrier layer 110.Simultaneously, in above-mentioned deposition process, described CuSiN layer 108 is polymerized the Mn in described alloy CuMn layer, thus forms a composite barrier on described copper-connection metal level 107, and described composite barrier is made up of Mn oxide, Mn silicide, MnSiN and CuSiN.
So far, whole processing steps that the method according to an exemplary embodiment of the present invention that completes is implemented, next, can be completed the making of whole semiconductor device by subsequent technique, described subsequent technique is identical with traditional process for fabricating semiconductor device.According to the present invention, closed barrier layer can be formed in the surrounding of copper-connection metal level, in a preferred embodiment of the invention, described closed barrier layer is made up of the Mn oxide skin(coating) in the metal Ta layer in described first barrier layer 106, described second barrier layer 110 and described composite barrier, thus more reliably can stop the copper ion drift that the self-diffusion of copper-connection metallic surface, room diffusion and electricity and thermal stress cause.
With reference to Fig. 2, illustrated therein is the flow chart of the formation method of the copper-connection metal diffusion barrier layer that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.
In step 201, Semiconductor substrate is provided;
In step 202., the silicon material layer of an etching stopping layer, an interlayer dielectric layer and one first doping carbon is formed on the semiconductor substrate successively;
In step 203, the groove for filling copper-connection metal and through hole is formed;
In step 204, one first barrier layer is formed at the sidewall of described groove and through hole and bottom;
In step 205, form a copper-connection metal level, to fill up described groove and through hole;
In step 206, grind described copper-connection metal level, to expose the silicon material layer of described first doping carbon;
In step 207, described copper-connection metal level forms a CuSiN layer;
In a step 208, the silicon material layer of one second doping carbon is formed, to cover the silicon material layer of described CuSiN layer and described first doping carbon.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.

Claims (20)

1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided;
Form the silicon material layer of an etching stopping layer, an interlayer dielectric layer and one first doping carbon on the semiconductor substrate successively;
Form groove and the through hole for filling copper-connection metal;
Form one first barrier layer at the sidewall of described groove and through hole and bottom, described first barrier layer is made up of the metal Ta layer stacked gradually from bottom to top and alloy CuMn layer;
Form a copper-connection metal level, to fill up described groove and through hole;
Grind described copper-connection metal level, to expose the silicon material layer of described first doping carbon;
Described copper-connection metal level is formed a CuSiN layer;
Form the silicon material layer of one second doping carbon, to cover the silicon material layer of described CuSiN layer and described first doping carbon, in the process of silicon material layer forming described second doping carbon, Mn in alloy CuMn layer described in described CuSiN layers of polymer, thus on described copper-connection metal level, form the composite barrier be made up of Mn oxide, Mn silicide, MnSiN and CuSiN.
2. method according to claim 1, is characterized in that, adopts chemical vapor deposition method to form the silicon material layer of described etching stopping layer, described interlayer dielectric layer and described first doping carbon.
3. method according to claim 1, is characterized in that, the material of described etching stopping layer is SiCN or SiC.
4. method according to claim 1, is characterized in that, the constituent material of described interlayer dielectric layer is the material with low k/ ultra low k.
5. method according to claim 1, is characterized in that, the silicon material layer of described first doping carbon is SiC layer.
6. method according to claim 1, is characterized in that, adopts dual damascene process to form described groove and through hole.
7. method according to claim 6, is characterized in that, the order of described dual damascene process forms groove after first forming through hole.
8. method according to claim 6, is characterized in that, described dual damascene process is integrated etch process.
9. method according to claim 8, is characterized in that, described one etch process comprises the steps: to form a passivation layer and a metal hard mask layer successively on the silicon material layer of described first doping carbon; Described metal hard mask layer is formed the figure for etching described through hole; The metal hard mask layer of described patterning forms an interlayer dielectric layer again; This interlayer dielectric layer forms photoresist, and on described photoresist, forms the figure for etching described groove; Perform a plasma dry etch process, to form described groove and through hole.
10. method according to claim 9, is characterized in that, the constituent material of described passivation layer is TEOS.
11. methods according to claim 9, is characterized in that, the constituent material of described metal hard mask layer is TiN or BN.
12. methods according to claim 6, is characterized in that, adopt argon ion sputtering technique to remove the etching stopping layer being positioned at described via bottoms.
13. methods according to claim 1, is characterized in that, adopt physical gas-phase deposition to form described first barrier layer.
14. methods according to claim 1, is characterized in that, adopt electroplating technology to form described copper-connection metal level.
15. methods according to claim 1, is characterized in that, after described grinding terminates, the thickness of the silicon material layer of residual described first doping carbon is 100-200 dust.
16. methods according to claim 1, is characterized in that, the step forming described CuSiN layer comprises: use SiH 4and NH 3semiconductor substrate described in the mist process formed; Use NH again 3plasma does further process to the described CuSiN layer formed.
17. methods according to claim 1, is characterized in that, adopt chemical vapor deposition method to form the silicon material layer of described second doping carbon.
18. methods according to claim 17, is characterized in that, described depositing operation carries out under the condition of 400 DEG C.
19. methods according to claim 17, is characterized in that, containing the oxygen of 5% in the silicon that described depositing operation uses and carbon-source gas.
20. methods according to claim 19, is characterized in that, described first oxidized formation one second barrier layer, barrier layer of part.
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CN105789439B (en) * 2016-04-22 2019-05-03 中国科学院微电子研究所 Preparation method of Cu-based resistive random access memory and memory
CN109545745A (en) * 2017-09-21 2019-03-29 上海磁宇信息科技有限公司 A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line
CN112151504B (en) * 2020-08-17 2022-04-29 复旦大学 Copper interconnection structure with hole sealing layer and preparation method thereof
CN113948618B (en) * 2021-12-22 2022-04-22 南昌凯捷半导体科技有限公司 Mini/micro LED chip applying Damascus process and manufacturing method thereof

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CN101569003A (en) * 2006-12-22 2009-10-28 日本电气株式会社 Semiconductor device and method for manufacturing the same

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CN101569003A (en) * 2006-12-22 2009-10-28 日本电气株式会社 Semiconductor device and method for manufacturing the same

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