CN103508410A - Method for manufacturing a component having an electrical through-connection - Google Patents

Method for manufacturing a component having an electrical through-connection Download PDF

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Publication number
CN103508410A
CN103508410A CN201310251111.5A CN201310251111A CN103508410A CN 103508410 A CN103508410 A CN 103508410A CN 201310251111 A CN201310251111 A CN 201310251111A CN 103508410 A CN103508410 A CN 103508410A
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Prior art keywords
semiconductor substrate
hole
front side
contact
dorsal part
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CN201310251111.5A
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CN103508410B (en
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J·莱茵穆特
J·弗莱
Y·贝格曼
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Robert Bosch GmbH
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Robert Bosch GmbH
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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    • B81—MICROSTRUCTURAL TECHNOLOGY
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    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for manufacturing a component (300) having an electrical through-connection (110) is described. The method includes the following steps: providing a semiconductor substrate (100) having a front side (101) and a back side (102) opposite from the front side (101), producing an insulating trench (121), which annularly surrounds a contact area (103), on the front side (101) of the semiconductor substrate (100), filling the insulating trench (121) with an insulating material (122), producing an electrical contact structure (130) on the front side (101) of the semiconductor substrate (100) by depositing an electrically conductive material in the contact area (103), removing the semiconductor material (104) remaining in the contact area (103) on the back side (102) of the semiconductor substrate (100) in order to produce a contact hole (111) which opens up the bottom side of the contact structure (103), and depositing a metallic material (114) in the contact hole (111) in order to electrically connect the electrical contact structure (130) to the back side (102) of the semiconductor substrate (100).

Description

For the manufacture of the method with the member of electric plating through hole
Technical field
The present invention relates to a kind of method for the manufacture of thering is the member of electric plating through hole, especially micro-mechanical component.
Background technology
Extend through the electric contact structure of Semiconductor substrate for microelectromechaniccomponents components (MEMS, micro-electro-mechanical system: MEMS).Therefore, for example use this break-through contact site (Durchkontakt), plating through hole (Durchkontaktierung), the VIA(vertical interconnect access of being called again: perpendicular interconnection accesses) or the in the situation that of silicon substrate, be for example called TSV(Through Silicon Via: contact structures silicon via hole), to the different aspects of member are electrically connected to.At this, described vertical plating through hole allows special joint space-efficient structure type.Except connecting up simply again, this plating through hole can be realized each assembly and mutually be stacked into a so-called three-dimension packaging.Therefore, can with the form of section save space of three-dimension packaging build for example sensor chip, sensor wrap and analyzing and processing circuit (ASIC), wherein by electric plating through hole, realize the vertical electrical connection between each assembly.For the heap superimposition plating of each assembly, connecting also can term " MEMS three-dimensional is integrated ".
In vertical realization of connecting, make every effort to have the contact structures of as far as possible little basal plane.Electricity plating through hole has as far as possible little bulk resistor (Durchgangswiderstand) simultaneously.In order to realize this point, conventionally in Semiconductor substrate, produce very narrow, there is almost vertical Bi hole.This for example can realize by common grooving method or laser.Subsequently on the sidewall of contact hole and bottom the insulating barrier of deposition of thin and open the insulating barrier at place, contact hole bottom after, completely or partially with metal filled described hole.Described be filled in this or by CVD method (chemical vapour deposition: chemical vapour deposition (CVD)) or by by electro-plating method in conjunction with the previous initiation layer (seed-layer: inculating crystal layer) depositing metal layers is realized of deposition.
Because the manufacture of plating through hole is carried out completely when wafer technique finishes in described scheme, so these methods are also referred to as rear via hole (Via-Last).In described rear passing method, key is the quality of the difference of insulating barrier, because determined only can realize with little thickness the deposition of insulating materials by technology in having the deep hole of high aspect ratio.In addition, typically the oxide as insulating materials has relatively poor oxide mass, because only can use the deposition process with lower maximum technological temperature when wafer technique finishes.In addition,, due to the high aspect ratio in hole, open the insulating barrier difficulty especially at the bottom place in hole.This is the situation of applicable thick insulating barrier especially.Finally, the diffusion barrier deposition of typically implementing before metal deposition is also because the degree of depth in high aspect ratio and hole is very difficult technically.
Also can in operation stage more early, manufacture plating through hole in principle.Therefore, for example, in the centre of wafer technique, in wafer, produce blind hole, and blind hole is provided with insulating barrier and barrier layer (Barriere-schicht).After subsequently with metal filled contact hole, can between the structure on the front side of metal filled and wafer, produce and connect by simple front side technique.Subsequently, can carry out other front side technique.Before typically setting up metal printed conductor on wafer front side, so-called metal rear end, this manufactures filled blind hole.
When normal wafer operation finishes, grinding wafer on dorsal part is wherein carried out grinding so deeply, makes to expose the metal filled of blind hole.Finally, depositing insulating layer and open to the contact area of Metal Contact face in insulating barrier in wafer backside.The metal level that then, can also deposit in wafer backside by another is carried out connecting up again of Metal Contact portion.This typical in via hole (Via-Middle) technique, the difference of the metal using and the thermal coefficient of expansion of silicon substrate may cause the damage during backend process of the TSV structure that previously applied.In addition, grinding process confirms it is very difficult, for example, because simultaneously must the different material of grinding---silicon, oxide, barrier material and metal and this external this must be avoided metal fuzzy (Metall-verschmierung) as much as possible by insulated by oxide face.
Summary of the invention
Therefore, task of the present invention is, a kind of middle passing method for the manufacture of electric plating through hole is provided, described middle passing method in higher backend process temperature, be sane and in described middle passing method, avoid grinding simultaneously during metal scatter (Metallverschleppung).Described task solves by the method according to claim 1.In addition, described task solves by the member according to claim 11.Other favourable embodiments illustrate in the dependent claims.
According to the present invention, a kind of method for the manufacture of having the member of plating through hole is provided, wherein provides a kind of and there is the Semiconductor substrate of the opposed dorsal part in He Yu front side, front side and on the front side of Semiconductor substrate, produce the insulated trench that surrounds circlewise contact area.Subsequently, in insulated trench, apply insulating materials, to produce annular insulation system.Then implement the method step of backend process, in described backend process category, by deposits conductive material in contact area, on the front side in Semiconductor substrate, produce electric contact structure.Subsequently, on the dorsal part of Semiconductor substrate, remove and stay the semi-conducting material in contact area, to produce the contact hole of the downside that exposes contact structures.Finally, deposit metallic material in contact hole, to be electrically connected to electric contact structure with the dorsal part of semi-conducting material.In described method, after the manufacturing process of member finishes just with metal filled contact hole, thereby the plating through hole completing does not suffer higher backend process temperature.Conventionally the damage to TSV structure that can avoid thus the different heat expansion coefficient due to the metal filled and Semiconductor substrate of plating through hole to occur during backend process.Can when wafer technique finishes, use higher maximum technological temperature now, this for example can realize the more good quality of deposited oxide layer simultaneously.By using annular insulated trench, can realize the metal filled of plating through hole and around semi-conducting material between thick especially insulating barrier, this reduces again the danger that leakage current and condenser type disturb.Compare with the rear via hole technique that applies plating through hole completely when wafer technique finishes, neither need in the method according to the invention deposit and spread potential barrier also not need to open by contact hole the insulating barrier at place, contact hole bottom.Eliminate thus the problem of following.
According to a kind of embodiment, insulated trench is configured to blind hole, and produce electric contact structure on the front side of Semiconductor substrate after from dorsal part attenuate Semiconductor substrate, to expose insulating materials at this.The larger layer thickness of wafer during described method allows to process, simplifies the processing of wafer on the one hand thus and reduces on the other hand the danger of wafer breakage.Because after grinded semiconductor wafer just with metal filled contact hole, so differently reduce with middle passing method the danger that metal on insulated by oxide face is fuzzy.
Regulation after attenuate Semiconductor substrate, produces insulating barrier on the dorsal part of Semiconductor substrate in another embodiment.By isotropic engraving method, with respect to the insulating materials in insulating barrier and insulated trench, optionally remove subsequently the semi-conducting material of staying in contact area.Can realize thus the opening of self-adjustment of contact hole.At this, also etching has the dark contact hole of high aspect ratio reliably.
Another kind of embodiment regulation produces insulating barrier on the dorsal part of Semiconductor substrate, and from substrate front remove semi-conducting material until insulating barrier to produce insulated trench.Then, in contact area, open the insulating barrier on the dorsal part of Semiconductor substrate, and by the insulating materials with respect in insulating barrier and insulated trench optionally etching stay semi-conducting material in contact area to produce contact hole.By described method, can produce the contact hole with the definition degree of depth in simple especially mode.The insulating barrier producing on dorsal part at this is not only for manufacturing insulated trench but also for opening contact hole with dorsal part technique with front side technique.
Regulation, in order to apply insulating materials in insulated trench, is used the combination of oxide deposition and polysilicon deposition in another embodiment.The deposition of material of combination is particularly conducive to fills the groove with intermediate trenches width.
Stipulate in another embodiment, the glass applying in insulated trench by process for stamping, especially Pyrex are as insulating materials.By using glass, especially Pyrex as insulating materials, can produce relatively wide insulated trench, by described insulated trench, can reduce possible parasitic capacitance and the danger of leakage current.At this, can particularly advantageously fill exactly wider groove by process for stamping.Because glass has the thermal coefficient of expansion suitable with silicon, so can therefore reduce the mechanical stress of thermoinduction in substrate.
Regulation is carried out the deposition of metal material in contact hole together with manufacturing wiring again on dorsal part in Semiconductor substrate in another embodiment.Thus can method for saving step, the reduction that this causes not only the simplification of manufacture method and ground related to this but also causes the manufacturing cost of member.
Another kind of embodiment regulation, by grinding process, wet etching process or dry etching process or carry out the attenuate of Semiconductor substrate by the combination of grinding process and wet etching process or dry etching process.By the grinding process thick especially semiconductor layer of attenuate effectively.In contrast, wet etching process and dry etching process can be realized the selective removal of semi-conducting material.
Regulation, for metal material filling contact hole, is used low temperature deposition method in conjunction with barrier layer and/or inculating crystal layer in another embodiment.By low temperature deposition method, can the thermic load of the member completing be kept relatively lowly.Barrier layer effectively prevents that at this metal is diffused in semi-conducting material.In contrast, initiation layer or inculating crystal layer can be realized the optimum growh of metal material in contact hole.
Another kind of embodiment regulation is electrically connected to electric contact structure before deposit metallic material in bonding technology category in contact hole with the complementary contact structures of function substrate, in described bonding technology, Semiconductor substrate is connected with function substrate.Because just carry out the metal deposition in contact hole after bonding technology, so guaranteed that the plating through hole completing does not suffer the thermic load occurring during bonding technology.
Regulation, produces the hole for holding the lip-deep functional structure that is arranged on function substrate on the front side in Semiconductor substrate before Semiconductor substrate is connected with function substrate in another embodiment.By this hole, produce the spatial accommodation for functional structure, it can practical function structure be sealed with respect to the airtight of the external world.
In addition, propose a kind of member according to the present invention, it comprises having the plating through hole that penetrates Semiconductor substrate from the opposed dorsal part in Zhi Yu front side, front side.Plating through hole this comprise by with filling insulating material and surround circlewise insulation system that the insulated trench of contact area forms, electric contact structure on the front side that is arranged on the Semiconductor substrate in contact area and be arranged on contact area in by insulation system gauge and electric contact structure is electrically connected to the dorsal part of Semiconductor substrate metal filled.Because manufacture has the possibility of the insulated trench of any thickness, can make plating through hole mate different technology application.Especially by relatively wide insulated trench can realize metal filled with around the good electrical insulation of Semiconductor substrate.Can also reduce interference capacitors simultaneously.The all right metal filled diameter of any configuration, the bulk resistor of plating through hole can relatively simply be mated different application thus.
Stipulate in one embodiment, Semiconductor substrate has hole and is so connected with function substrate, makes the lip-deep functional structure that is arranged on function substrate be positioned at hole.Electric contact structure is electrically connected to the complementary contact structures of functional structure at this.In described device, the cover that acts on the functional structure of function substrate for Semiconductor substrate.Plating through hole allows to be enclosed in the electrical connection of two functional structures between substrate at this.
Accompanying drawing explanation
Below describe with reference to the accompanying drawings the present invention in detail.Accompanying drawing illustrates:
Fig. 1: the Semiconductor substrate with insulated trench circular structure, annular on front side;
Fig. 2: the Semiconductor substrate in Fig. 1, has the insulated trench with filling insulating material;
Fig. 3: the Semiconductor substrate in Fig. 2, with comprise before the function substrate bonding of functional structure thering is contact structures and the hole producing on front side;
Fig. 4: the Semiconductor substrate after bonding technology and function substrate;
Fig. 5: the Semiconductor substrate after dorsal part attenuate Semiconductor substrate;
Fig. 6: Semiconductor substrate, there is the insulating barrier on the dorsal part of Semiconductor substrate, described insulating barrier is opened in contact area;
Fig. 7: removing the member completing after the semi-conducting material in contact area of staying of Semiconductor substrate;
Fig. 8: in Fig. 7 at the member with after metal material filling contact hole.
The specific embodiment
Below exemplarily according to having at least one micro electronmechanical functional structure, the method according to this invention is explained in the manufacture of the member of---for example micro electronmechanical motion or speed probe---in detail.At this, in Semiconductor substrate, produce plating through hole, the cover wafer that acts on the micro electronmechanical functional structure being arranged on function substrate for described Semiconductor substrate.Onset point is the Semiconductor substrate of silicon wafer form for example at this, first produces the annular insulation system with the insulated trench form of filling insulating material in described Semiconductor substrate.Being manufactured on this and for example can realizing by common grooving method or by laser of insulated trench 121.Fig. 1 illustrates the Semiconductor substrate 100 with 101He Yu front side, front side 101 opposed dorsal parts 102.On Semiconductor substrate 100 front side 101, first produce annular groove structure 121.Groove structure 121 surrounds inner contact area 103 circlewise at this, and wherein " annular " also means other any extend close-shaped in the case except circular and rectangle.At this by by photoetching method (fluting) or produce groove structure 121 by laser ablation semi-conducting material.This preferably remove semi-conducting material until definition the degree of depth, thereby groove structure 121 only extends through a part for Semiconductor substrate 100.Fig. 1 illustrates the Semiconductor substrate 100 with the groove structure 121 having produced.
Subsequently, with filling insulating material groove structure 121.In described method, in the stage, allow high temperature.According to application, in order to produce insulating barrier, can use diverse ways.At this, especially relatively little for having, lower than for the groove structure of the groove width of 10 μ m advantageously, with thermal oxide layer, carry out closed groove structure.For medium groove width (between 5 μ m and 25 μ m), for example the combination with oxide deposition and polysilicon deposition carrys out filling groove.At this, deposited oxide layer and fill groove structure so that form, that reduce by polysilicon on the sidewall of groove structure 121 and bottom first.For relatively wide groove (being greater than 10 μ m), with glass---for example Pyrex filling groove proves particularly advantageous.For this reason, with process for stamping, in groove structure 121, apply glass.Fig. 2 illustrates the Semiconductor substrate 100 with the insulation system 120 by producing in the interior deposition of insulative material 122 of groove structure 121.
After filling insulated trench 121, carry out backend process, wherein by insulated trench around substrate surface on produce electric interface.Backend process also can comprise the manufacture of stack of wafers, wherein a plurality of wafers can be set each other stackingly.Therefore, for example sensor wafer can be bonded on ready substrate wafer.In current embodiment, function substrate 200 is bonded in Semiconductor substrate 100, wherein Semiconductor substrate 100 use act on the cover wafer that is arranged on the micro electronmechanical functional structure 221 on function substrate 200.By plating through hole, at this, set up to the electrical connection of the contact element of function substrate 200.For this reason, preferably electrically contacting with the manufacture of CMOS technique and the silicon plugs that surrounded by insulated trench.But for MEMS application, can also use substrate as cover and manufacture and the contact area of the second wafer, for example sensor wafer.The manufacture of the electric contact structure 130 in contact area 103 and the connection of two wafers are preferably undertaken by metal bonding method in a step.Bonding method by two metal level is particularly advantageous, and described two metal level are configured to have the combination of the alloy of liquid phase, and its melt temperature is lower than the melt temperature of each metal level.To this, can consider that for example aluminium and germanium, copper and zinc and similar system are as metallic combination.
Fig. 3 illustrates has the electric contact structure 130 of generation in contact area 103 and lip-deep other Semiconductor substrate 100 as the metal level 131,132 of syndeton of substrate front side 101.In addition, Fig. 3 illustrates the chip 200 being ready for Semiconductor substrate 100 bondings.The chip 200 that is for example constructed to sensor chip comprises the functional structure 210 with the functional layer 220 arranging thereon at this.For example, by the insulating barrier 240 functional layer 220 interior structure micro electronmechanical functional structure 221 separated with functional structure 210, micro electronmechanical motion sensor.Micro electronmechanical functional structure 221 is by being electrically connected to and contact structures 222,223 and electric contact structure 230 connections that are provided for being connected the electric contact structure 130 of semiconductor wafer.In addition, a plurality of syndetons 231,232 are set in functional layer 220, described a plurality of syndetons are with acting on the complementary syndeton being connected with the syndeton 131,132 of semiconductor wafer.
As shown in Figure 3, in Semiconductor substrate 100, produce and be used for holding micro electronmechanical functional structure 221 hole 105.The removal of semi-conducting material can realize by suitable engraving method at this.For bonding, chip 200 and Semiconductor substrate 100 is so directed, makes complementary terminal pad 231,232 dish 131,132 and complementary contact disc 230 contact disc 130 that reclines that is posted by connecting.After heating steps, syndeton 131,132,231,232 forms the syndeton 331,332 that connects Semiconductor substrate 100 and chip 200 now.In contrast, contact disc 130,230 forms the contact structures 130 that connect Semiconductor substrate 100 and chip now.The corresponding method stage is shown in Figure 4.
After backend process, from dorsal part 102 attenuate Semiconductor substrate 100.Described attenuate this can be by grinding process, by wet etching process or dry etching process or by the combination of these techniques, realize.When attenuate, by grinding process, wet etching process or dry etching process or by the combination degree like this of these techniques remove the semi-conducting material on the dorsal part 102 of Semiconductor substrate 100, until the insulated trench 121 of filling by insulating materials 122 exposes completely.Corresponding method state is shown in Figure 5.
Subsequently, by suitable method, from the dorsal part 102 of semiconductor wafer 100, remove and stay the semi-conducting material 104 contact area 103 between insulation system 120.In advance on the dorsal part 102 of Semiconductor substrate, apply insulating barrier 140, described insulating barrier also can be with the protection mask that acts on the semi-conducting material 104 in etching contact area 103.In this case, open the insulating barrier 140 in contact area 103.Corresponding method state is shown in Figure 6.
Subsequently, preferably by isotropic engraving method, with respect to insulating barrier 140 and insulating materials 121, optionally so remove insulating materials 104 to degree, until the downside 333 of contact structures 330 exposes.For etching semiconductor plunger 104, preferably use isotropic engraving method, described isotropic engraving method also allows high aspect ratio, for example, by CI, F3 or XeF2 or by SF6 plasma etching.Corresponding method state is shown in Figure 7.
Finally, with conductive material, especially metal material, fill formed contact hole 111.Can also with the dorsal part 102 of Semiconductor substrate 100 on 150 the manufacture of connecting up again side by side carry out fill process.Can carry out with known method the filling of contact hole 111.At this, low temperature method---for example to apply (Cu-ECD) be particularly advantageous in the plating of copper.Electro-coppering is deposited on this can be by for suppressing the suitable barrier layer of metal diffusion and combining for improving the inculating crystal layer of layer growth.Corresponding method state is shown in Figure 8.
For the wafer of bonding particularly advantageously, after bonding chip technique, just by metal, carry out the filling of contact hole 111, thereby make metal filled 104 during bonding technology, not suffer thermic load.Therefore,, for fill process, can also use and compare the metal with high thermal expansion coefficient with silicon---copper for example.Fig. 8 illustrates the member completing 300 of the sensor chip 200 having in Semiconductor substrate of being bonded in 100.Semiconductor substrate 100 uses at this cover wafer that acts on micro electronmechanical functional structure 211.The micro electronmechanical functional structure 211 that for example can be constructed to motion sensor is electrically connected to electric conductor structure 150 with contact structures 223,222,333 and 114 by being electrically connected to.
In a kind of alternative process variations scheme shown in Fig. 9 to 14, it is good in the situation that of attenuate semiconductor wafer not.Therefore, similar to Fig. 1, Fig. 9 illustrates Semiconductor substrate 100, and the Semiconductor substrate in itself and Fig. 9 differently has insulating barrier 141 on dorsal part 102.Insulated trench 121 is constructed now until insulating barrier 141.This preferably realizes by suitable engraving method, and wherein insulating barrier 141 is as etch stop layer.
Subsequently with insulating materials 122, especially glass---for example Pyrex are filled insulated trench 121.Described method state shown in Figure 10.
Then on Semiconductor substrate 100 front side 101, produce hole 105.In addition, for example by the suitable material of deposition, on Semiconductor substrate 100 front side 101, produce corresponding contact and terminal pad 130,131,132.Corresponding method state is shown in Figure 10.
In bonding technology, ready semiconductor wafer 100Yi Qi like this front side 101 is bonded on function substrate 210 or on corresponding chip 200.Corresponding method state is shown in Figure 11.
In another method step, open the insulating barrier 141 on the dorsal part 102 that is arranged on Semiconductor substrate 100 in contact area 103.Described method state is shown in Figure 12.
Subsequently, by suitable method, with respect to insulating barrier 141 with respect to the insulating materials 122 of insulation system 120, optionally remove the semi-conducting material 104 of staying in contact area 103, and expose the downside of contact structures 130 at this.Corresponding method state is shown in Figure 13.
Finally, with conductive material, preferably with the cavity of metal filled formation like this.When metallization, can also on the dorsal part 102 in Semiconductor substrate 100, produce again wire structures 151,152,153,154 simultaneously.Corresponding method state is shown in Figure 14.
Substitute the via hole of filling completely, metallization also can be implemented as metal level sidewall, thin that only infiltrates annular insulation system.
Although explain details of the present invention by preferred embodiment, the invention is not restricted to disclosed example.But can therefrom derive other flexible programs by those skilled in the art, and do not depart from protection scope of the present invention.Except material as mentioned herein---for example backing material, metallization material and insulating materials, can also be used other suitable materials substantially.Any significant combination of different materials is applicable to substantially for this reason.
Therefore, for example, can also carry out the metallization of contact hole and/or the manufacture of wiring again by jet printing method, the organic Nano Silver China ink that wherein for example use has easy discharge in order to metallize is as solvent.To this, substantially also can consider metal paste printing process.
In addition, substantially also can be for microelectromechaniccomponents components at the plating through hole on microelectromechaniccomponents components side of this manufacture.
Substantially likely, by following methods, manufacture microelectromechaniccomponents components: by wafer (Wafer-on-Wafer) method on so-called wafer---wherein wafer each other bonding and subsequently separated bonding wafer, by crystal grain (Die-on-Wafer) method on so-called wafer---separating wafer on wafer and subsequently by each grain bonding wherein, or by crystal grain (Die-on-Die) method on so-called crystal grain---separated crystal grain of bonding each other wherein.

Claims (13)

1. for the manufacture of a method with the member (300) of electric plating through hole (110), said method comprising the steps of:
Provide there is front side (101) and with the Semiconductor substrate (100) of the opposed dorsal part in described front side (102),
In the upper generation in the described front side (101) of described Semiconductor substrate (100), surround circlewise the insulated trench (121) of contact area (103),
In described insulated trench (121), apply insulating materials (122),
By deposits conductive material in described contact area (103), in the described front side (101) of described Semiconductor substrate (100), above produce electric contact structure (130),
Remove the semi-conducting material (104) in described contact area (103) of staying on the described dorsal part (102) of described Semiconductor substrate (100), to produce the contact hole (111) of the downside (134) that exposes described contact structures (130),
Deposit metallic material (114) in described contact hole (111), to be electrically connected to described electric contact structure (130) with the described dorsal part (102) of described Semiconductor substrate (100).
2. method according to claim 1, wherein, described insulated trench (121) is configured to blind hole, wherein, in the described front side (101) of described Semiconductor substrate (102) the upper described electric contact structure (130) that produces afterwards from Semiconductor substrate (100) described in described dorsal part (102) attenuate and expose described insulating materials (122) at this.
3. method according to claim 2, wherein, in Semiconductor substrate described in attenuate (100) afterwards, the upper insulating barrier (140) that produces of described dorsal part (102) in described Semiconductor substrate (100), wherein, by isotropic engraving method, with respect to the described insulating materials (122) in described insulating barrier (140) and described insulated trench (121), optionally remove the insulating materials (104) of staying in described contact area (103).
4. method according to claim 1, wherein, the upper insulating barrier (141) that produces of described dorsal part (102) in described Semiconductor substrate (100), and from the described front side (101) of described Semiconductor substrate (100), remove described semi-conducting material until described insulating barrier (141) to produce described insulated trench (121), wherein, in described contact area, open the described insulating barrier (141) on the described dorsal part (102) of described Semiconductor substrate (100), wherein, the semi-conducting material (104) of staying in described contact area (103) by etching optionally produces described contact hole (111) with respect to the described insulating materials (122) in described insulating barrier (141) and described insulated trench (121).
5. according to the method described in any one of the preceding claims, wherein, by process for stamping, in described insulated trench (121), apply glass, especially Pyrex as insulating materials (122).
6. according to the method described in any one of the preceding claims, wherein, in order to apply described insulating materials (122) in described insulated trench (121), use the combination of oxide deposition and polysilicon deposition.
7. according to the method described in any one of the preceding claims, wherein, connect up again together with (150) and carry out the deposition of described metal material (114) in described contact hole (111) with the upper manufacture of described dorsal part (102) in described Semiconductor substrate (100).
8. according to the method described in any one of the preceding claims, wherein, in order to fill described contact hole (111) with described metal material (114), use low temperature deposition method in conjunction with barrier layer and/or inculating crystal layer (115,116).
9. according to the method described in any one of the preceding claims, wherein, in bonding technology category, in described contact hole (111), the described metal material of deposition (122) is connected described electric contact structure (130) before with the complementary contact structures (230) of described function substrate (210), in described bonding technology, described Semiconductor substrate (100) is connected with function substrate (210).
10. method according to claim 9, wherein, before the described function substrate (210) on the described front side (101) of described Semiconductor substrate (100) and described Semiconductor substrate (100) is connected, produce the hole (105) that is used for holding the functional structure (221) being arranged on described function substrate (210).
A 11. member (300), it comprises that having from front side (101) extremely penetrates the electric plating through hole (110) of described Semiconductor substrate (100) with the opposed dorsal part in described front side (101) (102), wherein, described plating through hole (110) comprises the insulation system (120) being comprised of the insulated trench (121) that surrounds circlewise contact area (103) and fill with insulating materials (122), be arranged on the electric contact structure (330) on the described front side (101) of Semiconductor substrate (100) described in described contact area (103) and be arranged in described contact area (103) by described insulation system (120) gauge and metal filled (114) that described electric contact structure (330) is electrically connected to the described dorsal part (102) of described Semiconductor substrate (100).
12. members according to claim 11 (300), wherein, described Semiconductor substrate (100) has hole (105) and is so connected with function substrate (210), make the lip-deep functional structure (221) that is arranged on described function substrate (210) be positioned at described hole (105)
Wherein, described electric contact structure (130) is electrically connected to the complementary contact structures (230) of described functional structure (221).
13. according to the member described in claim 11 or 12 (300), and wherein, described insulated trench (121) has glass, especially Pyrex as insulating materials (122).
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105731360A (en) * 2014-12-09 2016-07-06 中芯国际集成电路制造(上海)有限公司 MEMS sensor and preparation method of MEMS sensor
CN105967140A (en) * 2016-07-27 2016-09-28 上海华虹宏力半导体制造有限公司 Method for forming MEMS wafer electrical connection through polycrystal germanium-silicon through hole
CN109860098A (en) * 2019-01-07 2019-06-07 中国科学院微电子研究所 A kind of SOI device structure and preparation method thereof
CN112093773A (en) * 2020-09-16 2020-12-18 上海矽睿科技有限公司 Method for preparing micro-mechanical equipment

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160086391A1 (en) * 2012-03-14 2016-03-24 Autoconnect Holdings Llc Fleetwide vehicle telematics systems and methods
FR3008690B1 (en) * 2013-07-22 2016-12-23 Commissariat Energie Atomique DEVICE COMPRISING A FLUID CHANNEL PROVIDED WITH AT LEAST ONE MICRO OR NANOELECTRONIC SYSTEM AND METHOD OF MAKING SUCH A DEVICE
KR101538543B1 (en) * 2013-08-13 2015-07-22 앰코 테크놀로지 코리아 주식회사 Semiconductor Device and Fabricating Method Thereof
DE102014002824A1 (en) * 2014-02-25 2015-08-27 Northrop Grumman Litef Gmbh Method for producing a component
NO2777050T3 (en) 2014-02-25 2018-06-16
US9776858B2 (en) * 2014-02-26 2017-10-03 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement and formation thereof
US10379497B2 (en) * 2015-03-07 2019-08-13 Apple Inc. Obtaining and displaying time-related data on an electronic watch
US10273148B2 (en) * 2015-08-14 2019-04-30 Taiwan Semiconductor Manufacturing Company Ltd. Micro-electro-mechanical system and manufacturing method thereof
US10410981B2 (en) * 2015-12-31 2019-09-10 International Business Machines Corporation Effective medium semiconductor cavities for RF applications
JP2021044498A (en) * 2019-09-13 2021-03-18 キオクシア株式会社 Manufacturing method of semiconductor device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101208771A (en) * 2005-05-04 2008-06-25 艾斯莫斯技术公司 Silicon wafer having through-wafer vias
WO2008136316A1 (en) * 2007-04-26 2008-11-13 Alps Electric Co., Ltd. Laminated substrate structure and method for manufacturing the same
CN101789390A (en) * 2009-01-23 2010-07-28 财团法人工业技术研究院 Manufacturing method of silicon through hole and silicon through hole structure
US20110031565A1 (en) * 2009-08-04 2011-02-10 David Lambe Marx Micromachined devices and fabricating the same
CN102208363A (en) * 2011-05-13 2011-10-05 中国科学院微电子研究所 Method for forming through silicon via
CN102254948A (en) * 2011-07-29 2011-11-23 北京大学 Tunneling field effect transistor with double-gate structure and preparing method thereof
CN102362346A (en) * 2008-12-23 2012-02-22 西雷克斯微系统股份有限公司 Via structure and method thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4873517B2 (en) 2004-10-28 2012-02-08 オンセミコンダクター・トレーディング・リミテッド Semiconductor device and manufacturing method thereof
DE102008021568B3 (en) * 2008-04-30 2010-02-04 Advanced Micro Devices, Inc., Sunnyvale A method of reducing erosion of a metal cap layer during via formation in semiconductor devices and semiconductor device with a protective material for reducing erosion of the metal cap layer
TWI366890B (en) * 2008-12-31 2012-06-21 Ind Tech Res Inst Method of manufacturing through-silicon-via and through-silicon-via structure
JP2011014728A (en) * 2009-07-02 2011-01-20 Casio Computer Co Ltd Semiconductor device and method of manufacturing semiconductor device
TWI405321B (en) * 2009-09-08 2013-08-11 Ind Tech Res Inst 3d multi-wafer stacked semiconductor structure and method for manufacturing the same
US7956463B2 (en) * 2009-09-16 2011-06-07 International Business Machines Corporation Large grain size conductive structure for narrow interconnect openings
DE102010039298B4 (en) * 2010-08-13 2022-11-10 Robert Bosch Gmbh Process for filling cavities in wafers
KR20120030782A (en) * 2010-09-20 2012-03-29 삼성전자주식회사 Method of forming through silicon via using low-k material

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101208771A (en) * 2005-05-04 2008-06-25 艾斯莫斯技术公司 Silicon wafer having through-wafer vias
WO2008136316A1 (en) * 2007-04-26 2008-11-13 Alps Electric Co., Ltd. Laminated substrate structure and method for manufacturing the same
CN102362346A (en) * 2008-12-23 2012-02-22 西雷克斯微系统股份有限公司 Via structure and method thereof
CN101789390A (en) * 2009-01-23 2010-07-28 财团法人工业技术研究院 Manufacturing method of silicon through hole and silicon through hole structure
US20110031565A1 (en) * 2009-08-04 2011-02-10 David Lambe Marx Micromachined devices and fabricating the same
CN102208363A (en) * 2011-05-13 2011-10-05 中国科学院微电子研究所 Method for forming through silicon via
CN102254948A (en) * 2011-07-29 2011-11-23 北京大学 Tunneling field effect transistor with double-gate structure and preparing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105731360A (en) * 2014-12-09 2016-07-06 中芯国际集成电路制造(上海)有限公司 MEMS sensor and preparation method of MEMS sensor
CN105731360B (en) * 2014-12-09 2017-10-10 中芯国际集成电路制造(上海)有限公司 MEMS sensor and preparation method thereof
CN105967140A (en) * 2016-07-27 2016-09-28 上海华虹宏力半导体制造有限公司 Method for forming MEMS wafer electrical connection through polycrystal germanium-silicon through hole
CN105967140B (en) * 2016-07-27 2017-08-25 上海华虹宏力半导体制造有限公司 Utilize the method for poly-SiGe through hole formation MEMS wafer electrical connection
CN109860098A (en) * 2019-01-07 2019-06-07 中国科学院微电子研究所 A kind of SOI device structure and preparation method thereof
CN112093773A (en) * 2020-09-16 2020-12-18 上海矽睿科技有限公司 Method for preparing micro-mechanical equipment

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