CN103500585A

CN103500585A - Control circuit for controlling single programmable memory and control method of control circuit

Info

Publication number: CN103500585A
Application number: CN201310466671.2A
Authority: CN
Inventors: 朱潇挺; 蒋振雷
Original assignee: WUXI NAXUN MICROELECTRONIC CO Ltd
Current assignee: WUXI NAXUN MICROELECTRONIC CO Ltd
Priority date: 2013-10-09
Filing date: 2013-10-09
Publication date: 2014-01-08
Anticipated expiration: 2033-10-09
Also published as: CN103500585B

Abstract

The invention discloses a control circuit for controlling a single programmable memory and a control method of the control circuit. The control circuit comprises an upper computer, an interface circuit, a bus controller and the single programmable memory, wherein the upper computer is connected with the bus controller through the interface circuit; the bus controller is also connected with the single programmable memory; the upper computer is connected with the interface circuit through a data wire. According to the control method disclosed by the invention, resolving of data input through the interface circuit is implemented, and a complete control signal for controlling the memory is generated.

Description

A kind of control circuit and control method thereof for controlling single programmable memory

Technical field

The invention belongs to technical field of semiconductors, relate in particular to a kind of control circuit and control method thereof for controlling single programmable memory.

Background technology

Now, there are many chips need to be in Embedded disposable programmable memory and debug registers, in order in chip carries out finished product test or user's use procedure, the parameter of chip internal is adjusted and revised.But many middle and small scale circuit are due to the restriction of number of pins and function, or do not have special-purpose communication interface.For example SPI and I2C interface at least need 2-3 root private communication line.

Summary of the invention

Goal of the invention: the objective of the invention is to disclose a kind of control circuit and control method thereof for controlling single programmable memory for the deficiencies in the prior art, thereby only need a data line just can realize the operation of host computer to single programmable memory.

Technical scheme: in order to realize the purpose of invention, the invention discloses a kind of for controlling the control circuit of single programmable memory, comprise host computer, interface circuit, bus controller and single programmable memory, host computer is connected with bus controller by interface circuit, bus controller is connected with single programmable memory simultaneously, it is characterized in that, host computer is connected with interface circuit by a data lines; Host computer and interface circuit are connected with the DATA line, by there is no the clock

period signal indication

1 or 0 occured simultaneously; Be connected with din line and doen line between interface circuit and bus controller, the din line is for the data of host computer are sent to bus controller, and the doen line is for being sent to host computer by the response signal of bus controller; Be connected with load line, fuse_blowb line, fuse_data_b line, fuse_rb line, fuse_sb line, I_clk line and I_rstn line between bus controller and single programmable memory, wherein, the load line transfers to the reading address of single programmable memory for bus controller; The fuse_blowb line is the programming zone bit; The fuse_data_b line is the programming address; The fuse_rb line is for control bus controller reseting register, and fuse_sb is for the mid-bit register of control bus controller; The I_clk line is clock signal; The I_rstn line is reset signal.The port of described DATA line means 0 by the low level of 5～30 clock period, by the low level of 30～255 clock period, means 1.

According to embodiments of the invention on the other hand, the invention discloses a kind of for controlling the control method of single programmable memory, comprise the following steps: (1) bus controller receives the security code from interface circuit by the din line, provide response signal from the doen line by dragging down the DATA line, then by interface circuit, read on the DATA line address of wanting operation, the value of operation address has meaned a certain position of load line; (2) receive after operation address, this bit representation the operator scheme that is about to carry out for reading or writing; (3) if the operator scheme in step (2) for reading, bus controller is read value by the corresponding positions of fuse_rb line and fuse_sb line, and, by the time representation of the drop-down DATA line of doen, even read output signal is 0, the drop-down time is 5-30 clock period.If read output signal is 1, a drop-down 30-255 clock period, the read operation of such address is complete; If the operator scheme in step (2) is for writing, the corresponding positions of fuse_data_b line is set low, then the DATA line drags down and fuse_blowb is also synchronously dragged down, low level holding time is the time of writing, after writing end, whether bus controller can complete this read operation, for checking this position, correctly write, and the write operation of an address is complete.Described operation address binary coding representation; The security code of described step (1) adopts the binary code more than 4.

Beneficial effect: the present invention compared with prior art, has following advantage: can complete the parsing of data of interface circuit input and the complete control signal that produces control store by a data lines.

The accompanying drawing explanation

Fig. 1 is the annexation figure for the control circuit of controlling single programmable memory of the present invention;

The sequential chart that Fig. 2 is read operation of the present invention;

The sequential chart that Fig. 3 is write operation of the present invention.

Embodiment

Following examples are used for the present invention is described, but are not used for limiting the scope of the invention.

As shown in Figure 1, the single programmable memory of 8bit of take is example, Load[7:0]: mean to want the bit read; Fuse_blowb means after configuring the bit of wanting programming, and after Fuse_blowb drags down, the programming process starts, Low level effective; Fuse_data_b[7:0]: mean to want the bit address of programming, each bit is corresponding with a single programmable memory unit, Low level effective; Fuse_rb[7:0], Fuse_sb[7:0] mean that the single programmable memory unit is when reading single programmable memory at 1 o'clock, corresponding Fuse_rb sets to 0, and Fuse_sb puts 1.When readout is 0, corresponding Fuse_rb puts 1, Fuse_sb and sets to 0, and this two signal is for SET and the RESET end of control bus controller corresponding registers.I_clk is the work clock signal.I_rstn is reset signal, Low level effective.Din is the data from host computer to bus controller for transmission.Doen is for being sent to host computer by the response signal of bus controller, and this is that to control the doen signal by bus controller be 1, then passes through the drop-down DATA pin of switch, and the DATA pin is connected to power supply by pull-up resistor in interface circuit.

As shown in Figure 2, owing to being single line communication, there is no special-purpose data line and clock line, therefore in all sequential, 05 to 30 of use clock period meaned, 1 30 to 255 of use clock period meaned, due in the chip clock period along with the variation meeting of technique deviation slightly, can guarantee suitable nargin with above-mentioned method for expressing.At first being a string security code, is 10101100 in this example, and in reality, this security code can carry out difference setting as required.Providing response signal after controller reads in correct security code undercuts bus, and then from DATA end input, want to read the address of position, this address is with binary coding, can be expanded according to the figure place of actual single programmable memory, back to back is operator scheme, at this for reading, with 0, mean, for example want that the address of reading is 0100 so corresponding load[4] can be after read signal finishes effectively, corresponding single programmable memory passes through Fuse_rb[4] and Fuse_sb[4] read, then on bus, there will be the value of reading.So far an address read end of operation, if need to read another one, only need to repeat aforesaid operations, is changed to another address.

As shown in Figure 3, consistent with read operation at the leading portion of write operation, behind the address of input corresponding operating, immediately following one be operating as, write, with 1, mean.For example be similarly 0100 Fuse_data_b[4 now] set low, after this step completes, the DATA pin drags down, and corresponding fuse_blowb is synchronously dragged down, and low level length is the programming time.After programming finishes, bus controller can complete the read operation of a corresponding positions, and whether the check corresponding positions is correctly write, and is the process of write verification.So far a bit write operation finishes, and writes another bit if want, only needs to repeat aforesaid operations, is changed to another address.

Show by above-mentioned read-write process the complete control signal that the present invention can achieve a butt joint mouthful parsing of the data of circuit input and produce control store by single bus and control method of the present invention.

Claims

1. one kind for controlling the control circuit of single programmable memory, comprise host computer, interface circuit, bus controller and single programmable memory, host computer is connected with bus controller by interface circuit, bus controller is connected with single programmable memory simultaneously, it is characterized in that, host computer is connected with interface circuit by a data lines;

Host computer and interface circuit are connected with the DATA line, by there is no the clock period signal indication 1 or 0 occured simultaneously;

Be connected with din line and doen line between interface circuit and bus controller, the din line is for the data of host computer are sent to bus controller, and the doen line is for being sent to host computer by the response signal of bus controller;

Be connected with load line, fuse_blowb line, fuse_data_b line, fuse_rb line, fuse_sb line, I_clk line and I_rstn line between bus controller and single programmable memory,

Wherein, the load line transfers to the reading address of single programmable memory for bus controller; The fuse_blowb line is the programming zone bit; The fuse_data_b line is the programming address; The fuse_rb line is for control bus controller reseting register, and fuse_sb is for the mid-bit register of control bus controller; The I_clk line is clock signal; The I_rstn line is reset signal.

2. as claimed in claim 1 a kind ofly it is characterized in that for controlling the control circuit of single programmable memory, the port of DATA line means 0 by the low level of 5～30 clock period, by the low level of 30～255 clock period, means 1.

3. one kind for controlling the control method of single programmable memory, it is characterized in that, comprises the following steps:

(1) bus controller receives the security code from interface circuit by the din line, provide response signal from the doen line by dragging down the DATA line, then by interface circuit, read on the DATA line address of wanting operation, the value of operation address has meaned a certain position of load line;

(2) receive after operation address, this bit representation the operator scheme that is about to carry out for reading or writing;

(3) if the operator scheme in step (2) for reading, bus controller is read value by the corresponding positions of fuse_rb line and fuse_sb line, and, by the time representation of the drop-down DATA line of doen, even read output signal is 0, the drop-down time is 5-30 clock period.If read output signal is 1, a drop-down 30-255 clock period, the read operation of such address is complete;

If the operator scheme in step (2) is for writing, the corresponding positions of fuse_data_b line is set low, then the DATA line drags down and fuse_blowb is also synchronously dragged down, low level holding time is the time of writing, after writing end, whether bus controller can complete this read operation, for checking this position, correctly write, and the write operation of an address is complete.

4. as claimed in claim 3 a kind ofly it is characterized in that for controlling the control method of single programmable memory, the operation address binary coding representation.

5. as described as claim 3 or 4 a kind ofly it is characterized in that for controlling the control method of single programmable memory, the security code in step (1) adopts the binary code more than 4.