CN103489765A - Method for manufacturing NMOS metal gate electrode - Google Patents
Method for manufacturing NMOS metal gate electrode Download PDFInfo
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- CN103489765A CN103489765A CN201210189781.4A CN201210189781A CN103489765A CN 103489765 A CN103489765 A CN 103489765A CN 201210189781 A CN201210189781 A CN 201210189781A CN 103489765 A CN103489765 A CN 103489765A
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- gate
- replacement gate
- semiconductor substrate
- layer
- polysilicon replacement
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 25
- 239000002184 metal Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 61
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims description 44
- 230000006835 compression Effects 0.000 claims description 18
- 238000007906 compression Methods 0.000 claims description 18
- 230000008021 deposition Effects 0.000 claims description 9
- 238000006116 polymerization reaction Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 9
- 238000005498 polishing Methods 0.000 abstract description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 abstract 2
- 230000003647 oxidation Effects 0.000 abstract 2
- 238000007254 oxidation reaction Methods 0.000 abstract 2
- 239000000126 substance Substances 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- NRCKPUWWRHKANR-UHFFFAOYSA-N [O].[N].[Si].[Hf] Chemical compound [O].[N].[Si].[Hf] NRCKPUWWRHKANR-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005234 chemical deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910017464 nitrogen compound Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
Abstract
The invention discloses a method for manufacturing an NMOS metal gate electrode. The method comprises the following steps: forming a gate structure on the surface of a semiconductor substrate, wherein the gate structure includes a high-dielectric-constant gate oxidation layer and side wall layers, the high-dielectric-constant gate oxidation layer is located below a polycrystalline silicon alternate gate and contacts the semiconductor substrate, and the side wall layers are located at the two sides of the polycrystalline silicon alternate gate; performing N-type doping on the semiconductor substrate at the two sides of the gate structure to form a source region and a drain region; depositing an interlayer dielectric layer which covers the surface of the semiconductor substrate and the gate structure, and carrying out chemical mechanical polishing on the interlayer dielectric layer until the polycrystalline silicon alternate gate is exposed; removing a predetermined part of the polycrystalline silicon alternate gate, epitaxially forming a silicon germanium layer with compressive stress on the surface of the remaining polycrystalline silicon alternate gate and transferring transverse tensile stress to a channel region between the source region and the drain region; and removing the remaining polycrystalline silicon alternate gate and the epitaxially-formed silicon germanium layer with compressive stress and depositing and forming a metal gate electrode at the position of the polycrystalline silicon alternate gate. Therefore, stress can be applied to a channel accurately.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of NMOS metal gate electrode.
Background technology
At present, when manufacturing semiconductor device, can use silicon nitride to cause stress in transistor channel, thereby regulate carrier mobility in raceway groove.For nmos device, need on the NMOS structure, deposit the silicon nitride layer with tensile stress (tensile stress).
The manufacture method of NMOS metal gate electrode in prior art, in conjunction with its concrete cross-sectional view, Fig. 1 a to Fig. 1 e describes.
Refer to Fig. 1 a, form grid structures on Semiconductor substrate 100 surface, described grid structure comprises and is positioned at the high-k gate oxide 102 that polysilicon replacement gate 101 belows contact with Semiconductor substrate and the side wall layer 103 that is positioned at polysilicon replacement gate 101 both sides.
Concrete, deposit successively gate oxide and the polysilicon layer with high-k on Semiconductor substrate.The high-k gate oxide can be hafnium silicate, hafnium silicon oxygen nitrogen compound, hafnium oxide etc., and dielectric constant generally all is greater than 15;
Then polysilicon layer is carried out to etching, form polysilicon replacement gate 101;
Next form side wall layer 103 in polysilicon replacement gate both sides, be specially: can pass through the chemical vapor deposition (CVD) method on polysilicon replacement gate surface and semiconductor substrate surface deposit one deck silica, then etching forms side wall layer 103, and thickness is about tens nanometers.
Refer to Fig. 1 b, carry out the N-type doping and form source region and drain region 104 on the Semiconductor substrate 100 of grid structure both sides.
Wherein, nmos device is with electronics as majority carrier, so the source region of nmos device and drain region are N-type, the ion of injection is phosphorus or arsenic.
Refer to Fig. 1 c, deposit successively silicon nitride layer 105 and the interlayer dielectric layer 106 with tensile stress on the surface of said structure.
Wherein, the silicon nitride layer 105 with tensile stress covers source region and drain region, then indirectly horizontal tensile stress is applied in the raceway groove between source region and drain region.
Refer to Fig. 1 d, silicon nitride layer 105 and interlayer dielectric layer 106 are carried out to cmp to manifesting polysilicon replacement gate 101.
Refer to Fig. 1 e, remove polysilicon replacement gate 101, in the position of polysilicon replacement gate, deposition forms metal gate electrode 107.
During deposition, the metal gate electrode material also can cover the surface of interlayer dielectric layer 106, then, by CMP, the lip-deep metal gate electrode material of interlayer dielectric layer 106 is carried out to polishing, finally forms metal gate electrode 107.Wherein, as the material of metal gate electrode, can be the combination of any two kinds or three kinds in titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN).
Regulate carrier mobility in the NMOS raceway groove in prior art, that silicon nitride layer by having tensile stress (tensile stress) is applied to tensile stress on source region and drain region, then indirectly horizontal tensile stress is applied in raceway groove, therefore the effect of stress application is poor, can't accurately reach the requirement of device channel counter stress.
Summary of the invention
In view of this, the technical problem that the present invention solves is: accurately to the raceway groove stress application.
For solving the problems of the technologies described above, technical scheme of the present invention specifically is achieved in that
The invention discloses a kind of manufacture method of NMOS metal gate electrode, the method comprises:
Form grid structure at semiconductor substrate surface, described grid structure comprises the side wall layer that is positioned at the high-k gate oxide contacted with Semiconductor substrate below the polysilicon replacement gate and is positioned at polysilicon replacement gate both sides;
Carry out the N-type doping and form source region and drain region on the Semiconductor substrate of grid structure both sides;
The deposition interlayer dielectric layer, described interlayer dielectric layer covers semiconductor substrate surface and grid structure, and described interlayer dielectric layer is carried out to cmp to manifesting the polysilicon replacement gate;
Remove predetermined portions polysilicon replacement gate, and form the silicon germanide layer with compression in remaining polysilicon replacement gate surface extension, horizontal tensile stress is passed to the channel region between source region and drain region;
Remove the silicon germanide layer with compression that remaining polysilicon replacement gate and extension form, in the position of polysilicon replacement gate, deposition forms metal gate electrode.
The thickness of remaining polysilicon replacement gate is not more than 1/2 of whole polysilicon replacement gate thickness.
After extension formation has the silicon germanide layer of compression, the method further comprises carries out annealing in process to described silicon germanide layer, or ultraviolet light polymerization UV cure, or the step of Microwave Treatment.
As seen from the above technical solutions, method of the present invention is when making the NMOS metal gate electrode, directly compression is applied to raceway groove directly over, and expand the bottom sidewall by lattice misfit, thereby raceway groove is produced to horizontal tensile stress, regulate carrier mobility in raceway groove, compared with prior art, regulate stress more accurate.
The accompanying drawing explanation
The structural representation of the concrete manufacturing process that Fig. 1 a to Fig. 1 e is prior art NMOS metal gate electrode.
The schematic flow sheet that Fig. 2 is NMOS metal gate electrode manufacture method of the present invention.
The structural representation of the concrete manufacturing process that Fig. 3 a to Fig. 3 e is NMOS metal gate electrode of the present invention.
Embodiment
For make purpose of the present invention, technical scheme, and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention far and away.
The present invention utilizes schematic diagram have been described in detail, when the embodiment of the present invention is described in detail in detail, for convenience of explanation, the schematic diagram that means structure can be disobeyed local amplification of general ratio work, should not using this as limitation of the invention, in addition, in actual making, should comprise the three-dimensional space of length, width and the degree of depth.
The flow chart of NMOS metal gate electrode manufacture method of the present invention as shown in Figure 2, is elaborated below in conjunction with Fig. 3 a to Fig. 3 e, and it comprises the following steps:
Concrete, deposit successively gate oxide and the polysilicon layer with high-k on Semiconductor substrate.The high-k gate oxide can be hafnium silicate, hafnium silicon oxygen nitrogen compound, hafnium oxide etc., and dielectric constant generally all is greater than 15;
Then polysilicon layer is carried out to etching, form polysilicon replacement gate 101;
Next form side wall layer 103 in polysilicon replacement gate both sides, be specially: can pass through the chemical vapor deposition (CVD) method on polysilicon replacement gate surface and semiconductor substrate surface deposit one deck silica, then etching forms side wall layer 103, and thickness is about tens nanometers.
Step 22, refer to Fig. 3 b, carry out the N-type doping and form source region and drain region 104 on the Semiconductor substrate 100 of grid structure both sides;
Wherein, nmos device is with electronics as majority carrier, so the source region of nmos device and drain region are N-type, the ion of injection is phosphorus or arsenic.
Wherein, the thickness of remaining polysilicon replacement gate is not more than 1/2 of whole polysilicon replacement gate thickness, as long as epitaxial growth SiGe layer 301 thereon.
In silicon germanide layer 301, the atomic radius of germanium is greater than silicon, therefore on volume, can expand, and extruding sidewall and bottom, nature can produce downward compression to raceway groove like this, and horizontal tensile stress, and wherein horizontal tensile stress is the principal element that the NMOS raceway groove benefits.Due to the follow-up silicon germanide layer with compression 301 that will remove remaining polysilicon replacement gate 101 ' and extension formation, so extension forms the height of the silicon germanide layer 301 with compression and does not limit, as long as can apply horizontal tensile stress to raceway groove, highly can to the requirement of compression, be regulated according to device.
During deposition, the metal gate electrode material also can cover the surface of interlayer dielectric layer 300, then, by CMP, the lip-deep metal gate electrode material of interlayer dielectric layer 300 is carried out to polishing, finally forms metal gate electrode 107.Wherein, as the material of metal gate electrode, can be the combination of any two kinds or three kinds in titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN).
Further, in order to optimize the effect of 301 pairs of raceway groove stress applications of the silicon germanide layer with compression that extension forms, can also carry out annealing in process to described silicon germanide layer, or ultraviolet light polymerization (UV cure), or the step of Microwave Treatment.Usually, all be provided with UV curing apparatus in chemical deposition equipment, and the ultraviolet light that the present invention sends also is not limited to chemical deposition equipment, as long as the ultraviolet wavelength scope that ultraviolet light polymerization adopts reaches 200～400 nanometers.
The above, be only preferred embodiment of the present invention, is not intended to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (3)
1. the manufacture method of a NMOS metal gate electrode, the method comprises:
Form grid structure at semiconductor substrate surface, described grid structure comprises the side wall layer that is positioned at the high-k gate oxide contacted with Semiconductor substrate below the polysilicon replacement gate and is positioned at polysilicon replacement gate both sides;
Carry out the N-type doping and form source region and drain region on the Semiconductor substrate of grid structure both sides;
The deposition interlayer dielectric layer, described interlayer dielectric layer covers semiconductor substrate surface and grid structure, and described interlayer dielectric layer is carried out to cmp to manifesting the polysilicon replacement gate;
Remove predetermined portions polysilicon replacement gate, and form the silicon germanide layer with compression compressive stress in remaining polysilicon replacement gate surface extension, horizontal tensile stress is passed to the channel region between source region and drain region;
Remove the silicon germanide layer with compression that remaining polysilicon replacement gate and extension form, in the position of polysilicon replacement gate, deposition forms metal gate electrode.
2. the method for claim 1, is characterized in that, the thickness of remaining polysilicon replacement gate is not more than 1/2 of whole polysilicon replacement gate thickness.
3. the method for claim 1, is characterized in that, after extension formation has the silicon germanide layer of compression, the method further comprises carries out annealing in process to described silicon germanide layer, or ultraviolet light polymerization UV cure, or the step of Microwave Treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210189781.4A CN103489765B (en) | 2012-06-11 | 2012-06-11 | The manufacture method of NMOS metal gate electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210189781.4A CN103489765B (en) | 2012-06-11 | 2012-06-11 | The manufacture method of NMOS metal gate electrode |
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| Publication Number | Publication Date |
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| CN103489765A true CN103489765A (en) | 2014-01-01 |
| CN103489765B CN103489765B (en) | 2016-06-22 |
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| CN201210189781.4A Active CN103489765B (en) | 2012-06-11 | 2012-06-11 | The manufacture method of NMOS metal gate electrode |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060071285A1 (en) * | 2004-09-29 | 2006-04-06 | Suman Datta | Inducing strain in the channels of metal gate transistors |
| US20070077765A1 (en) * | 2005-09-30 | 2007-04-05 | Prince Matthew J | Etch stop and hard mask film property matching to enable improved replacement metal gate process |
| US20080064197A1 (en) * | 2004-04-23 | 2008-03-13 | International Business Machines Corporation | STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C |
| US20090230427A1 (en) * | 2008-03-13 | 2009-09-17 | International Business Machines Corporation | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing |
| US20100330757A1 (en) * | 2009-06-30 | 2010-12-30 | Markus Lenski | Enhanced cap layer integrity in a high-k metal gate stack by using a hard mask for offset spacer patterning |
-
2012
- 2012-06-11 CN CN201210189781.4A patent/CN103489765B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080064197A1 (en) * | 2004-04-23 | 2008-03-13 | International Business Machines Corporation | STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C |
| US20060071285A1 (en) * | 2004-09-29 | 2006-04-06 | Suman Datta | Inducing strain in the channels of metal gate transistors |
| US20070077765A1 (en) * | 2005-09-30 | 2007-04-05 | Prince Matthew J | Etch stop and hard mask film property matching to enable improved replacement metal gate process |
| US20090230427A1 (en) * | 2008-03-13 | 2009-09-17 | International Business Machines Corporation | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing |
| US20100330757A1 (en) * | 2009-06-30 | 2010-12-30 | Markus Lenski | Enhanced cap layer integrity in a high-k metal gate stack by using a hard mask for offset spacer patterning |
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| Publication number | Publication date |
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| CN103489765B (en) | 2016-06-22 |
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