CN103458432B - Simulated BBU test device, system and method for LTE RRU - Google Patents

Abstract

The invention provides a simulated BBU test device, system and method for an LTE RRU. The device comprises a processor module, a logic module, an optical port module and a clock module, wherein the processor module, the logic module and the optical port module are sequentially electrically connected, and the clock module outputs clock signals to the logic module, the optical port module and the processor module. The processor module comprises a CPU chip, a CPLD, a storage unit and a port circuit, wherein the CPLD, the storage unit and the port circuit are connected with the CPU chip. The logic module comprises an FPGA and an SRAM. The optical port module comprises a series and parallel conversion unit and a photovoltaic conversion unit. The device and system are simple in structure, strong in universality and capable of providing a basic RRU test environment by achieving partial functions of a real LTE-BBU under the condition that a real BBU is not used and additional revision, for matching of the RRU and a test, of original functions of the to-be-tested RRU is needless, and completely meet requirements of various test operations of performance indexes and stability of RRUs of multiple systems.

Description

Analog BBU for LTE RRU tests device, system and method

Technical field

The present invention relates to communication technical field, especially relate to a kind of analog BBU testing scheme for LTE radio extension unit.

Background technology

Existing LTE(Long Term Evolution, Long Term Evolution) E-NodeB(Evolved NodeB, the B node of evolution) use distributed frame more, the technical characterstic of distributed base station refers to the BBU(Base Band Unit of base station, base station processing unit) and RRU(Remote Radio Unit, Remote Radio Unit) respectively as independent module a kind of base station mode that is separated and that be connected by optical fiber.One radio-frequency channel of RRU includes transmission channel and receives passage.According to actual networking and application scenarios, RRU port number can be 1,2,4,8.RRU+BBU constitutes traditional complete base station, and wherein, the major function that BBU part realizes is: master control, clock, Base-Band Processing, Iub interface process, and the major function that RRU realizes includes: digital intermediate frequency, transceiver, power amplifier and LNA.Connect with optical fiber between the two, transmission base band.Iub interface is the interface between RNC and Node B.

Remote Radio Unit is an indispensable part in LTE network distributed base station equipment, and its performance indications directly affect the quality of whole network.In the actual production and R&D process of RRU, the indices to RRU and stability is needed to test.Owing to RRU is mainly responsible for realizing the radio frequency part in LTE base station system, and can only be connected with BBU by optical fiber, so the test of current RRU depends on baseband processing unit BBU and the radiofrequency generator instruments and meters of complexity, be not easy to research and development and the production of RRU.Therefore, research and development one has basic BBU function, and can provide corresponding test case and the analog BBU system of test software according to the feature of RRU, for simplifying the test mode of RRU, reduce testing cost, accelerate the commercial process of LTE network, it is ensured that the quality of network is significant.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of testing scheme for LTE radio extension unit, enabling with the test job completing LTE radio extension unit of cheap cost-effective.

The technical scheme is that a kind of analog BBU for LTE RRU tests device, described RRU is base station processing unit, described BBU is Remote Radio Unit, including processor module, logic module, optical interface module and clock module, processor module, logic module, optical interface module are electrically connected with successively, and clock module exports clock signal respectively to logic module, optical interface module and processor module；

Described processor module, including cpu chip and the CPLD, memory element and the interface circuit that are connected respectively with cpu chip；

Described logic module, connects including FPGA and SRAM, FPGA and SRAM；

Described optical interface module includes that serioparallel exchange unit and photoelectric conversion unit, serioparallel exchange unit and photoelectric conversion unit connect.

And, the clock signal of described clock module output includes 50M clock and 122.88M clock；Wherein, 50M clock is provided by crystal oscillator chip, 122.88M clock is provided by clock chip, and 122.88M clock that clock chip recovers in up test process with serioparallel exchange unit or 10M clock are as reference clock, and 10M clock provides for external offer or by crystal oscillator chip.

And, the cpu chip of described processor module is realized by POWER PC；Described memory element includes FPGA and SDRAM.

The analog BBU that the present invention further correspondingly provides for LTE RRU tests system, including analog BBU test device, tested RRU, computer, spectrum analyzer and signal source, computer is connected by RS232 Serial Port Line and netting twine with analog BBU test device, analog BBU test device is connected by optical fiber with tested RRU, and tested RRU is connected by radio frequency testing line respectively with spectrum analyzer, signal source.

The present invention further correspondingly provides the analog BBU method of testing for LTE RRU, by light mouth speed and the I/Q data source file of allocation of computer analog BBU test device, tested RRU is tested under multiple types and various bandwidth, described multiple types includes TDD-LTE and FDD-LTE, described various bandwidth includes that 5M, 10M, 15M, 20M and 40M, described test include descending test process and up test process.

And, being achieved in that of configuration I/Q data source file, I/Q data source file is stored in the FLASH of processor module, starts to be loaded in the SRAM in logic module during descending test process.

And, descending test process implementation is as follows,

In analog BBU test device, cpu chip produces according to the configuration-direct of system requirements and computer and controls management information, and by FPGA, I/Q data source file is loaded in SRAM, FPGA is loaded into I/Q data source file from SRAM, I/Q data in I/Q data source file is encoded with controlling management information, it is sent to optical interface module with the form of parallel data, serioparallel exchange unit in optical interface module converts parallel data into serial data and is sent to photoelectric conversion unit, by photoelectric conversion unit, serial data is converted to optical signal from the signal of telecommunication, tested RRU is given by luminous signal under optical fiber；The down going channel index of tested RRU analyzed by spectrum analyzer.

And, up test process implementation is as follows,

The signal that signal source produces is after tested RRU inter-process, and gained base band data is uploaded to analog BBU test device by optical signal by tested RRU；In analog BBU test device, photoelectric conversion unit converts optical signals to the signal of telecommunication and is sent to serioparallel exchange unit, by serioparallel exchange unit, the signal of telecommunication of serial data form is converted to parallel data again, the base band data of parallel data form is demodulated obtaining I/Q data and controlling management information by FPGA, and output processes to processor module, processor module carries out respective handling to controlling management information, and I/Q data is sent to computer；At computer, the I/Q data received is analyzed.

The present invention has highly versatile, framework realizes simple, resource is few, the advantage of low cost, can be not by true BBU, under conditions of in order to coordinate the original function testing additional modifications RRU to be measured, basic RRU test environment is provided, fully meets every test job of the performance indications to RRU and stability.

Accompanying drawing explanation

Fig. 1 be the RRU automatization stability test device of the embodiment of the present invention realize block diagram.

Fig. 2 is the system clock block diagram of the embodiment of the present invention.

Fig. 3 is that the RRU of the embodiment of the present invention tests block diagram.

Detailed description of the invention

The invention will be further described with embodiment below in conjunction with the accompanying drawings.

Refer to as it is shown in figure 1, the embodiment of the present invention provides the analog BBU test device for the test of LTE radio extension unit to be made up of following part: processor module, logic module, optical interface module, clock module.As it is shown in figure 1, processor module, logic module, optical interface module are electrically connected with successively, it is mainly used in transmitting up-downgoing data.In each module, unit can use existing chip and circuit realiration in prior art, for the sake of ease of implementation, it is provided that be described as follows:

Described processor module is with CPU as core, including the interface circuit of cpu chip, CPLD, memory element and cpu chip electric connection.Described memory element includes FLASH and SDRAM chip, for accepting the operation of CPU, stores data；The data being stored in FLASH include system program, CPLD code, FPGA code, I/Q data source and other log informations, and these part data load after system start-up；SDRAM is for storing ephemeral data in equipment work process.Cpu chip is the core of processor module, can realize with POWER PC, use Vxworks operating system, be used for configuration and the monitoring of each business chip, produces and interactive controlling, management information, the upgrading of management software version, generates and manage journal file；And realize the access to external memory storage (FLASH and SDRAM), the function that completion system self-starting, program load by local data bus and address bus.The CPU of embodiment uses MPC852T chip, also can be selected other processor chips by those skilled in the art when being embodied as.CPLD is for the interface of extension CPU, when being embodied as, CPU can realize the configuration of each business chip (FPGA, clock chip, serioparallel exchange chip, various interface chips etc.) and monitoring and system reset function by CPLD, it is possible to by transmission link and interface circuit respectively with RRU and computer interactive controlling, management information.Described interface circuit includes Ethernet interface and RS-232 interface, is used for and outer computer interactive information.By interactive information, outer computer comprises the steps that 1 to the operation of analog BBU test device, software (generally comprising system program, CPLD code, FPGA code, I/Q data source) is upgraded and updated；2, configuration-direct is sent to analog BBU test device, including the relevant parameter of configuration analog BBU test device, such as light mouth speed, clock reference 3, the running status of reading analog BBU test device.

Described logic module is for completing IQ(orthogonal modulation according to IR agreement) data and control framing and the demodulation of management information (C&M data).Logic module includes that FPGA and plug-in SRAM, i.e. FPGA and SRAM connect.I/Q data source file is loaded in the plug-in SRAM of FPGA by CPU by FPGA, and FPGA extracts I/Q data again from SRAM and carries out framing with controlling management information.

Described optical interface module has been used for serial/parallel conversion and the opto-electronic conversion of signal.The optical interface module of embodiment includes that serioparallel exchange unit (SERDES) and photoelectric conversion unit (OPT), serioparallel exchange unit and photoelectric conversion unit connect.Serioparallel exchange unit completes the conversion of serial data and parallel data, by serial data, the downstream signal from logic module is converted into parallel data, is sent to photoelectric conversion unit；The upstream data inputted from photoelectric conversion unit is converted to parallel data by serial data simultaneously, is sent to logic module.SERDES has multiple-working mode, can configure light mouth speed by the mode of operation of change SERDES.It supports that 3 kinds of low speed are to the mode of operation of high-speed serial data, the mode of operation of respectively 1:1, the mode of operation of 2:1, the mode of operation of 4:1.The photoelectric conversion unit of optical interface module completes photosignal and converts, it is provided that light mouth speed support 10G, simultaneously can the light mouth speed of backward compatible 2.5G and 5G, thus support the RRU of different systems and bandwidth.The optical signal interface of photoelectric conversion unit connects external fiber, and electric signal interface connects serioparallel exchange unit.Optical signal interface (light mouth) can comprise two SFP+(optoelectronic transceiver modules) interface, respectively main light port and from Guang Kou.Main light port is used for connecting subordinate RRU, from light mouth for supporting the multiple cascade system of RRU.

Described clock module is respectively other modules and provides work clock.As in figure 2 it is shown, described clock module comprises two parts, a portion is designated as clock unit 1, provides the synchronised clock of 122.88M to the serioparallel exchange unit in the FPGA in logic module and optical interface module, is mainly realized by clock chip；Another part is designated as clock unit 2, there is provided 50M system clock to the FPGA in the processor chips in processor module, CPLD and logic module, produced by the 50M crystal oscillator on plate, it is input to CPU, then is exported by CPU and pass through a CLOCK BUFFER(clock buffer) it is separately input to CPLD and FPGA.Clock unit 1 has two kinds of working methods, and one is that the 122.88M clock recovered from upward signal using serioparallel exchange unit (SERDES) works as reference clock, generation clock for FPGA and the optical interface module of logic module；Another way is as reference clock, 10M reference signal using 10M signal can to select the 10M crystal oscillator on use equipment by toggle switch or access outside 10M signal by Sub-miniature B.Clock unit 1 and clock unit 2 provide clock to FPGA respectively, realize respective function respectively.

When being embodied as, processor module, logic module, optical interface intermodule specifically connect realization, can by CPLD connect FPGA, FPGA connect SERDES.

nullRefer to shown in Fig. 3，The embodiment of the present invention provides the one analog BBU system that LTE radio extension unit (the most tested RRU) is tested by test device，Device is tested including analog BBU、Tested RRU、Computer、Spectrum analyzer and signal source，Computer (typically using PC) is connected by RS232 Serial Port Line and netting twine with analog BBU test device，Analog BBU test device is connected by optical fiber with LTE radio extension unit，Tested Remote Radio Unit and spectrum analyzer、Signal source is connected by radio frequency testing line respectively，Connect the Sub-miniature B (a kind of radio frequency connector) on analog BBU by the 10M_REF_OUT mouth of spectrum analyzer simultaneously，The outside 10M signal of input is to clock unit 1，The reference clock of 10M is provided to analog BBU test device.

Described computer passes through RS232 interface and Ethernet interface, the light mouth speed of configuration analog BBU test device and working method.Mode of operation can be selected to be TD-LTE or FDD-LTE according to the testing requirement of the object RRU of test, and the data source selecting downgoing baseband data to be single carrier or multicarrier.After system start-up, analog BBU test device completes to initialize and parameter configuration, receives PC configuration-direct and is handed down to tested RRU, receives the interactive information that RRU uploads simultaneously.Complete community set up and monitor connection status.

When being embodied as, by configuring light mouth speed and the I/Q data source file of analog BBU test device, the analog BBU test device of the present invention is applicable to multiple types and includes that TDD-LTE and FDD-LTE and various bandwidth include that the LTE-RRU of 5M, 10M, 15M, 20M, 40M tests.Described I/Q data source file is by the I/Q data finished in advance according to LTE protocol, the source that the RRU device of corresponding different systems and bandwidth is used also differs, can be inputted previously according to needs by those skilled in the art, I/Q data source file is by computer programming storage device in processor module.After system start-up, I/Q data source file is loaded in the plug-in SRAM of FPGA by CPU by FPGA, and FPGA extracts I/Q data again from SRAM and carries out framing with controlling management information.Control management information (C&M) to be produced according to the demand of system and the configuration-direct of PC by CPU, be implemented as prior art.

Test process described further below.

Descending test process: in analog BBU test device, CPU produces according to the configuration-direct of system requirements and PC and controls management information, and I/Q data source file is loaded in the plug-in SRAM of FPGA by CPU by FPGA simultaneously；FPGA is loaded into I/Q data source file from plug-in SRAM, the I/Q data in I/Q data source file is encoded with controlling management information, is sent to optical interface module with the form of parallel data.In optical interface module, serioparallel exchange unit converts parallel data into serial data and is sent to photoelectric conversion unit, by photoelectric conversion unit, from the signal of telecommunication, serial data is converted to optical signal, gives tested RRU by luminous signal under optical fiber.Radio frequency interface at tested RRU connects spectrum analyzer, can analyze the down going channel index of tested RRU.

Up test process: up for RRU input radio frequency interface is connect signal generator (signal source), the signal that signal source produces is after tested RRU inter-process, gained base band data is uploaded to analog BBU test device by optical signal by optical interface by tested RRU, and the base band data that tested RRU obtains has comprised I/Q data and the control management information of the other end from communication.In analog BBU test device, photoelectric conversion unit converts optical signals to the signal of telecommunication and is sent to serioparallel exchange unit, by serioparallel exchange unit, the signal of telecommunication of serial data form being converted to parallel data again, now the clock chip of serioparallel exchange unit can obtain the light mouth recovered clock of 122.88M from serioparallel exchange unit.The base band data of parallel data form is demodulated obtaining I/Q data and controlling management information by FPGA, and output processes to processor module.Processor module carries out respective handling to controlling management information, and by Ethernet interface, I/Q data is sent to computer processes.The I/Q data received can be analyzed at computer, so can test the data feedback channel of RRU.

In test process, the 10M signal that analog BBU test device provides with audiofrequency spectrometer, as reference signal, is synchronized by clock unit, is distributed to other chips, it is achieved synchronization.

Meanwhile, the analog BBU test device of the present invention can also support the test of the multiple networking modes such as the single-point of RRU, star, chain, annular.

Specific embodiment described herein is only to present invention spirit explanation for example.Described specific embodiment can be made various amendment or supplements or use similar mode to substitute by those skilled in the art, but without departing from the spirit of the present invention or surmount scope defined in appended claims.

Claims (7)

1., for an analog BBU test device of LTE RRU, described BBU is base station processing unit, and described RRU is radio frequency Extension unit, it is characterised in that: include processor module, logic module, optical interface module and clock module, processor module, Logic module, optical interface module are electrically connected with successively, and clock module is to logic module, optical interface module and processor module respectively Output clock signal；

Described processor module, including cpu chip and the CPLD, memory element and the interface circuit that are connected respectively with cpu chip； Described logic module, connects including FPGA and SRAM, FPGA and SRAM；

Described optical interface module includes that serioparallel exchange unit and photoelectric conversion unit, serioparallel exchange unit and photoelectric conversion unit connect；

The clock signal of described clock module output includes 50M clock and 122.88M clock；Wherein, 50M clock is by crystal oscillator chip Thering is provided, 122.88M clock is provided by clock chip, and clock chip was tested up with 10M clock or serioparallel exchange unit The 122.88M clock recovered in journey is reference clock, and 10M clock provides for external offer or by crystal oscillator chip；

Descending test process implementation is as follows,

In analog BBU test device, cpu chip produces, according to the configuration-direct of system requirements and computer, the management information that controls, and Being loaded in SRAM by I/Q data source file by FPGA, FPGA is loaded into I/Q data source file from SRAM, will I/Q data in I/Q data source file encodes with controlling management information, is sent to optical interface module, light with the form of parallel data Serioparallel exchange unit in interface module converts parallel data into serial data and is sent to photoelectric conversion unit, is turned by photoelectricity Change unit and serial data is converted to optical signal from the signal of telecommunication, give tested RRU by luminous signal under optical fiber；Spectrum analyzer divides Analyse the down going channel index of tested RRU；

Up test process implementation is as follows,

The signal that signal source produces is after tested RRU inter-process, and gained base band data is uploaded to by tested RRU by optical signal Analog BBU test device；In analog BBU test device, photoelectric conversion unit converts optical signals to the signal of telecommunication and is sent to Serioparallel exchange unit, then by serioparallel exchange unit, the signal of telecommunication of serial data form is converted to parallel data, FPGA will also The base band data of row data mode is demodulated obtaining I/Q data and controlling management information, and exports at processor module Reason, processor module carries out respective handling to controlling management information, and I/Q data is sent to computer；At computer to being connect The I/Q data received is analyzed.

The most according to claim 1 for the analog BBU test device of LTE RRU, it is characterised in that: described processor module Cpu chip realized by POWER PC；Described memory element includes FLASH and SDRAM.

Analog BBU for LTE RRU the most according to claim 1 or claim 2 tests the test system that device realizes, and its feature exists In: include analog BBU test device, tested RRU, computer, spectrum analyzer and signal source, computer and analog BBU Test device is connected by RS232 Serial Port Line and netting twine, and analog BBU test device is connected by optical fiber with tested RRU, quilt Survey RRU to be connected by radio frequency testing line respectively with spectrum analyzer, signal source.

The method of testing realized for the analog BBU test system of LTE RRU the most according to claim 3, it is characterised in that: By light mouth speed and the I/Q data source file of allocation of computer analog BBU test device, to tested RRU at multiple types Test with under various bandwidth, described multiple types include TDD-LTE and FDD-LTE, described various bandwidth include 5M, 10M, 15M, 20M and 40M, described test includes descending test process and up test process.

Method of testing the most according to claim 4, it is characterised in that: being achieved in that, by IQ number of configuration I/Q data source file It is stored in the FLASH of processor module according to source file, starts the SRAM being loaded in logic module during descending test process In.

Method of testing the most according to claim 5, it is characterised in that: descending test process implementation is as follows,

In analog BBU test device, cpu chip produces, according to the configuration-direct of system requirements and computer, the management information that controls, and Being loaded in SRAM by I/Q data source file by FPGA, FPGA is loaded into I/Q data source file from SRAM, will I/Q data in I/Q data source file encodes with controlling management information, is sent to optical interface module, light with the form of parallel data Serioparallel exchange unit in interface module converts parallel data into serial data and is sent to photoelectric conversion unit, is turned by photoelectricity Change unit and serial data is converted to optical signal from the signal of telecommunication, give tested RRU by luminous signal under optical fiber；Spectrum analyzer divides Analyse the down going channel index of tested RRU.

Method of testing the most according to claim 5, it is characterised in that: up test process implementation is as follows,

The signal that signal source produces is after tested RRU inter-process, and gained base band data is uploaded to by tested RRU by optical signal Analog BBU test device；In analog BBU test device, photoelectric conversion unit converts optical signals to the signal of telecommunication and is sent to Serioparallel exchange unit, then by serioparallel exchange unit, the signal of telecommunication of serial data form is converted to parallel data, FPGA will also The base band data of row data mode is demodulated obtaining I/Q data and controlling management information, and exports at processor module Reason, processor module carries out respective handling to controlling management information, and I/Q data is sent to computer；At computer to being connect The I/Q data received is analyzed.