CN103455649A - Method for detecting interference of spatial structures - Google Patents
Method for detecting interference of spatial structures Download PDFInfo
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- CN103455649A CN103455649A CN2012101829732A CN201210182973A CN103455649A CN 103455649 A CN103455649 A CN 103455649A CN 2012101829732 A CN2012101829732 A CN 2012101829732A CN 201210182973 A CN201210182973 A CN 201210182973A CN 103455649 A CN103455649 A CN 103455649A
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Abstract
The invention provides a method for detecting interference of spatial structures. The method includes steps setting a first limiting height for a circuit base board, and respectively setting a plurality of second limiting heights smaller than or equal to the first limiting height for a part of a plurality of coordinate areas in the circuit base board; creating Keep-out areas of the circuit base board according to the second limiting heights of the coordinate areas and the first limiting height; comparing heights corresponding to various coordinates in base board accommodating space to the Keep-out areas, and simulating and judging whether conflict can be caused or not when the circuit base board is accommodated in the base board accommodating space. The method has the advantage that by the aid of the method, whether the interference between the circuit base board and the base board accommodating space can occur or not and whether the spatial conflict between the circuit base board and the base board accommodating space can occur or not can be quickly detected by a user.
Description
Technical field
The invention relates to the interference judgment technology of a kind of space conflict, and particularly relevant for a kind of decision circuitry substrate and substrate, insert the interference checking method of the space structure between space.
Background technology
In recent years, along with advancing by leaps and bounds of electronics technology, make the electronic product of various difference in functionalitys constantly appear on market, and profoundly affect our work and daily life.With regard to small-sized electronic product, electronic product generally includes circuit substrate and casing.Circuit substrate is consisted of many electronic components and the circuit board that carries electronic component, and casing is the periphery that is coated on mainboard, in order to effectively to protect mainboard.
In manufacturing the process of electronic product, in order to ensure circuit substrate can accurately be placed in casing, the space conflict can not occur, may carry out a large amount of inspections to avoid conflict to space in circuit substrate and casing by the tester in early days.The tester (for example can utilize the 3-D view software for drawing now; AutoCAD); whereby one by one in the check circuit substrate each part whether can correctly be configured in casing in the finite space, be not impacted when inserting casing and can hold easily with the part in the holding circuit substrate.
When carrying out the check of above-mentioned space conflict, owing to being mostly to be formed by miniature parts in circuit substrate, the 3-D view software for drawing is the model parameter of these parts on the reading circuit substrate one by one, and utilizes the module parameter of these parts and the space in casing to compare one by one.For example, the 3-D view software for drawing can first read the module parameter of a certain part, obtains coordinate and height relationships in these module parameters, utilizes in above-mentioned relation and casing after space compares, and continues to read the model parameter of next part.In same circuit substrate, for example, although often possess same a plurality of parts (adopting resistance, the electric capacity of same size), the 3-D view software for drawing only can read corresponding part one by one, thereby need to exhaust a large amount of time.
Summary of the invention
The present invention proposes a kind of interference checking method of space structure, the coordinates regional that it is first divided by electronic component and maximum height limit thereof are set up a height-limit area structure, and the substrate that utilizes this height-limit area structure and circuit substrate inserts space and compare, check and whether interfere and the space conflict whereby.
The present invention proposes a kind of interference checking method of space structure, comprises the following steps.Obtain circuit substrate, wherein circuit substrate has been set with the first maximum height limit, and in circuit substrate, a plurality of coordinates regionals of part are set respectively a plurality of the second maximum height limits, and wherein the second maximum height limit is less than or equal to the first maximum height limit.The second maximum height limit and the height-limit area structure (Keep-out area) of the first maximum height limit to set up circuit substrate according to coordinates regional.Insert the corresponding height of each coordinate in space according to height-limit area structure alignment substrate, whether simulation decision circuitry substrate cause conflict when being placed in substrate and inserting space.
In one embodiment of this invention, above-mentioned height-limit area structure comprises a plurality of height limiting zones, each coordinates regional in each height limiting zone corresponding circuits substrate wherein, and, according to the second maximum height limit and first maximum height limit of coordinates regional, with the height-limit area structure of setting up circuit substrate, comprise the following steps: in the decision circuitry substrate, whether each coordinates regional has each corresponding second maximum height limit.When the second corresponding maximum height limit has been set in the coordinates of targets zone, each height limiting zone corresponding with the coordinates of targets zone is set as to the second maximum height limit.When the second corresponding maximum height limit is not set in the coordinates of targets zone, each height limiting zone corresponding with the coordinates of targets zone is set as to the first maximum height limit.
In one embodiment of this invention, above-mentionedly insert the corresponding height of each coordinate in space according to height-limit area structure alignment substrate and comprise the following steps: sequentially to judge the setting height of each height limiting zone in the height-limit area structure and the height that substrate is inserted space institute respective coordinates.
In one embodiment of this invention, whether above-mentioned simulation decision circuitry substrate cause conflict to comprise the following steps: that inserting the corresponding height of each coordinate of space when substrate surpasses the corresponding height-limit area structure in coordinate district when being placed in substrate and inserting space, the judgement substrate is inserted space and is caused and conflict with circuit substrate, and the prompting error message.
In one embodiment of this invention, above-mentioned substrate is inserted space by a plurality of mechanism elements establishment generations
In one embodiment of this invention, above-mentioned interference checking method also comprises provides graphic interface to insert space to show height-limit area structure and substrate.
In one embodiment of this invention, above-mentioned interference checking method also comprises that the first specifications list according to circuit substrate is to obtain corresponding the second maximum height limit of the first maximum height limit and coordinates regional.
In one embodiment of this invention, above-mentioned interference checking method also comprises that second specifications list of according to substrate, inserting space inserts the coordinates regional in space to obtain substrate.
Based on above-mentioned, according to the first maximum height limit and a plurality of second maximum height limit of circuit substrate, can set up the height-limit area structure of circuit substrate.In addition, compare the substrate of a space structure according to the height-limit area structure and insert the corresponding height of each coordinate in space, can simulate with the decision circuitry substrate and whether cause and conflict when being placed in substrate and inserting space.Thus, the coordinates regional that the present embodiment is divided by electronic component and maximum height limit thereof are set up a height-limit area structure, and the substrate that utilizes this height-limit area structure and circuit substrate inserts space and compare, whether check circuit substrate and substrate are inserted and are interfered between space and conflict in space whereby.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
The accompanying drawing explanation
Fig. 1 is the calcspar of the shown electronic installation of one embodiment of the invention;
Fig. 2 is the side diagrammatic cross-section of the shown circuit substrate of one embodiment of the invention; Fig. 3 is the side diagrammatic cross-section that the shown substrate of one embodiment of the invention is inserted space;
Fig. 4 is the interference checking method flow diagram of the shown space structure of one embodiment of the invention;
Fig. 5 is the schematic diagram of the shown interference checking of one embodiment of the invention;
Fig. 6 is the shown method flow diagram of setting up the height-limit area structure of one embodiment of the invention;
Fig. 7 is the schematic diagram of the shown interference checking method of one embodiment of the invention.
Description of reference numerals: 100: electronic installation;
111: processing unit;
113: storage unit;
115: display unit;
117: the electronic component database;
119: the mechanism element database;
230: circuit substrate;
231～239,341～349,251～259,741～749: coordinates regional;
22,24,26,28,41～49: area of space;
51～59: height limiting zone;
250: the height-limit area structure;
340,740: substrate is inserted space;
532,533: the coordinates of targets zone;
H1, H22, H24, H26, H28, H41～H49, H71, H73, H75, H77, H78: highly;
S401～S403: each step of interference checking method of space structure;
S601～S603: each step of method of setting up the height-limit area structure.
Embodiment
The method of the interference checking of the present embodiment can realize by software, and at relevant electronic installation (for example carry out, computer, server) in, wherein a circuit substrate be simulated and be judged to hardware unit can (for example, mainboard) for example be placed in, when a substrate is inserted space (, the space in casing) whether cause conflict.Yet those skilled in the art can adopt the implementations such as firmware program or hardware configuration in part embodiment, carry out whereby the interference checking method of the described space structure of this case, be not limited to above-mentioned software and realize.In order to make content of the present invention more clear, below the example that really can implement according to this as the present invention especially exemplified by embodiment.
Fig. 1 is the calcspar of the shown electronic installation 100 of one embodiment of the invention.The method of the interference checking of the present embodiment can be executed in electronic installation 100.Electronic installation 100 is for example light weight user side (Thin Client; TC), server, PC, notebook computer, personal digital assistant (personal digital assistant, PDA) etc., be not limited to above-mentioned.
Processing unit 111 is for example central processing unit (Central Processing Unit, CPU), and it can control the overall operation of electronic installation 100, and realizes the interference checking method of the present embodiment.Display unit 115 is for example computer screen.Display unit 115 can pass through computer graphics software (Computer-aided design; CAD) provide the graphic interface (not shown), and processing unit 111 can be presented in graphic interface the result after interference checking.
Say further, but said memory cells 113 store electrons components databases 117 and mechanism element database 119.Electronic component database 117 comprises the data such as correlation space model that numerous electronic components (for example, electric capacity, resistance, chip) are pre-set and parameter thereof, for example the solid space model of various electronic components; Highly, the related datas such as width, length, connecting point position and quantity.The designer of design circuit substrate (example, mainboard) can select to set up the required material of mainboard by electronic component database 117, designs whereby the space structure information of circuit substrate.
119 of mechanism element databases (for example comprise numerous mechanism elements, the required associated mechanisms part in order to the construction casing) data such as pre-set correlation space model and parameter thereof, the designer of design casing also can select to set up the required materials and parts of casing by mechanism element database 119, designs whereby the structural information that the substrate that need to insert circuit substrate is inserted space.
In the present embodiment, the space structure information of circuit substrate can comprise a plurality of coordinates regionals of circuit substrate, and wherein each coordinates regional can be corresponding to one or more mechanism elements.The electronic component database 117 of the present embodiment the first maximum height limit that also but the memory circuit substrate has been set (namely, the default maximum height of circuit substrate integral body), and a plurality of the second maximum height limits that simultaneously coordinates regional of part is set respectively in the memory circuit substrate (namely, the relative maximum height that the part coordinates regional can be used), wherein the second maximum height limit is less than or equal to the first maximum height limit.The whole height that above-mentioned the first maximum height limit (the default maximum height of circuit substrate integral body) can be inserted space with reference to previous experiences or substrate by the designer is set.Yet, due to the space in the part casing can furnish peculiar part (for example furnish hard disk, CD-ROM drive ... etc.) will cause the part coordinates regional of circuit substrate can't reach above-mentioned default maximum height, therefore need set its second maximum height limit to the coordinates regional of part in circuit substrate respectively.
For instance, processing unit 111 can be obtained the first maximum height limit of circuit substrate from the specifications list of circuit substrate, and corresponding a plurality of second maximum height limits of coordinates regional of part, and is stored in the electronic component database 117 in storage unit 113.In addition, processing unit 111 can be according to the space structure information of foregoing circuit substrate, the graphic interface display circuit substrate in display unit 115.
Fig. 2 is the space structure side diagrammatic cross-section of the shown circuit substrate of one embodiment of the invention.Please refer to Fig. 2, circuit substrate 230 comprises coordinates regional 231～239, and wherein, coordinates regional 232,234,236 and 238 corresponds respectively to the shared area of space 22,24,26 and 28 of a plurality of mechanism elements in circuit substrate 230.For instance, if be configured to electric capacity in coordinates regional 232, area of space 22 means the space that electric capacity occupies.Circuit substrate 230 has been set the first maximum height limit H1, and the coordinates regional 232,234,236 and 238 of part in circuit substrate 230, set respectively the second maximum height limit H22, H24, H26 and H28, wherein the second maximum height limit H22, H24, H26 and H28 can be less than or equal to the first maximum height limit H1.In the present embodiment, the first maximum height limit H1 is set as the maximum height of circuit substrate 230, is also corresponding the second maximum height limit H28 of coordinates regional 238.Certainly, in other embodiments, the first maximum height limit H1 can be the height that the user sets.In addition, processing unit 111 can be from the specifications list of circuit substrate 230, obtain the first maximum height limit H1 of circuit substrate 230, and corresponding the second maximum height limit H22 of coordinates regional 232,234,236 and 238, H24, H26 and the H28 of part, and be stored in electronic component database 117.
Thus, processing unit 111 can be obtained the space structure information that circuit substrate 230 and substrate are inserted space 340 from electronic component database 117 and mechanism element database 119, and whether check circuit substrate 230 is inserted space 340 with substrate and caused and conflict on space structure.It is below the interference checking method of the above-mentioned electronic installation 100 prescribed space structures of collocation.Fig. 4 is the interference checking method flow diagram of the shown space structure of one embodiment of the invention.
Referring to Fig. 1, Fig. 2 and Fig. 4, at step S401, processing unit 111 can be obtained from electronic component database 117 the space structure information of circuit substrate 230, wherein space structure information comprises the first maximum height limit H1 of circuit substrate 230, and in circuit substrate 230 part corresponding the second maximum height limit H22 of a plurality of coordinates regionals 232,234,236 and 238, H24, H26 and H28.Below describe step S401 in detail with Fig. 2 and Fig. 5.
Fig. 5 is the schematic diagram of the shown interference checking of one embodiment of the invention.Please according to Fig. 4 and simultaneously with reference to Fig. 2 and Fig. 5, at step S403, processing unit 111 can, according to corresponding the second maximum height limit H22, H24, H26 and H28 and the first maximum height limit H1 in a plurality of coordinates regionals 231～239, be set up the height-limit area structure (Keep-out area) 250 of circuit substrate 230.In Fig. 5, height-limit area structure 250 comprises a plurality of height limiting zones 51～59, and height limiting zone 51～59 coordinates regional 251～259 separately, the coordinates regional 231～239 in corresponding circuits substrate 230 respectively.The detailed process of setting up height-limit area structure (Keep-out area) 250 of following description of step S403.
Fig. 6 is the shown method flow diagram of setting up the height-limit area structure of one embodiment of the invention, the namely detail flowchart of the step S403 of Fig. 4.At step S601, the processing unit 111 of Fig. 1 can judge whether each coordinates regional 231～239 in Fig. 2 circuit substrate 230 has the second corresponding maximum height limit.For instance, processing unit 111 can be judged in coordinates regional 232,234,236 and 238, there is the second maximum height limit H22, H24, H26 and the H28 that have set, and processing unit 111 can be judged in coordinates regional 231,233,235,237 and 239, do not there is the second corresponding maximum height limit.
At this, the coordinates regional that processing unit 111 judges is called the coordinates of targets zone.Say further, at step S603, when the second corresponding maximum height limit has been set in the coordinates of targets zone that processing unit 111 judges, the setting height of the height-limit area structure 250 that processing unit 111 can be corresponding by the coordinates of targets zone, be set as the second corresponding maximum height limit.Yet, when the second corresponding maximum height limit is not set in the coordinates of targets zone, at step S605, the setting height of the height-limit area structure 250 that processing unit 111 can be corresponding by the coordinates of targets zone, be set as the first maximum height limit H1.
Particularly, in Fig. 5, when processing unit 111 judgement coordinates of targets zone 532, can, by the setting height of corresponding height limiting zone 52, be set as the second maximum height limit H22.When processing unit 111 judgement coordinates of targets zone 533, because the second maximum height limit is not set in coordinates of targets zone 533, therefore, processing unit 111, by the setting height of the height limiting zone 53 of coordinates of targets zone 533 correspondences, is set as the first maximum height limit H1.And about remaining height limiting zone 51,54～59 corresponding setting height, can the rest may be inferred, repeat no more.
Get back to step S405 and referring to Fig. 3 and Fig. 5, processing unit 111 can be compared substrate according to height-limit area structure 250 and insert the corresponding height H 41～H49 of each coordinates regional 341～349 in space 340, whether simulation decision circuitry substrate 230, when being placed in substrate and inserting space 340, cause conflict.In Fig. 3 and Fig. 5, the substrate of Fig. 3 is inserted the coordinates regional 251～259 that coordinates regional 341～349 in space 340 corresponds respectively to the height-limit area structure 250 of Fig. 5.At this, the interference checking order that processing unit 111 can set according to the user, the inspection substrate is inserted the corresponding height H 41～H49 of each coordinates regional 341～349 in space 340, the setting height separately lower than height limiting zone 51～59 whether, yet, if height H 41～H49 wherein one lower than height limiting zone 51～59 setting height separately, processing unit 111 will decision circuitry substrate 230 be inserted space 340 with substrate the generation that conflicts.For instance, as shown in Fig. 3 and Fig. 5, due to coordinates regional 341～349 height H 41～H49 separately, it is all setting height separately higher than height limiting zone 51～59, therefore, processing unit 111 judgement height-limit area structures 250 and substrate are inserted the generation that conflicts of space 340 nothings, and circuit substrate 230 can not cause conflict inserting when substrate is inserted space 340.
Fig. 7 is the schematic diagram of the shown interference checking method of one embodiment of the invention.Please refer to Fig. 7 and Fig. 5, substrate is inserted the coordinates regional 251～259 that coordinates regional 741～749 in space 740 (being represented by dotted lines) corresponds respectively to height-limit area structure 250 (meaning with solid line).In Fig. 7, because the corresponding height H 71 of coordinates regional 741,743,745,747 and 748, H73, H75, H77 and H78 are lower than the corresponding setting height of height-limit area structure 250, therefore, processing unit 111 decision circuitry substrates 230 have caused conflict when being placed in substrate and inserting space 740.
In addition, display unit 115 also can be inserted space 740 and height-limit area structure 250 at the graphic interface display base plate, therefore insert space 740 and the corresponding height-limit area structure 250 of circuit substrate 230 when substrate and cause while conflicting, the user can be convenient to be checked in graphic interface.And, insert space 740 and circuit substrate 230 when processing unit 111 judgement substrates and caused while conflicting, can point out an error message in display unit 115.Thus, for arbitrary substrate is inserted space, processing unit 111 can be in graphic interface analog baseplate insert the configuration of space 740 and height-limit area structure 250, and can judge that substrate inserts space and whether with height-limit area structure 250, cause and conflict.
In sum, the interference checking method of space structure of the present invention, electronic installation can, according to the first maximum height limit and a plurality of second maximum height limit of circuit substrate, be set up the height-limit area structure of circuit substrate.Wherein, if the coordinates of targets zone of circuit substrate has the second maximum height limit, the setting height of the corresponding height-limit area structure in coordinates of targets district is the second maximum height limit, and if the coordinates of targets district of circuit substrate does not have the second maximum height limit, the height of the corresponding height-limit area structure in coordinates of targets district is the second maximum height limit.In addition, electronic installation can be inserted the corresponding height of each coordinate in space according to height-limit area structure alignment one substrate, and can judge that whether the height-limit area structure insert space with substrate and cause and conflict.In addition, insert space when height-limit area structure and substrate and cause while conflicting, electronic installation can be pointed out an error message.
Thus, the space structure of wanting to carry out circuit substrate (being for example mainboard) as the user and substrate insert space interference, conflict while checking, coordinates regional and the maximum height limit thereof that can divide by the electronic component of circuit substrate, set up a height-limit area structure, and utilize the substrate of this height-limit area structure and circuit substrate to insert space to compare.Whereby, can check and whether interfere and the space conflict.
Finally it should be noted that: above each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to aforementioned each embodiment, the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: its technical scheme that still can put down in writing aforementioned each embodiment is modified, or some or all of technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the scope of various embodiments of the present invention technical scheme.
Claims (8)
1. the interference checking method of a space structure, is characterized in that, comprising:
Obtain a circuit substrate, wherein this circuit substrate has been set with one first maximum height limit, and in this circuit substrate, a plurality of coordinates regionals of part are set respectively a plurality of the second maximum height limits, and wherein those second maximum height limits are less than or equal to this first maximum height limit;
According to those second maximum height limits of those coordinates regionals and this first maximum height limit to set up a height-limit area structure of this circuit substrate;
Insert the corresponding height of each coordinate in space according to this height-limit area structure alignment one substrate, simulate and judge this circuit substrate is being placed in when this substrate is inserted space whether cause conflict.
2. the interference checking method of space structure according to claim 1, is characterized in that, this height-limit area structure comprises a plurality of height limiting zones, and respectively this height limiting zone is to respectively this coordinates regional in should circuit substrate, and,
Those second maximum height limits and this first maximum height limit according to those coordinates regionals comprise the following steps: with this height-limit area structure of setting up this circuit substrate
Judge in this circuit substrate respectively whether this coordinates regional has corresponding respectively this second maximum height limit;
When this corresponding second maximum height limit has been set in a coordinates of targets zone, respectively this height limiting zone corresponding with this coordinates of targets zone is set as to this second maximum height limit; And
When this corresponding second maximum height limit is not set in a coordinates of targets zone, respectively this height limiting zone corresponding with this coordinates of targets zone is set as to this first maximum height limit.
3. the interference checking method of space structure according to claim 1, is characterized in that, inserts the corresponding height of each coordinate in space according to this this substrate of height-limit area structure alignment and comprise the following steps:
Sequentially judge in this height-limit area structure the height that the setting height of this height limiting zone respectively and this substrate are inserted space institute respective coordinates.
4. the interference checking method of space structure according to claim 1, is characterized in that, simulate and judge this circuit substrate be placed in when this substrate is inserted space whether causing the conflict comprise the following steps:
When this substrate is inserted, in space, respectively this coordinate is corresponding lower than corresponding this height-limit area structure in this coordinate district, judges that this substrate inserts space and cause and conflict with this circuit substrate, and points out an error message.
5. the interference checking method of space structure according to claim 1, is characterized in that, this substrate is inserted space and produced by a plurality of mechanism elements establishments.
6. the interference checking method of space structure according to claim 1 also comprises:
Provide a graphic interface to insert space to show this height-limit area structure and this substrate.
7. the interference checking method of space structure according to claim 1, is characterized in that, also comprises:
According to one first specifications list of this circuit substrate to obtain corresponding those second maximum height limits of this first maximum height limit and those coordinates regionals.
8. the interference checking method of space structure according to claim 1, is characterized in that, also comprises:
Insert one second specifications list in space according to this substrate and insert those coordinates regionals in space to obtain this substrate.
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| CN2012101829732A CN103455649A (en) | 2012-06-05 | 2012-06-05 | Method for detecting interference of spatial structures |
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| CN2012101829732A CN103455649A (en) | 2012-06-05 | 2012-06-05 | Method for detecting interference of spatial structures |
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| CN104392043A (en) * | 2014-11-24 | 2015-03-04 | 英业达科技有限公司 | Programmable drawing system preventing interference of part and shell and method of programmable drawing system |
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Application publication date: 20131218 |