CN103440880A - SRAM (Static Random Access Memory) and bit cell tracking method - Google Patents
SRAM (Static Random Access Memory) and bit cell tracking method Download PDFInfo
- Publication number
- CN103440880A CN103440880A CN2013103930436A CN201310393043A CN103440880A CN 103440880 A CN103440880 A CN 103440880A CN 2013103930436 A CN2013103930436 A CN 2013103930436A CN 201310393043 A CN201310393043 A CN 201310393043A CN 103440880 A CN103440880 A CN 103440880A
- Authority
- CN
- China
- Prior art keywords
- sram
- tracking
- tracks
- dummy
- follow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses an SRAM (Static Random Access Memory) and a bit cell tracking method. The SRAM is characterized in that a memory circuit comprises SRAM arrays, two tracking rows, two tracking columns, two dummy cells, two dummy SAs (sensor amplifiers), tracking bit lines and tracking word lines, wherein each memory circuit comprises SRAM bit cells which are arranged into rows and columns; the two tracking rows are respectively arranged on the upper parts of the two SRAM arrays; the two tracking columns are respectively arranged on two sides of the SRAM arrays; the two dummy cells are used for starting tracking bit line signals; the tracking bit lines penetrate through the tracking columns and are connected with dummy SAs; the tracking word lines penetrate through the tracking rows and are connected with the dummy cells. According to the SRAM, two tracking paths are utilized, the delay times of the two tracking paths are compared, and the larger delay time is utilized for controlling the sensor amplifier corresponding to a normal memory unit to be turned on. Thus, the SRAM has the main advantages that conditions of left and right BLs (bit lines), wLs (word lines) and cells can be simultaneously tracked, and influences of the process fluctuation, the voltage and the temperature on the read operation of the SRAM are reduced.
Description
Technical field
The present invention relates to integrated circuit fields, be specifically related to a kind of SRAM storer and bit location method for tracing.
Background technology
In recent years, static RAM (SRAM) is because the advantage such as its speed is fast, system is simple has obtained application in a large number and widely.Sram cell is 6 transistor units normally, and this transistor unit has two connected phase inverters to form latch.As long as energy sustainable supply device is arranged, the phase inverter that lateral cross connects will maintain the data of storage always, and not need by being refreshed to keep data.
The SRAM storage unit has a word line, and two bit lines of single spin-echo.Two bit lines are connected on small-signal difference sensor amplifier.When SRAM carries out read operation, it is all that preliminary filling is high level that two bit lines start.When having word line voltage to rise to activation level, selected with the SRAM storage unit that this word line is connected, its transfer tube is activated, and bit line is connected with storage unit.Now, one of them bit line discharges, level starts to drop to low level, so it is poor that two bit lines just can produce a primary differential signal component voltage.Sensor amplifier can be determined rapidly the value on bit line and complete logic level output is provided.Because the differential electrical pressure reduction that can correctly be sensed on bit line is only by the hundreds of millivolt.Will the SRAM read cycle do not extend to by the lower bit line of the bit line pairs required All Time that discharges fully, so the SRAM read cycle can shorten.In addition, because not electric discharge fully, so reduced the loss of read operation power consumption.The above-mentioned time of reading changes along with the variation of SRAM technique, voltage, temperature.
Therefore, the SRAM array, all comprise that detection signal is transferred to the tracking circuit of the delay of array.Enough long in order to guarantee to read event horizon, guarantee the data on correct read memory, the sequential of storer control signal is adjusted in the delay detected by trace signals, can improve greatly performance and the security of SRAM.Traditional SRAM tracking scheme as shown in Figure 1, comprises the SRAM array, and a tracking clock generator is followed the tracks of row for one, and a dummy cell follows the tracks of row, a dummy sensor amplifier for one.Wherein dummy cell is a special storage unit, can store predefined logic state.Send an internal clock signal by following the tracks of the hour hands generator, to start through the trace word signal on the TWL that follows the tracks of row, the tracking line time postpones, while being transferred to dummy cell, started through the trace bit signal on the TBL that follows the tracks of row by dummy cell, follow the tracks of the row time delay, read by specific sensor amplifier dummy SA, and dummy SA sends a reset signal to following the tracks of generator all the time, mean that this read operation tracing process finishes.
Similar traditional tracking scheme, patent CN102637452A has proposed a kind of tracking scheme for storer, and discloses and have for reading the capable reservoir of tracking circuit.This circuit can postpone effectively to follow the tracks of to memory read operation, and this scheme can only be followed the tracks of for word line and the bit line of a side.Patent CN102800355A has proposed SRAM timing unit apparatus and method, this device comprises a plurality of word lines, each word line is connected with memory cell along a line wherein, in addition, contrary with the parallel tracking cell arranged in prior art, tracking cell in this scheme does not need to aim at bit line or is placed on the position corresponding with bit line, and can use the tracking cell of any amount, therefore, reach better susceptibility for overall process variable and local process variable, same problem, this scheme can only be followed the trail of bit line and the word line of a side.
In view of this, be necessary to propose a kind of improved SRAM and read tracking scheme, shorten read operation and postpone, make the SRAM reading speed sooner and don't lose correctness.
Summary of the invention
For deficiency of the prior art, the invention provides a kind of SRAM storer and bit location method for tracing, adopt two to follow the trail of path, to increase the accuracy of following the trail of operation.
At this, a kind of SRAM memory circuitry that reads tracking usage track circuit that has is provided, comprise several SRAM arrays symmetrical about INTERNAL-CLK.
For example, the memory circuit of SRAM storer can comprise two SRAM arrays, and each SRAM array comprises the SRAM bit location of embarking on journey with setting in column, symmetrical about INTERNAL-CLK; Follow the tracks of row, be placed in respectively two parts SRAM array top for two; Follow the tracks of row for two, be placed in respectively the both sides of SRAM array; Two dummy cell, be used for starting the tracking bit line signal; Two dummy SA sensor amplifiers; Follow the tracks of bit line, through following the tracks of row, be connected with dummy SA; The trace word line, through following the tracks of row, be connected with dummy cell.
This SRAM memory circuit can further comprise: follow the tracks of clock generator, the tracking clock signal is provided.Decision device, be connected with dummy SA, for giving, follows the tracks of clock generator feedback reset signal, and decision device can be realized with door with one simply.
At this, a kind of method of trace memory also is provided, comprising: follow the tracks of row along two respectively and send the tracking word-line signal; Set tracking data in dummy cell, by two dummy cell, receive and follow the tracks of word-line signal, in response to receiving, follow the tracks of word-line signal, to both sides, corresponding tracking row provide the tracking bit line signal respectively; The dummy SA sensor amplifier of both sides receives follows the tracks of bit line signal, in response to following the tracks of bit line signal, reads the tracking data of setting in dummy cell; Detect dummy SA1 and whether dummy SA2 all reads end by decision device, if finish, give and follow the tracks of a reset signal of clock generator feedback, finish the operation of this secondary tracking.Wherein, tracking data can be set to 1.
Beneficial effect: SRAM storer of the present invention and bit location method for tracing, adopt two to follow the trail of path, relatively two time delays of following the trail of path, get its larger sensor amplifier corresponding to common storage unit of controlling and close.Therefore, major advantage of the present invention is to follow the tracks of left and right BL simultaneously, wL, and the situation of cell, reduce the impact on the SRAM read operation of technological fluctuation, voltage, temperature.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of instructions, below with preferred embodiment of the present invention and coordinate accompanying drawing to be described in detail as follows.The specific embodiment of the present invention is provided in detail by following examples and accompanying drawing thereof.
The accompanying drawing explanation
For a more complete understanding of the present invention and advantage, below with reference to the description of doing below in conjunction with accompanying drawing, in the accompanying drawings:
Fig. 1 is traditional SRAM tracking circuit scheme schematic diagram.
Fig. 2 is the SRAM tracking circuit scheme schematic diagram of the embodiment of the present invention.
Fig. 3 illustrates the SRAM bit cell circuit of the SRAM array in Fig. 2.
Fig. 4 illustrates the waveform of the exemplary tracking scheme of the embodiment in Fig. 2.
Fig. 5 is the process flow diagram of embodiment in Fig. 2.
Embodiment
Below, discuss manufacture and the use of embodiment in detail.Yet, should be appreciated that, the disclosure provides many applicable inventive concepts that can realize in various specific environments.The specific embodiment of discussing only shows the concrete mode of manufacturing and using, and is not used in restriction the scope of the present disclosure.
Fig. 2 is the schematic diagram of the exemplary tracking scheme of embodiment.The SRAM array is divided into two parts, and these two parts take the INTERNAL-CLK line as axis of symmetry symmetrical, for example, the SRAM array that is 4M for memory space, being divided into memory space is all two parts SRAM array of 2M, and take INTERNAL-CLK as axis of symmetry symmetrical.The SRAM array has word line and the bit line be connected with bit location.Following the tracks of clock generator is connected with the TWL that follows the tracks of row through two.Two trace word line TWL are connected on dummy cell.Dummy cell is connected with dummy SA2 with specific sensor amplifier dummy SA1 by the tracking bit line TBL through following the tracks of row respectively again.Above-mentioned two sensor amplifiers are connected with same decision device, and decision device is connected with the tracking clock generator again.
Following the tracks of two sensor amplifier dummy SA1 and the dummy SA2 that row are corresponding in Fig. 2 is connected on a decision device.After these two sensor amplifiers all complete read operation, decision device can be exported a reset signal to following the tracks of clock generator, and in the present embodiment, this decision device can simply be realized with door with one.
Fig. 3 there is shown at circuit can be for the typical 6T SRAM bit location of embodiment.Can certainly use other SRAM determined bit position structure, 8T in addition commonly used.Fig. 3 has comprised that the phase inverter that pair of cross connects forms latch, that is, and and the CMOS phase inverter formed by PMOS transistor MP1 and nmos pass transistor MN3 respectively, and the CMOS phase inverter formed by PMOS transistor MP2 and nmos pass transistor MN4.Because these two phase inverter cross connections strengthen output, so, as long as there is energy to offer transistor, SRAM will not need to repeat to refresh to keep data.
Next, the function of the tracking scheme shown in Fig. 2 is described in conjunction with Fig. 4.Fig. 4 is the oscillogram of tracking scheme in Fig. 2.Follow the tracks of clock generator and produce internal clock signal INTERNAL-CLK, respectively along the activation TWL1 and the TWL2 that follow the tracks of row, to the SRAM array, capable delay is followed the tracks of.
After two dummy cell receive the trace word signal on TWL, along following the tracks of row, activate TBL1 and TBL2, postpone to follow the tracks of to being positioned at the every trade of advancing of following the tracks of the row both sides respectively.The dummy ce1l of both sides receives respectively the tracking word-line signal on TWLl and TWL2, response with receive word-line signal, dummy cell has activated respectively TBL1 and TBL2, being about to that TBL1 and TBL2 drag down is 0.The sensor amplifier dummy SA1 of both sides and dummy SA21 read and preset the particular logic value " 1 " be stored in dummy cell, the result of reading outputs to decision device, after two results of decision device reception all are " 1 ", will give and follow the tracks of a reset signal of clock generator transmission, front was mentioned, and decision device herein can realizing with door with one 2 input.Receive reset signal when following the tracks of clock generator, just mean that this read latency tracking has operated, and can read to follow the tracks of operation next time.
Fig. 5 is the process flow diagram of the tracking scheme in embodiment Fig. 2.
By the above, this programme adopts two to follow the trail of path, and then half of the height and width that every paths is the SRAM array compare two time delays of following the trail of paths, gets its larger sensor amplifier corresponding to common storage unit of controlling and close.Therefore, major advantage of the present invention is to follow the tracks of left and right BL simultaneously, WL, and the situation of cell, reduce the impact on the SRAM read operation of technological fluctuation, voltage, temperature.
The above; it is only better case study on implementation of the present invention; not the present invention is imposed any restrictions; every similar mode of any simple modification, change, employing that essence is done above embodiment according to the present invention substitutes and the variation of equivalent structure, all still belongs in the protection domain of technical solution of the present invention.
Claims (7)
1. a SRAM storer, is characterized in that, the memory circuit of described SRAM storer comprises several SRAM arrays symmetrical about INTERNAL-CLK.
2. SRAM storer according to claim 1 and bit location method for tracing, is characterized in that, the memory circuit of described SRAM storer comprises two SRAM arrays, and each SRAM array comprises the SRAM bit location of embarking on journey with setting in column.
3. SRAM storer according to claim 1, is characterized in that, also comprises that two are followed the tracks of row, are placed in respectively the top of SRAM array; Follow the tracks of row for two, be placed in respectively the both sides of SRAM array; Two dummy cell, be used for starting the tracking bit line signal; Two dummy SA sensor amplifiers; Follow the tracks of bit line, through following the tracks of row, be connected with dummy SA; The trace word line, through following the tracks of row, be connected with dummy cell.
4. according to the described SRAM storer of any one in claims 1 to 3, it is characterized in that, described SRAM memory circuit also comprises a tracking clock generator.
5. SRAM storer according to claim 4 and bit location method for tracing, is characterized in that, described SRAM memory circuit also comprises that one for the decision device to following the tracks of clock generator feedback reset signal, is connected with dummy SA.
6. SRAM storer according to claim 5 and bit location method for tracing, is characterized in that, described decision device is one and door.
7. the method for a trace memory, is characterized in that, on the basis of the SRAM storer of arranging in SRAM array, concrete tracking is: follow the tracks of row along two respectively and send the tracking word-line signal; Set tracking data in dummy cell, by two dummy cell, receive and follow the tracks of word-line signal, in response to receiving, follow the tracks of word-line signal, to both sides, corresponding tracking row provide the tracking bit line signal respectively; The dummy SA sensor amplifier of both sides receives follows the tracks of bit line signal, in response to following the tracks of bit line signal, reads the tracking data of setting in dummy cell; Detect dummy SA1 and whether dummy SA2 all reads end by decision device, if finish, give and follow the tracks of a reset signal of clock generator feedback, finish the operation of this secondary tracking.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013103930436A CN103440880A (en) | 2013-09-03 | 2013-09-03 | SRAM (Static Random Access Memory) and bit cell tracking method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013103930436A CN103440880A (en) | 2013-09-03 | 2013-09-03 | SRAM (Static Random Access Memory) and bit cell tracking method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103440880A true CN103440880A (en) | 2013-12-11 |
Family
ID=49694569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013103930436A Pending CN103440880A (en) | 2013-09-03 | 2013-09-03 | SRAM (Static Random Access Memory) and bit cell tracking method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103440880A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293323A (en) * | 2016-04-05 | 2017-10-24 | 中芯国际集成电路制造(上海)有限公司 | Write operation follows the trail of circuit and the memory of circuit is followed the trail of including write operation |
| CN108665923A (en) * | 2018-01-30 | 2018-10-16 | 苏州大学 | A kind of SRAM memory |
| CN110428861A (en) * | 2019-09-12 | 2019-11-08 | 上海明矽微电子有限公司 | A method of reducing eeprom memory area |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1444230A (en) * | 2002-03-13 | 2003-09-24 | 富士通株式会社 | Semiconductor storage device |
| CN1670861A (en) * | 2004-03-18 | 2005-09-21 | 富士通株式会社 | Semiconductor memory device and timing control method |
| CN1811985A (en) * | 2005-01-19 | 2006-08-02 | 尔必达存储器株式会社 | Memory device |
| US20060239094A1 (en) * | 2003-11-28 | 2006-10-26 | Fujitsu Limited | Semiconductor memory including self-timing circuit |
| US20100322022A1 (en) * | 2009-06-19 | 2010-12-23 | Renesas Electronics Corporation | Semiconductor storage device |
-
2013
- 2013-09-03 CN CN2013103930436A patent/CN103440880A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1444230A (en) * | 2002-03-13 | 2003-09-24 | 富士通株式会社 | Semiconductor storage device |
| US20060239094A1 (en) * | 2003-11-28 | 2006-10-26 | Fujitsu Limited | Semiconductor memory including self-timing circuit |
| CN1670861A (en) * | 2004-03-18 | 2005-09-21 | 富士通株式会社 | Semiconductor memory device and timing control method |
| CN1811985A (en) * | 2005-01-19 | 2006-08-02 | 尔必达存储器株式会社 | Memory device |
| US20100322022A1 (en) * | 2009-06-19 | 2010-12-23 | Renesas Electronics Corporation | Semiconductor storage device |
Non-Patent Citations (1)
| Title |
|---|
| 方海涛: "高速低功耗嵌入式SRAM的设计", 《中国优秀硕士学位论文全文数据库》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293323A (en) * | 2016-04-05 | 2017-10-24 | 中芯国际集成电路制造(上海)有限公司 | Write operation follows the trail of circuit and the memory of circuit is followed the trail of including write operation |
| CN107293323B (en) * | 2016-04-05 | 2020-04-10 | 中芯国际集成电路制造(上海)有限公司 | Write operation tracking circuit and memory including the same |
| CN108665923A (en) * | 2018-01-30 | 2018-10-16 | 苏州大学 | A kind of SRAM memory |
| CN108665923B (en) * | 2018-01-30 | 2021-11-23 | 苏州大学 | SRAM memory |
| CN110428861A (en) * | 2019-09-12 | 2019-11-08 | 上海明矽微电子有限公司 | A method of reducing eeprom memory area |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8164974B2 (en) | Memory circuits, systems, and method of interleaving accesses thereof | |
| US9142285B2 (en) | Multi-port SRAM with shared write bit-line architecture and selective read path for low power operation | |
| TWI466130B (en) | Semiconductor memories and bitcells tracking scheme | |
| CN103474093B (en) | Control following the trail of circuit and using the SRAM following the trail of circuit of sense amplifier unlatching | |
| US20140112062A1 (en) | Method and system for an adaptive negative-boost write assist circuit for memory architectures | |
| US8976614B2 (en) | Tracking scheme for memory | |
| CN110634515A (en) | Data processing apparatus | |
| US8477527B2 (en) | SRAM timing cell apparatus and methods | |
| US8953401B2 (en) | Memory device and method for driving memory array thereof | |
| US8824238B2 (en) | Memory device with bi-directional tracking of timing constraints | |
| CN106710625B (en) | Burst mode read controllable SRAM | |
| US20160099069A1 (en) | Program verify with multiple sensing | |
| CN103745743A (en) | SRAM (static random access memory) sense amplifier based on temperature compensation | |
| KR100905840B1 (en) | Determining optimal time instances to sense the output of a memory array | |
| CN104505117A (en) | Dynamic memory refreshing method and refreshing controller | |
| US10217508B2 (en) | SRAM and periphery specialized device sensors | |
| CN103456346A (en) | Memory and time sequence tracking method thereof | |
| CN108352175A (en) | Sensing amplifier in low-power high-performance SRAM | |
| CN103440880A (en) | SRAM (Static Random Access Memory) and bit cell tracking method | |
| US20160086657A1 (en) | Memory Tracking Scheme | |
| WO2016135500A1 (en) | Error detection circuitry for use with memory | |
| CN102171761B (en) | Timing processing method and circuit for synchronous static random accessible memory (SRAM) | |
| CN101814313B (en) | Single-tube single-capacitor type (1T1C) ferroelectric random access memory (FeRAM) | |
| CN108122570A (en) | Memory device with definite time window | |
| CN114944180B (en) | Weight-configurable pulse generating device based on copy column |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20131211 |