CN103440879B - Address change monitoring circuit, device and generation method thereof - Google Patents
Address change monitoring circuit, device and generation method thereof Download PDFInfo
- Publication number
- CN103440879B CN103440879B CN201310371648.5A CN201310371648A CN103440879B CN 103440879 B CN103440879 B CN 103440879B CN 201310371648 A CN201310371648 A CN 201310371648A CN 103440879 B CN103440879 B CN 103440879B
- Authority
- CN
- China
- Prior art keywords
- signal
- output
- output terminal
- logic
- address change
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000008859 change Effects 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000012544 monitoring process Methods 0.000 title abstract description 9
- 239000003990 capacitor Substances 0.000 claims description 7
- 230000000694 effects Effects 0.000 claims description 6
- 238000012806 monitoring device Methods 0.000 claims description 4
- 238000012360 testing method Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 36
- 238000010586 diagram Methods 0.000 description 16
- 230000006870 function Effects 0.000 description 9
- 230000008569 process Effects 0.000 description 8
- 238000004891 communication Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 238000004590 computer program Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000004422 calculation algorithm Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000003278 mimic effect Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
An address change monitoring circuit, apparatus and method are disclosed. The circuit includes: a zero clearing and delay unit receiving an input signal at a second input terminal and an inverted input signal at a first input terminal; the overturning unit is connected between the first output end and the second output end in series; and a judging unit outputting a timing signal based on a logical relationship between the signals on the first and second output terminals. According to the method of the embodiment, the address change monitoring circuits with different speeds can be generated, and the requirements of the storage circuits with different sizes are met.
Description
Technical field
This technology relates generally to the address change monitoring used in storage class integrated circuit, is specifically related to a kind of address change observation circuit, device and generates the method for this circuit.
Background technology
Need in a lot of integrated circuit to use memory circuit, such as static RAM or flash memory, for preserving the intermediate data needed for electronic system operation temporarily, or some record data of long-term preservation.Often be integrated with address change observation circuit in memory circuit, it generates the timing control signal that memory circuit carries out needed for read operation when memory address changes.
As shown in Figure 1, comprise by multiple address transfer monitoring (ATD) unit 101 and logical circuit 102 (logical OR circuit as shown in Figure 1) according to the address change observation circuit of prior art.Multiple input terminals 103 of address change observation circuit receive many address signal A [0] ..., A [N-1].The lead-out terminal 104 of address change observation circuit exports the timing control signal ATD that the read operation for memory circuit provides.Fig. 2 shows the circuit diagram of ATD unit as shown in Figure 1.
As shown in Figure 2, each ATD unit comprises the input terminal of reception input signal AIN and the lead-out terminal of output timing signal ATDU.In each ATD unit, the input signal after the delay units delay of multiple series connection and undelayed input signal AIN are input to the input end of OR-NOT circuit, at output terminal output timing signal ATDU.
Fig. 3 shows the input/output signal sequential chart of ATD unit as shown in Figure 2.As shown in Figure 3, when the address signal inputted produces logic change, such as, when becoming " 1 " from logical zero, the output terminal of ATD unit can produce high level interval, and it can the reading useful signal of time T needed for corresponding storage circuit read operation.
On the one hand, circuit as shown in Figure 2, owing to have employed the string of impact damper and capacitor and structure, cannot form new address change observation circuit by increasing or reduce some parts simply.Therefore, in prior art, the memory circuit for friction speed and sizes of memory all needs newly to design address change observation circuit.
On the other hand, take computerized algorithm as optimized integration, can memory circuit be generated, meet the different dimensional requirement of Integrated circuit designers for flash memory circuit.The address change observation circuit of usual needs engineer's one group of friction speed in advance, with the reading speed of corresponding different size memory circuit.But, in prior art, be difficult to the address change observation circuit being generated various friction speed (different T effective time) by automatic algorithms.
Summary of the invention
Consider one or more problem of the prior art, propose a kind of address change observation circuit, device and generation method thereof.
According to the embodiment of this technology, a kind of address change observation circuit, comprise: reset and delay cell, there is first input end and the second input end and the first output terminal and the second output terminal, receive input signal at described second input end and receive anti-phase input signal at first input end, roll-over unit, is connected in series between described first output terminal and described second output terminal, and judging unit, based on the logical relation between the signal on the signal on described first output terminal and described second output terminal, output timing signal, wherein, before the input signal of described second output changes into logic height from logic low, the signal of described first output is in logic low, it is high that the signal of described second output is in logic, the signal of the output of described judging unit is in logic low, when the signal of the second input end is changing into logic height from logic low, the signal of described second output is forced to become strong logic low, and the signal at described first input end place to become logic high, described clearing and delay cell is made to relieve control to described first output signal, the signal of described second output terminal and described first output is logic low, described judging unit is high at its output terminal output logic, start to make the read operation of memory circuit effective, described roll-over unit is being subject to the impact of the strong logic low that described second output produces, more weak upset logic is produced to described first output terminal, when described first output terminal becomes logic height by this effect, described judging unit passes through the logical relation judged between the signal of described first output terminal and described second output, low at its output output logic, terminate the read operation of memory circuit.
According to the embodiment of this technology, a kind of address change monitoring device, comprising:
The address change observation circuit of multiple parallel connection, each address change testing circuit is address change observation circuit as above;
Or circuit, receive the clock signal exported from described multiple address change observation circuit, export the timing control signal being used for memory read operations.
According to the embodiment of this technology, a kind of method utilizing Practical computer teaching address change observation circuit, comprise step: multiple clearing and delay cell that at least one or parallel connection are provided, each clearing and delay cell have the first and second input ends and the first and second output terminals, receive input signal at described second input end and receive anti-phase input signal at first input end, there is provided roll-over unit, described roll-over unit is connected in series between described first output terminal and described second output terminal, judging unit is provided, described judging unit based on the logical relation between the signal on the signal on described first output terminal and described second output terminal, output timing signal, there is provided or circuit, described or circuit receives the clock signal exported from multiple address change observation circuit, exports the timing control signal being used for memory read operations, wherein, before the input signal of described second output changes into logic height from logic low, the signal of described first output is in logic low, it is high that the signal of described second output is in logic, the signal of the output of described judging unit is in logic low, when the signal of the second input end is changing into logic height from logic low, the signal of described second output is forced to become strong logic low, and the signal at described first input end place to become logic high, described clearing and delay cell is made to relieve control to described first output signal, the signal of described second output terminal and described first output is logic low, described judging unit is high at its output terminal output logic, start to make the read operation of memory circuit effective, described roll-over unit is being subject to the impact of the strong logic low that described second output produces, more weak upset logic is produced to described first output terminal, when described first output terminal becomes logic height by this effect, described judging unit passes through the logical relation judged between the signal of described first output terminal and described second output, low at its output output logic, terminate the read operation of memory circuit.
According to the address change observation circuit of this technical em-bodiments and address change monitoring device for monitoring external address signal change, for the read operation of storage class integrated circuit provides timing control signal.In addition, the embodiment of this technology is applied to the quick generation of address change observation circuit in the memory circuit of different size in integrated circuit, to meet the different demands of Integrated circuit designers for memory circuit reading speed.
Accompanying drawing explanation
According to following explanation and claims, by reference to the accompanying drawings, foregoing and other feature of the present disclosure will clearly.Recognizing that these drawing merely show according to examples more of the present disclosure and under therefore should not being considered to the prerequisite limiting disclosure scope, describe the disclosure in detail, in accompanying drawing by using accompanying drawing with extra characteristic sum details:
Fig. 1 shows the structural representation of the address change observation circuit according to prior art;
Fig. 2 shows the circuit diagram of the ATD unit in address change observation circuit as shown in Figure 1;
Fig. 3 shows the input/output signal sequential relationship of ATD unit as shown in Figure 2;
Fig. 4 A shows the schematic block diagram of the address change observation circuit according to this technology embodiment;
Fig. 4 B shows the exemplary timing diagram of address change observation circuit as shown in Figure 4 A;
Fig. 5 describes the process flow diagram according to the generation method of the address change observation circuit of this technology;
Fig. 6 shows the schematic block diagram of the address change observation circuit according to another embodiment of this technology; And
Fig. 7 shows the schematic circuit of the address change observation circuit of the another embodiment according to this technology.
Embodiment
By reference to the accompanying drawings the embodiment of this technology will be described in detail hereinafter.Although set forth in conjunction with the embodiments, be interpreted as this and not mean this technology limiting in these embodiments.On the contrary, this technology is intended to contain the various possibilities, modification and the equivalent that define in this technical spirit and scope of being defined by claims.
In addition, in order to better understand this technology, in the following description, a large amount of concrete details has been set forth, such as concrete circuit, device, annexation etc.But the those of ordinary skill in the field of this technology should be appreciated that, do not have these concrete details, this technology still can be implemented.In other some embodiments, for the ease of highlighting the purport of this technology, the technology known is not explained in detail.
Specific embodiment hereinafter described represents the exemplary embodiment of this technology, and be only in essence example illustrate and unrestricted.In the description, mention that " embodiment " or " embodiment " mean to be included at least one embodiment of this technology in conjunction with the special characteristic described by this embodiment, structure or characteristic.Term " in one embodiment " in the description each position occurs all not relating to identical embodiment, neither mutually get rid of other embodiments or various embodiments.All features disclosed in this instructions, or the step in disclosed all methods or process, except mutually exclusive feature and/or step, all can combine by any way.In addition, it should be understood by one skilled in the art that the diagram provided at this is all for illustrative purposes, and diagram is not necessarily drawn in proportion.Should be appreciated that when claim " element " " be connected to " or " coupling " to another element time, it can be directly connected or coupled to another element or can there is intermediary element.On the contrary, when claim element " be directly connected to " or " being directly coupled to " another element time, there is not intermediary element.Identical Reference numeral indicates identical element.Term "and/or" used herein comprises any and all combinations of one or more relevant project listed.
According to the address change observation circuit of this technical em-bodiments and address change monitoring device for monitoring external address signal change, for the read operation of storage class integrated circuit provides timing control signal.In addition, the embodiment of this technology is applied to the quick generation of address change observation circuit in the memory circuit of different size in integrated circuit, to meet the different demands of Integrated circuit designers for memory circuit reading speed.
Fig. 4 A shows the schematic block diagram of the address change observation circuit according to this technology embodiment.Address change observation circuit shown in Fig. 4 A, in ground floor structure still as shown in Figure 1, distinguishing characteristics is the inner structure of ATD unit.
As shown in Figure 4 A, each ATD unit comprises clearing and delay cell 13, roll-over unit 11 and judging unit 12.
Reset and delay cell 13, there is first input end and the second input end and the first output terminal 16 and the second output terminal 17.Receive from the input signal of the input end 14 of device at the second input end and receive anti-phase input signal at first input end.
Between the first output terminal 16 that roll-over unit 11 is connected in series in clearing and delay cell 13 and the second output terminal 17.
Judging unit 12 based on the logical relation between the signal on the signal on the first output terminal 16 and the second output terminal 17, at output terminal 15 output timing signal.
Such as, the input end 14 of ATD unit itself and anti-phase input signal 18 connect two input ends of clearing and delay cell 13, and whether the signal controlling two output terminals (logic is deposited a little) 16 and 17 resets.When anti-phase input signal 18 is logical one, the first output terminal 16 is set to logical zero.When input signal 14 is logical one, the second output terminal 17 is set to logical zero.Roll-over unit 11 provides the upset logic compared with weak logic intensity for the first and second output terminals 16 and 17, namely its logical strength of providing is more weak than the logical strength reset and delay cell 13 produces, thus the signal at guarantee the first and second output terminal 16 and 17 places its logical value is contrary after stabilization.Here, the implication of " logical strength " refers to that the load capacity of the drive source producing certain logic is stronger, such as, when output low level, larger filling electric current can be born, can bear during output high level and larger draw electric current.Such as, the logical strength of the upset logic that roll-over unit 11 provides lower than the signal on the first and second output terminals 16 and 17, the such as logical strength of logical zero signal.Then, judging unit 12, by the logical relation between the signal on judgement first and second output terminal 16 and 17, exports the read operation Control timing sequence signal of memory circuit at output terminal 15.According to an embodiment, in period of time T, when the signal of the first and second output terminals 16 and 17 is logical zero, judging unit 12 is logical one in its output terminal 15 output signal.
According to one embodiment of present invention, when roll-over unit 12 provides the upset logic from logical zero to logical one, clearing and delay cell 13 can provide at its output terminal 16 and postpone a period of time to the foundation of this logical one.This such as by arranging capacitor to realize in clearing and delay cell 13.High level T effective time of the reading useful signal needed for memory circuit read operation determines jointly by resetting the logical strength that the delay ability that applies the signal of the first and second output terminals 16 and 17 with delay cell 13 and roll-over unit 11 apply.
Fig. 4 B shows the exemplary timing diagram of address change observation circuit as shown in Figure 4 A.As shown in Figure 4 B, before the address signal at input end 14 place of ATD unit produces address signal change, namely before changing into logical one from logical zero, the signal at the first output terminal 16 place is in logical zero, the signal at the second output terminal 17 place is in logical one, and the signal at output terminal 15 place of judging unit 12 is in logical zero.When the signal at input end 14 place is changing into logical one from logical zero, the signal at the second output terminal 17 place can be forced to become strong logical zero, and the input signal 18 after phase inverter 20 is anti-phase becomes logical zero, make to reset and delay cell 13 relieves control to the first output terminal 16 place signal.Now the signal at the second output terminal 17 and the first output terminal 16 place is logical zero, thus judging unit 12 is at its output terminal 15 output logic " 1 ", starts to make the read operation of memory circuit effective.Roll-over unit 11 is subject to the impact of the strong logical zero that the second output terminal 17 place produces at this moment, more weak upset logic is produced to the first output terminal 16, when the first output terminal 16 becomes logical one by this effect, judging unit 12 is by the logical relation between judgement first output terminal 16 and the signal at the second output terminal 17 place, at output terminal 15 place output logic " 0 ", terminate the read operation of memory circuit.Can be determined by the delay ability reset and delay cell 13 provides from the time that the process that " 0 " becomes " 1 " spends at the signal of the first output terminal 16.Like this, the signal at output terminal 15 place is T from becoming logical one to recovering time of logical zero.
Fig. 5 describes the process flow diagram according to the generation method of the address change observation circuit of this technology.Generation method according to this technology can be configured address variation monitoring circuit according to specific reading speed.
In step 51, multiple clearing and the delay cell 13 of at least one or parallel connection are provided, each clearing and delay cell have the first and second input ends and the first and second output terminals 16 and 17, receive input signal at described second input end and receive anti-phase input signal at first input end.
In step 52, provide roll-over unit 11, described roll-over unit 11 is connected in series between described first output terminal 16 and described second output terminal 17;
In step 53, provide judging unit 12, described judging unit 12 based on the logical relation between the signal on the signal on described first output terminal 16 and described second output terminal 17, output timing signal;
In step 54, provide or circuit, described or circuit receives the clock signal exported from multiple address change observation circuit, exports the timing control signal being used for memory read operations.
Before the address signal at input end 14 place of address variation monitoring circuit produces address signal change, namely before changing into logical one from logical zero, the signal at the first output terminal 16 place is in logical zero, the signal at the second output terminal 17 place is in logical one, and the signal at output terminal 15 place of judging unit 12 is in logical zero.When the signal at input end 14 place is changing into logical one from logical zero, the signal at the second output terminal 17 place can be forced to become strong logical zero, and the input signal 18 after phase inverter 20 is anti-phase becomes logical zero, make to reset and delay cell 13 relieves control to the first output terminal 16 place signal.Now the signal at the second output terminal 17 and the first output terminal 16 place is logical zero, thus judging unit 12 is at its output terminal 15 output logic " 1 ", starts to make the read operation of memory circuit effective.Roll-over unit 11 is subject to the impact of the strong logical zero that the second output terminal 17 place produces at this moment, more weak upset logic is produced to the first output terminal 16, when the first output terminal 16 becomes logical one by this effect, judging unit 12 is by the logical relation between judgement first output terminal 16 and the signal at the second output terminal 17 place, at output terminal 15 place output logic " 0 ", terminate the read operation of memory circuit.Can be determined by the delay ability reset and delay cell 13 provides from the time that the process that " 0 " becomes " 1 " spends at the signal of the first output terminal 16.Like this, the signal at output terminal 15 place is T from becoming logical one to recovering time of logical zero.
Although show the step 51 generating clearing and delay cell in Fig. 5 according to sequence number, generate the step 52 of roll-over unit, generate the step 53 of judging unit and the step 54 of formation logic or structure, but those of ordinary skill in the art it should be appreciated that and there is no any sequencing between above-mentioned step.Above-mentioned Reference numeral is only for purposes of illustration, instead of limits the precedence relationship between these steps.
In method as shown in Figure 5, clearing and delay cell can be configured according to specific reading speed, such as, realize by carrying out parallel connection configuration for the module in clearing and delay cell 13.
Fig. 6 shows the schematic block diagram of the address change observation circuit according to another embodiment of this technology.As shown in Figure 6, reset and have intrinsic unit 21 and extra cell 22 in delay cell 13.The number of extra cell can be 0, also can be several.Unit 21 and 22 and and 22 suitable unit between there is parallel relationship.Because the intensity overturning logic is determined by roll-over unit 11, putting before this, the logic flip-flop transition (i.e. T effective time of memory circuit read operation) produced uniquely is determined by the ability in logical delay of clearing and delay cell 13.According to embodiments of the invention, reset equal with the delay ability of unit 21 and 22 etc. in delay cell 13, but also can be unequal.
When needing to configure specific reading speed (i.e. T effective time of read operation), only need be configured the delay ability of clearing and delay cell 13, namely the configuration in number or type need only be carried out to the extra cell in parallel with intrinsic unit 21, without the need to manually carrying out circuit design.And this is configured to configuration in parallel, both without the need to revising existing layout, also without the need to annexation existing in modification circuits, makes the method realize fast by computer program.
Fig. 7 shows the schematic circuit of the address change observation circuit of the another embodiment according to this technology.As shown in Figure 7, reset and delay cell 13 in intrinsic clearing and delay cell 31 comprise the first MOS transistor, such as nmos pass transistor, its grid receives anti-phase input signal, drain electrode end as or be connected to the first lead-out terminal 16; First capacitor, between the drain electrode being connected in series in the first MOS transistor and source electrode; Second MOS transistor, such as nmos pass transistor, its grid receive input signal, drain electrode end as or be connected to the second lead-out terminal, the second capacitor, between the drain electrode being connected in series in the second MOS transistor and source electrode.In unit 31 shown in Fig. 7, the driving force of NMOS is much larger than the driving force of phase inverter in roll-over unit 11.In addition, unit 32 is substantially the same with the structure of unit 31 with 33, and with unit 31 to reset the connected mode with in delay cell 13 identical.
The address change observation circuit of friction speed can be generated according to the method for this technical em-bodiments, meet the requirement of the memory circuit of different size.In addition, said method can be realized by computer program, improves the efficiency generating friction speed address change observation circuit.
Clearing above-mentioned as those skilled in the art will appreciate that and delay cell, roll-over unit, judging unit both can be realized by mimic channel, also can by digital circuit, or by simulate and digital hybrid circuit realizes.
In addition, although be described in detail with positive logic in above-described embodiment, those skilled in the art will appreciate that, this is not the restriction to this technology, and this technology may be used in negative logic system equally.
In addition, some little difference can be there are between the hardware and software implementation of system schema.The use of hardware or software general (but not always, because the selection under specific circumstances between hardware and software may become very important) a kind ofly embodies the design alternative weighed between cost and efficiency.Various means (such as, hardware, software and/or firmware) system as described herein and/or other technologies can be implemented, and preferred scheme changes along with applied environment.Such as, if realization side determines that speed and accuracy are most important, then the means being mainly hardware and/or firmware can be selected by realization side; If dirigibility is most important, then the embodiment of mainly software can be selected by realization side; Or be equally also alternatively, the particular combination of hardware, software and/or firmware can be selected by realization side.
Above detailed description, by user's block diagram, process flow diagram and/or example, has set forth numerous embodiments of equipment and/or method.When this block scheme, process flow diagram and/or example comprise one or more function and/or operation, it will be understood by those skilled in the art that each function in this block scheme, process flow diagram or example and/or operation can by various hardware, software, firmware or in fact their combination in any come to realize separately and/or jointly.In one embodiment, some parts of theme described in this technology can be realized by special IC (ASIC), field programmable gate array (FPGA), digital signal processor (DSP) or other integrated forms.But, those skilled in the art will recognize that, some aspects of embodiment disclosed herein can realize in integrated circuits on the whole or partly equally, be embodied as one or more computer programs of running on one or more computing machine (such as, be embodied as the one or more programs run in one or more computer system), be embodied as one or more programs of running on the one or more processors (such as, be embodied as the one or more programs run on one or more microprocessor), be embodied as firmware, or be embodied as in fact the combination in any of aforesaid way, and those skilled in the art are according to the disclosure, the ability of design circuit and/or write software and/or firmware code will be possessed.In addition, those skilled in the art will recognize that, the mechanism of theme described in the disclosure can be distributed as the program product of various ways, and regardless of the actual particular type of signal bearing medium being used for performing distribution, the exemplary embodiment of theme described in this technology is all applicable.The example of signal bearing medium includes but not limited to: recordable-type media, as floppy disk, hard disk drive, compact-disc (CD), digital universal disc (DVD), numerical tape, computer memory etc.; And transmission type media, as numeral and/or analogue communication medium (such as, optical fiber cable, waveguide, wired communications links, wireless communication link etc.).
Those skilled in the art will appreciate that above-detailed equipment and/or technique, after this using engineering practice described equipment and/or technique to be integrated in data handling system is the conventional means of this area.Also namely, can being integrated in data handling system by the test of fair amount at least partially of equipment described here and/or technique.Those skilled in the art will recognize that, it is one or more that typical data handling system generally comprises in the following: system unit shell; Video display apparatus; Storer, as volatibility and nonvolatile memory; Processor, as microprocessor and digital signal processor; Computational entity, as operating system, driver, graphical user interface and application program; One or more interactive device, as touch pad or screen; And/or control system, comprise feedback loop and control motor (such as, for the feedback of sense position and/or speed; For mobile and/or modifying ingredients and/or quantity control motor).Typical data handling system can utilize the commercial parts of any appropriate (as data calculate/communicate and/or parts conventional in network calculations/communication system) to be achieved.
Theme described in this technology illustrates that different parts are included in different miscellaneous parts or different parts are connected from different miscellaneous parts sometimes.Should be appreciated that the framework described like this is example, in fact can realize many other frameworks that can realize identical function.Conceptually, " association " is in order to realize any setting of the parts of identical function effectively, thus realizes required function.Therefore, any two parts that combination here realizes concrete function can be regarded as each other " association " thus realize required function, and regardless of framework or intermediate member.Equally, any two parts so associated also can be regarded as each other " being operably connected " or " being operationally coupled " to realize required function, and any two parts that can so associate also can be regarded as each other " can operationally be coupled " to realize required function.The concrete example that can operationally be coupled includes but not limited to physically can match and/or physically mutual parts, and/or wireless interaction and/or can the parts of wireless interaction, and/or logic is mutual and/or can the mutual parts of logic.
As for any about use that is most and/or singular references herein, those skilled in the art can be singulative from most formal transformation, and/or are converted to most form from singulative, with applicable specific environment and application.For clarity sake, interchangeable in this explicit state singulative/most form.
Those skilled in the art are to be understood that, generally speaking, the term used, particularly in claims (such as, in the main part of claims) term that uses, usually be interpreted as open to the outside world term (such as, term " comprises " and should be interpreted as " including but not limited to ", term " have " should be interpreted as " at least having " etc.).Those skilled in the art should also be understood that then this intention will explicitly point out in this claim if be intended to indicate concrete number in introduced claim, and when do not have this clearly indicate, then there is not this intention.
Above to the description that example is shown of this technology, comprise described in summary, not desirably limit or restriction to disclosed precise forms.Although there is described herein specific embodiment and the example of this technology for illustration purposes, when not departing from the wider spirit and scope of this technology, various equivalent modifications is fine.In fact, should be appreciated that signal specific, electric current, frequency, power range values, time etc. are provided for illustration purpose, and other values also can be used in other embodiments and example of instructing according to this technology.
Claims (11)
1. an address change observation circuit, comprising:
Reset and delay cell, there is first input end and the second input end and the first output terminal and the second output terminal, receive input signal at described second input end and receive anti-phase input signal at first input end;
Roll-over unit, is connected in series between described first output terminal and described second output terminal; And
Judging unit, based on the logical relation between the signal on the signal on described first output terminal and described second output terminal, output timing signal;
Wherein, before the input signal of described second output changes into logic height from logic low, the signal of described first output is in logic low, it is high that the signal of described second output is in logic, the signal of the output of described judging unit is in logic low, when the signal of the second input end is changing into logic height from logic low, the signal of described second output is forced to become strong logic low, and the signal at described first input end place to become logic high, described clearing and delay cell is made to relieve control to described first output signal, the signal of described second output terminal and described first output is logic low, described judging unit is high at its output terminal output logic, start to make the read operation of memory circuit effective, described roll-over unit is being subject to the impact of the strong logic low that described second output produces, more weak upset logic is produced to described first output terminal, when described first output terminal becomes logic height by this effect, described judging unit passes through the logical relation judged between the signal of described first output terminal and described second output, low at its output output logic, terminate the read operation of memory circuit.
2. address change observation circuit as claimed in claim 1, also comprises:
Phase inverter, receives described input signal at its input end, exports described anti-phase input signal at its output terminal.
3. address change observation circuit as claimed in claim 1, also comprises another and resets and delay cell, and described another resets and delay cell has and to be connected in parallel with described clearing and delay cell and to have identical circuit structure.
4. address change observation circuit as claimed in claim 1, wherein said clearing and delay cell comprise:
First MOS transistor, grid receives described anti-phase input signal, and drain electrode end is as described first output terminal;
First capacitor, is connected in series between the source electrode of the first MOS transistor and drain electrode;
Second MOS transistor, grid receives described input signal, and drain electrode end is as described second output terminal;
Second capacitor, is connected in series between the source electrode of the second MOS transistor and drain electrode.
5. address change observation circuit as claimed in claim 4, the capacity of wherein said first and second capacitors is substantially equal.
6. address change observation circuit as claimed in claim 4, the driving force of wherein said first MOS transistor and the second MOS transistor is greater than the driving force of described roll-over unit.
7. address change observation circuit as claimed in claim 1, wherein said roll-over unit comprises two phase inverters be connected in antiparallel.
8. address change observation circuit as claimed in claim 1, wherein said judging unit is OR-NOT circuit.
9. an address change monitoring device, comprising:
The address change observation circuit of multiple parallel connection, each address change testing circuit is address change observation circuit as claimed in claim 1;
Or circuit, receive the clock signal exported from described multiple address change observation circuit, export the timing control signal being used for memory read operations.
10. utilize a method for Practical computer teaching address change observation circuit, comprise step:
Multiple clearing and the delay cell of at least one or parallel connection are provided, each clearing and delay cell have the first and second input ends and the first and second output terminals, receive input signal at described second input end and receive anti-phase input signal at first input end;
There is provided roll-over unit, described roll-over unit is connected in series between described first output terminal and described second output terminal;
Judging unit is provided, described judging unit based on the logical relation between the signal on the signal on described first output terminal and described second output terminal, output timing signal;
There is provided or circuit, described or circuit receives the clock signal exported from multiple address change observation circuit, exports the timing control signal being used for memory read operations;
Wherein, before the input signal of described second output changes into logic height from logic low, the signal of described first output is in logic low, it is high that the signal of described second output is in logic, the signal of the output of described judging unit is in logic low, when the signal of the second input end is changing into logic height from logic low, the signal of described second output is forced to become strong logic low, and the signal at described first input end place to become logic high, described clearing and delay cell is made to relieve control to described first output signal, the signal of described second output terminal and described first output is logic low, described judging unit is high at its output terminal output logic, start to make the read operation of memory circuit effective, described roll-over unit is being subject to the impact of the strong logic low that described second output produces, more weak upset logic is produced to described first output terminal, when described first output terminal becomes logic height by this effect, described judging unit passes through the logical relation judged between the signal of described first output terminal and described second output, low at its output output logic, terminate the read operation of memory circuit.
11. methods as claimed in claim 10, wherein, based on selected reading speed, increase another reset and delay cell, described another reset and delay cell with described at least one reset and delay cell in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310371648.5A CN103440879B (en) | 2013-08-23 | 2013-08-23 | Address change monitoring circuit, device and generation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310371648.5A CN103440879B (en) | 2013-08-23 | 2013-08-23 | Address change monitoring circuit, device and generation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103440879A CN103440879A (en) | 2013-12-11 |
| CN103440879B true CN103440879B (en) | 2016-04-20 |
Family
ID=49694568
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310371648.5A Active CN103440879B (en) | 2013-08-23 | 2013-08-23 | Address change monitoring circuit, device and generation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103440879B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4843596A (en) * | 1986-11-29 | 1989-06-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with address transition detection and timing control |
| CN1151592A (en) * | 1995-11-30 | 1997-06-11 | 三菱电机株式会社 | Semiconductor memory device comprising address transition detecting circuit having stable response characteristic for address signal conversion |
| KR20010045945A (en) * | 1999-11-09 | 2001-06-05 | 박종섭 | Address transition detection circuit of semiconductor memory |
| CN102820045A (en) * | 2011-06-09 | 2012-12-12 | 芯成半导体（上海）有限公司 | Address transition detection circuit |
-
2013
- 2013-08-23 CN CN201310371648.5A patent/CN103440879B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4843596A (en) * | 1986-11-29 | 1989-06-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with address transition detection and timing control |
| CN1151592A (en) * | 1995-11-30 | 1997-06-11 | 三菱电机株式会社 | Semiconductor memory device comprising address transition detecting circuit having stable response characteristic for address signal conversion |
| KR20010045945A (en) * | 1999-11-09 | 2001-06-05 | 박종섭 | Address transition detection circuit of semiconductor memory |
| CN102820045A (en) * | 2011-06-09 | 2012-12-12 | 芯成半导体（上海）有限公司 | Address transition detection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103440879A (en) | 2013-12-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103227635B (en) | A kind of CMOS full adder of high-speed low-power-consumption and operation method thereof | |
| JP5935544B2 (en) | Method, product and computer system for generating an analog model of a logic cell | |
| JP2020129425A (en) | Random access memory and associated circuit, method and system | |
| CN108092660A (en) | Sub-threshold circuit optimization method and system | |
| CN103116069A (en) | Method, device and system of testing of chip frequency | |
| CN105247436B (en) | Voltage regulator with feedforward and feedback control | |
| US20100275168A1 (en) | Design method of semiconductor integrated circuit device and program | |
| CN107315863B (en) | Layout optimization method and device, terminal and storage medium | |
| CN114880975A (en) | Hardware trojan generation method, system, equipment and medium | |
| CN109639267A (en) | A kind of phase inverter quantity optimization method in exclusive or-majority logic figure | |
| CN108664066B (en) | Chip and voltage adjusting method thereof | |
| CN103440879B (en) | Address change monitoring circuit, device and generation method thereof | |
| CN104092240A (en) | Method and system for recognizing connection mode of photovoltaic modules | |
| CN107517055B (en) | Design method of CMOS digital logic circuit | |
| JP2000357183A (en) | Representing method and generating method for delay library, and delay calculating method using delay library | |
| CN105758648A (en) | Vehicle performance test method and device | |
| JP4664222B2 (en) | Allowable value calculation method and verification method | |
| CN103309781A (en) | Single-rate SDRAM detection method based on DSP and FPGA | |
| CN102624227A (en) | Current control circuit | |
| CN109714057B (en) | Dynamic digital-to-analog signal conversion model and modeling method | |
| CN104392703B (en) | A kind of mu balanced circuit and control method, display device | |
| CN104077172A (en) | Method for verifying AXI (advanced extensible interface) read-write video data and VMM (verification methodology manual) verifying platform | |
| CN204808885U (en) | Optimize in data storage type flash memory and read data circuit | |
| JP2016213637A (en) | Error verification method of programmable logic device, and circuit formation method of programmable logic device | |
| CN204858964U (en) | Clock actuating system of charge pump |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |