CN103440018B - Power control method, power control circuit and energy-saving system - Google Patents
Power control method, power control circuit and energy-saving system Download PDFInfo
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- CN103440018B CN103440018B CN201310378463.7A CN201310378463A CN103440018B CN 103440018 B CN103440018 B CN 103440018B CN 201310378463 A CN201310378463 A CN 201310378463A CN 103440018 B CN103440018 B CN 103440018B
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Abstract
The embodiment of the invention provides a power control method, a power control circuit and an energy-saving system. In order to the solve the problems that according to a battery management chip of an existing terminal, when a controller of the terminal is powered down, due to the fact that the terminal can not enter a low-power consumption mode, the power consumption is increased, and the probability that a battery is damaged is increased, the method comprises the steps of being free of generating signals for delayed restarting any more when periodic pulse signals coming from the controller of the terminal are not detected in preset duration, determining the signals which are not generated for the delayed restarting in delayed duration, and after the delayed duration is ended, outputting a conditioning signal of a first level to a low-power consumption mode register in the battery management chip of the terminal, wherein the conditioning signal of the first level can allow the battery management chip to enter the low-power consumption mode.
Description
Technical field
The present invention relates to technical field of circuit design, particularly relate to a kind of Poewr control method, power control circuit and energy conserving system.
Background technology
At present, some chips are had to may operate in low-power consumption mode, such as, battery management chip, battery need not (namely battery does not charge, and does not also power to mobile terminal) or battery electric quantity is lower time may operate in low-power consumption mode under, to save electric energy, thus extend the service time of battery.Due to when the electricity of battery is lower, if can not charge the battery in time, then because chip from battery ceaselessly power taking, can cause cell damage.If when battery electric quantity is lower, under chip operates in low-power consumption mode, so because the service time of battery extends, the chance charged the battery will increase, and can reduce the probability of cell damage like this.
Battery management chip conventional at present has two kinds, and one can be operated in standby mode, measurement pattern and monitoring mode.When it is in standby mode, except serial ports and voltage regulator circuit, other circuit are all in closed condition, and at this moment the electric current of this battery management chip is in minimum state.When it operates in measurement pattern or monitoring mode, if need to enter standby mode, CPU (central processing unit) (CPU, Center ProcessingUnit) by Serial Peripheral Interface (SPI) (SPI, Serial Peripheral Interface) the work period configuration bit of the register of the standby mode of this battery management chip is set to level signal needed for standby mode, thus make this battery management chip enter standby mode.Another kind of battery management chip, can be operated in sleep pattern, when it is operated in sleep pattern, the power consumption of this chip is minimum.The controlled input/output port of the register of the sleep pattern of this battery management chip can be set to level signal needed for sleep pattern by SPI by CPU, thus makes this battery management chip enter sleep pattern.
Two kinds of above-mentioned battery management chips, when entering low-power consumption mode, all need CPU to write certain value at the low-power consumption mode register of chip, just can enter low-power consumption mode.Now, if CPU powered-off fault, CPU is not able to do in time in the low-power consumption mode register of chip, write corresponding value, so chip cannot enter low-power consumption mode, now, the power consumption of chip will be larger, and the electricity of battery can be depleted by chip very soon, and this can cause the impaired probability of battery to increase.
In sum, existing battery management chip, need the controller in terminal, as just can low-power consumption mode be entered under the control of CPU, if and controller powered-off fault, then battery management chip cannot enter low-power consumption mode, and this can make the electricity of battery be depleted very soon, thus causes the impaired probability of battery to increase.
Summary of the invention
Embodiments provide a kind of Poewr control method, power control circuit and energy conserving system, in order to solve existing battery management chip, when the controller power down of terminal, low-power consumption mode cannot be entered, power consumption is increased, thus causes the problem that the impaired probability of battery increases.
First aspect, provides a kind of Poewr control method, comprising:
When not detecting the cyclic pulse signal of the controller of self terminal in preset duration, the not regeneration time delay signal of restarting;
Determine not generate in a delay duration signal that time delay is restarted, after this delay duration terminates, export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of described terminal, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode;
Wherein, start time of described delay duration early than or equal finish time of described preset duration, described delay duration is more than or equal to described preset duration, and described preset duration is greater than a pulse width of described cyclic pulse signal.
In conjunction with first aspect, in the implementation that the first is possible, before determining not generate in a delay duration signal that time delay restarts, described method also comprises:
When the number of the pulse of the described cyclic pulse signal detected in preset duration is less than N, the not regeneration time delay signal of restarting, wherein, preset duration equals the length in N number of cycle of described cyclic pulse signal.
In conjunction with the first possible implementation of first aspect, in the implementation that the second is possible, described method also comprises:
When the number of the pulse of the described cyclic pulse signal detected in preset duration is more than or equal to N, generate the signal that time delay is restarted;
In a delay duration after the signal that generation time delay is restarted, export the adjustment signal of second electrical level to the low-power consumption mode register in described battery management chip, the adjustment signal of described second electrical level can make described battery management chip exit the signal of low-power consumption mode.
Second aspect, provides another kind of Poewr control method, comprising:
The control signal that the controller determining not receive terminal exports, the battery management chip that described control signal is provided for described terminal enters low-power consumption mode or exits low-power consumption mode;
Export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of described terminal, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode.
In conjunction with second aspect, in the implementation that the first is possible, export the adjustment signal of the first level to the low-power consumption mode register in described battery management chip before, described method also comprises:
The control signal of the first predeterminated voltage that the controller determining to receive described terminal exports.
In conjunction with second aspect, in the implementation that the second is possible, described method also comprises:
The control signal of the second predeterminated voltage that the controller determining to receive described terminal exports;
Export the adjustment signal of second electrical level to the low-power consumption mode register in described battery management chip, the adjustment signal of described second electrical level can make described battery management chip exit low-power consumption mode.
The third aspect, a kind of power control circuit is provided, comprise and detect generative circuit and output circuit, described detection generative circuit connects for exporting the port of cyclic pulse signal and described output circuit in the controller of terminal, and described output circuit connects the low-power consumption mode register in the battery management chip of described terminal;
Described detection generative circuit, during for not detecting the cyclic pulse signal of the controller of self terminal in preset duration, the not regeneration time delay signal of restarting; Described preset duration is greater than a pulse width of described cyclic pulse signal;
Described output circuit, for determining not generate in a delay duration signal that time delay is restarted, after this delay duration terminates, export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of described terminal, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode; Start time of described delay duration early than or equal finish time of described preset duration, described delay duration is more than or equal to described preset duration.
In conjunction with the third aspect, in the implementation that the first is possible, described detection generative circuit also for:
Before determining not generate in a delay duration signal that time delay restarts, if the number of the pulse of the described cyclic pulse signal detected in preset duration is less than N, the not regeneration time delay signal of restarting, wherein, preset duration equals the length in N number of cycle of described cyclic pulse signal.
In conjunction with the first possible implementation of the third aspect, in the implementation that the second is possible, described detection generative circuit also for:
When the number of the pulse of the cyclic pulse signal detected in preset duration is more than or equal to N, generate the signal that time delay is restarted;
Described output circuit, also in a delay duration after generating the time delay signal of restarting, export the adjustment signal of second electrical level to the low-power consumption mode register in described battery management chip, the adjustment signal of described second electrical level can make described battery management chip exit the signal of low-power consumption mode.
Fourth aspect, another kind of power control circuit is provided, comprise receiving circuit and transmission circuit, described receiving circuit connects for exporting the port of control signal and described transmission circuit in the controller of terminal, and described transmission circuit connects the low-power consumption mode register in the battery management chip of described terminal;
Described receiving circuit, the control signal that the controller for receiving described terminal exports, the battery management chip that described control signal is provided for described terminal enters low-power consumption mode or exits low-power consumption mode;
Described transmission circuit, during for determining the control signal not receiving the output of described controller at described receiving circuit, export the adjustment signal of the first level to the low-power consumption mode register in described battery management chip, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode.
In conjunction with fourth aspect, in the implementation that the first is possible, described transmission circuit also for:
When the control signal receiving the first predeterminated voltage that described controller exports determined by described receiving circuit, export the adjustment signal of the first level to the low-power consumption mode register in described battery management chip, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode.
In conjunction with fourth aspect, in the implementation that the second is possible, described transmission circuit also for:
When the control signal of the second predeterminated voltage that the controller that described receiving circuit determines to receive described terminal exports, export the adjustment signal of second electrical level to the low-power consumption mode register in described battery management chip, the adjustment signal of described second electrical level can make described battery management chip exit low-power consumption mode.
In conjunction with fourth aspect, in the implementation that the third is possible, described receiving circuit comprises the first resistance unit;
One end of described first resistance unit connects for exporting the port of control signal in described controller, and the control signal received exports to described transmission unit by the other end of described first resistance unit.
In conjunction with fourth aspect, in the 4th kind of possible implementation, described transmission circuit comprises the second resistance unit and the 3rd resistance unit, one end of described second resistance unit receives setting voltage signal, the other end of described second resistance unit is connected with one end of the 3rd resistance unit, and receives the signal of described receiving element; If the adjustment signal of described setting voltage signal and the first level is high level signal, or be low level signal, then the other end of described 3rd resistance unit connects the low-power consumption mode register in the battery management chip of described terminal.
In conjunction with fourth aspect, in the 5th kind of possible implementation, if described setting voltage signal is high level signal, the adjustment signal of the first level is low level signal, or described setting voltage signal is low level signal, the signal of the adjustment of the first level is high level signal; Then described output circuit also comprises negate circuit, and the other end of described 3rd resistance unit connects the low-power consumption mode register in the battery management chip of described terminal by described negate circuit.
5th aspect, a kind of energy conserving system is provided, comprise the controller of terminal, the battery management chip of this terminal and the third aspect, the third aspect the first possible implementation to the first possible implementation of possible implementation, fourth aspect and the fourth aspect of the second of the third aspect to any one power control circuit in the 5th kind of possible implementation of fourth aspect.
The beneficial effect of the embodiment of the present invention comprises:
Embodiments provide a kind of Poewr control method, power control circuit and energy conserving system, if if the controller powered-off fault of terminal, cyclic pulse signal can not be exported, time then by the cyclic pulse signal that do not detect the controller of self terminal in preset duration, the not regeneration time delay signal of restarting, and determine not generate in a delay duration signal that time delay restarts, after this delay duration terminates, the adjustment signal of the first level is exported to the low-power consumption mode register in the battery management chip of this terminal, the adjustment signal of this first level can make this battery management chip enter low-power consumption mode, or by after the control signal determining the controller output not receiving terminal, the battery management chip that this control signal is provided for described terminal enters low-power consumption mode or exits low-power consumption mode, export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of this terminal, the adjustment signal of this first level can make this battery management chip enter low-power consumption mode, thus make the battery management chip of terminal to enter low-power consumption mode, and then reduce power consumption, extend the service time of battery, the impaired probability of final reduction battery.
Accompanying drawing explanation
One of process flow diagram of the Poewr control method that Fig. 1 provides for the embodiment of the present invention;
The process flow diagram two of the Poewr control method that Fig. 2 provides for the embodiment of the present invention;
The process flow diagram three of the Poewr control method that Fig. 3 provides for the embodiment of the present invention;
The process flow diagram four of the Poewr control method that Fig. 4 provides for the embodiment of the present invention;
The process flow diagram five of the Poewr control method that Fig. 5 provides for the embodiment of the present invention;
The process flow diagram six of the Poewr control method that Fig. 6 provides for the embodiment of the present invention;
Fig. 7 is applied to one of process flow diagram in reality for Poewr control method that the embodiment of the present invention provides;
Fig. 8 is applied to the process flow diagram two in reality for Poewr control method that the embodiment of the present invention provides;
One of structural representation of the power control circuit that Fig. 9 embodiment of the present invention provides;
The structural representation two of the power control circuit that Figure 10 embodiment of the present invention provides;
The structural representation three of the power control circuit that Figure 11 embodiment of the present invention provides;
The structural representation four of the power control circuit that Figure 12 a provides for the embodiment of the present invention;
The structural representation five of the power control circuit that Figure 12 b provides for the embodiment of the present invention.
Embodiment
Embodiments provide a kind of Poewr control method, power control circuit and energy conserving system, during by the cyclic pulse signal that do not detect the controller of self terminal in preset duration, determine that the controller of terminal breaks down, uncontrollable battery management chip enters low-power consumption mode, the not regeneration time delay signal of restarting, if do not generate the signal that time delay is restarted in a delay duration, then after this delay duration terminates, the adjustment signal of the first level is exported to the low-power consumption mode register in the battery management chip of described terminal, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode, start time of described delay duration early than or equal finish time of described preset duration, described delay duration is more than or equal to described preset duration, and described preset duration is greater than a pulse width of described cyclic pulse signal.Or, by after the control signal determining the controller output not receiving terminal, export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of described terminal, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode; The battery management chip that described control signal is provided for described terminal enters low-power consumption mode or exits low-power consumption mode, thus break down at the controller of terminal, when uncontrollable battery management chip enters low-power consumption mode, the adjustment signal of the first level is exported to the low-power consumption mode register in the battery management chip of terminal, the battery management chip of control terminal enters low-power consumption mode, thus reduces power consumption.
Below in conjunction with Figure of description, the embodiment of a kind of Poewr control method, power control circuit and energy conserving system that the embodiment of the present invention provides is described.
A kind of Poewr control method that the embodiment of the present invention provides, as shown in Figure 1, specifically comprises the following steps:
S101, when not detecting the cyclic pulse signal of controller of self terminal in preset duration, the not regeneration time delay signal of restarting;
S102, determine not generate in a delay duration signal that time delay restarts, after this delay duration terminates, export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of this terminal, the adjustment signal of the first level can make this battery management chip enter low-power consumption mode;
Wherein, start time of delay duration early than or equal finish time of preset duration, delay duration is more than or equal to preset duration, and preset duration is greater than a pulse width of described cyclic pulse signal.
Like this can at the controller of terminal, as CPU etc., during abnormal power-down, because controller can not export cyclic pulse signal, thus the battery management chip of control terminal enters low-power consumption mode.
Wherein, cyclic pulse signal can be clock signal, or other cyclical signal etc.The adjustment signal of the first level can be high level signal, can be also low level signal, the level of signal required when specifically depending on that the battery management chip of terminal enters low-power consumption mode.
Further, the Poewr control method that the embodiment of the present invention provides, as shown in Figure 2, before S102, also comprises:
When S101a, the number of the pulse of cyclic pulse signal detected in preset duration are less than N, the not regeneration time delay signal of restarting, wherein, preset duration equals the length in N number of cycle of this cyclic pulse signal.
Alternatively, the Poewr control method that the embodiment of the present invention provides, as shown in Figure 3, also comprises:
When S301, the number carrying out the pulse of the cyclic pulse signal of the controller of self terminal detected in preset duration are more than or equal to N, generate the signal that time delay is restarted;
In S302, a delay duration after generating the time delay signal of restarting, export the adjustment signal of second electrical level to the low-power consumption mode register in the battery management chip of this terminal, the adjustment signal of second electrical level can make this battery management chip exit low-power consumption mode.
When the adjustment signal of the first level is high level signal, the adjustment signal of second electrical level is low level signal; When the adjustment signal of the first level is low level, the adjustment signal of second electrical level is high level signal.
The another kind of Poewr control method that the embodiment of the present invention provides, as shown in Figure 4, comprising:
The control signal that S401, the controller determining not receive terminal export, the battery management chip that control signal is provided for this terminal enters low-power consumption mode or exits low-power consumption mode;
S402, export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of this terminal, the adjustment signal of the first level can make described battery management chip enter low-power consumption mode.
Alternatively, the Poewr control method that the embodiment of the present invention provides, as shown in Figure 5, also comprised before S402:
The control signal of the first predeterminated voltage that S401a, the controller determining to receive terminal export.
Wherein, the signal of the first predeterminated voltage can be high level signal, also can be low level signal.
Alternatively, the Poewr control method that the embodiment of the present invention provides, as shown in Figure 6, also comprises:
The control signal of the second predeterminated voltage that S601, the controller determining to receive terminal export;
S602, export the adjustment signal of second electrical level to the low-power consumption mode register in the battery management chip of terminal, the adjustment signal of second electrical level can make described battery management chip exit low-power consumption mode.
When the control signal of the first predeterminated voltage is high level signal, the control signal of the second predeterminated voltage is low level signal; When the control signal of the first predeterminated voltage is low level signal, the control signal of the second predeterminated voltage is high level signal.
In order to further illustrate the Poewr control method that the embodiment of the present invention provides, being applied in reality for this Poewr control method below and being described.
A kind of Poewr control method that the embodiment of the present invention provides is applied to process flow diagram in reality as shown in Figure 7, comprising:
S701, judge whether the control signal of the controller receiving self terminal, the battery management chip that this control signal is provided for this terminal enters low-power consumption mode or exits low-power consumption mode, if so, performs S702, otherwise, perform S703;
S702, judge that whether the control signal from this controller that receives is the control signal of the first predeterminated voltage, if so, perform S703, otherwise namely control signal is the control signal of the second predeterminated voltage, performs S704;
S703, export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of this terminal, the adjustment signal of the first level can make described battery management chip enter low-power consumption mode;
S704, export the adjustment signal of second electrical level to the low-power consumption mode register in the battery management chip of terminal, the adjustment signal of second electrical level can make described battery management chip exit low-power consumption mode.
The another kind of Poewr control method that the embodiment of the present invention provides is applied to process flow diagram in reality as shown in Figure 8, comprising:
S801, judge whether the number carrying out the pulse of the cyclic pulse signal of the controller of self terminal detected in preset duration is more than or equal to N, if so, then performs S802, otherwise, perform S804; Wherein, preset duration equals the length in N number of cycle of control signal;
The signal that S802, generation time delay are restarted;
In S803, a delay duration after generating the time delay signal of restarting, export the adjustment signal of second electrical level to the low-power consumption mode register in the battery management chip of this terminal, the adjustment signal of second electrical level can make this battery management chip exit the signal of low-power consumption mode; Start time of this delay duration early than or equal finish time of this preset duration, this delay duration is more than or equal to this preset duration;
The signal that S804, not regeneration time delay are restarted;
If S805 does not generate the signal that time delay is restarted in a delay duration, then after this delay duration terminates, export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of this terminal, the adjustment signal of the first level can make this battery management chip enter low-power consumption mode.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of power control circuit and energy conserving system, the principle of dealing with problems due to these circuit and system is similar to aforementioned control method, therefore the enforcement of these circuit and system see the enforcement of preceding method, can repeat part and repeats no more.
A kind of power control circuit that the embodiment of the present invention provides, as shown in Figure 9, comprises and detects generative circuit 91 and output circuit 92; Detect generative circuit 91 to connect for exporting port and the output circuit 92 of cyclic pulse signal in the controller 90 of terminal, output circuit 92 connects the low-power consumption mode register in the battery management chip 93 of terminal;
Detect generative circuit 91, during for not detecting the cyclic pulse signal of controller 90 of self terminal in preset duration, the not regeneration time delay signal of restarting; Described preset duration is greater than a pulse width of described cyclic pulse signal;
Output circuit 92, for determining not generate in a delay duration signal that time delay is restarted, after this delay duration terminates, export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip 93 of terminal, the adjustment signal of described first level can make battery management chip 93 enter low-power consumption mode; Start time of described delay duration early than or equal finish time of described preset duration, described delay duration is more than or equal to described preset duration.
Wherein, detection generative circuit 91 and output circuit 92 can be arranged in battery management chip, also can be positioned at outside battery management chip.In Fig. 9, for detect generative circuit and output circuit be positioned at there is low-power consumption mode chip outside be described.
Alternatively, detect generative circuit 91, also for before determine not generate in a delay duration signal that time delay restarts at output circuit 92, if the number of the pulse of the described cyclic pulse signal detected in preset duration is less than N, the not regeneration time delay signal of restarting, wherein, preset duration equals the length in N number of cycle of described cyclic pulse signal.
Alternatively, detect generative circuit 91, when being also more than or equal to N for the number of the pulse of cyclic pulse signal detected in preset duration, generate the signal that time delay is restarted;
Output circuit 92, also in a delay duration after generating the time delay signal of restarting, export the adjustment signal of second electrical level to the low-power consumption mode register in described battery management chip, the adjustment signal of described second electrical level can make described battery management chip exit the signal of low-power consumption mode.
Another power control circuit that the embodiment of the present invention provides, as shown in Figure 10, comprise receiving circuit 101 and transmission circuit 102, receiving circuit 101 connects for exporting port and the transmission circuit 102 of control signal in the controller 90 of terminal, and transmission circuit 102 connects the low-power consumption mode register in the battery management chip 93 of terminal;
Receiving circuit 101, the control signal that the controller 90 for receiving terminal exports, the battery management chip 93 that described control signal is provided for terminal enters low-power consumption mode or exits low-power consumption mode;
Transmission circuit 102, during for determining the control signal not receiving controller 90 output at described receiving circuit 101, export the adjustment signal of the first level to the low-power consumption mode register in battery management chip 93, the adjustment signal of described first level can make battery management chip 93 enter low-power consumption mode.
Alternatively, transmission circuit 102, time also for determining the control signal receiving the first predeterminated voltage that controller 90 exports at receiving circuit 101, export the adjustment signal of the first level to the low-power consumption mode register in battery management chip 93, the adjustment signal of the first level can make described battery management chip enter low-power consumption mode.
Alternatively, transmission circuit 102, during the control signal of the second predeterminated voltage also exported for the controller 90 determining to receive terminal at receiving circuit 101, export the adjustment signal of second electrical level to the low-power consumption mode register in battery management chip 93, the adjustment signal of second electrical level can make described battery management chip 93 exit low-power consumption mode.
Alternatively, as shown in figure 11, receiving circuit 101 comprises the first resistance unit 1011; For exporting the port of control signal in one end connection control device 90 of the first resistance unit 1011, the control signal received exports to transmission unit 102 by the other end of the first resistance unit 1011.Wherein, the first resistance unit be some strings the network of resistance of parallel connection.
Alternatively, as figure 12 a shows, transmission circuit 102 comprises the second resistance unit 1021 and the 3rd resistance unit 1022, one end of second resistance unit 1021 receives setting voltage signal V, the other end of the second resistance unit 1021 is connected with one end of the 3rd resistance unit 1022, and receives the signal of receiving element 102; If the adjustment signal of setting voltage signal V and the first level is high level signal, or be low level signal, then the other end of the 3rd resistance unit 1022 connects the low-power consumption mode register in the battery management chip 93 of terminal.
Wherein, setting voltage signal V can be ground signalling, also for presetting the voltage signal of magnitude of voltage, can generate high level signal according to this setting voltage signal.Second resistance unit be some strings the network of resistance of parallel connection, the 3rd resistance unit be some strings the network of resistance of parallel connection.
When setting voltage signal V is ground signalling, when battery management chip 93 low-power consumption mode register wherein sets to 0, just low-power consumption mode can be entered when namely storing low level signal in low-power consumption mode register, the signal that battery management chip 93 namely can be made to enter low-power consumption mode is low level signal, then when the first resistance unit 1011 does not receive control signal, first resistance unit 1011 cannot export control signal to output circuit 102, and receive setting voltage signal V due to one end of the second resistance unit 1021, i.e. ground connection, therefore, 3rd resistance unit 1022 can output low level signal, second resistance unit 1021 is pull down resistor.When preset signals V is the voltage signal presetting magnitude of voltage, when battery management chip 93 low-power consumption mode register wherein puts 1, just low-power consumption mode can be entered when namely storing high level signal in low-power consumption mode register, the signal that battery management chip 93 namely can be made to enter low-power consumption mode is high level signal, then when the first resistance unit 1011 does not receive control signal, first resistance unit 1011 cannot export control signal to output circuit 102, and receive setting voltage signal V due to one end of the second resistance unit 1021, namely the voltage signal presetting magnitude of voltage is received, therefore, 3rd resistance unit 1022 can export high level signal, second resistance unit 1021 is pull-up resistor.
Alternatively, as shown in Figure 12b, if setting voltage signal is high level signal, the adjustment signal of the first level is low level signal, or setting voltage signal is low level signal, and the signal of the adjustment of the first level is high level signal; The other end that then described output circuit also comprises negate circuit the 1023, three resistance unit 1022 connects the low-power consumption mode register in the battery management chip 93 of terminal by negate circuit 1023.
When setting voltage signal V is ground signalling, when battery management chip 93 low-power consumption mode register wherein puts 1, just low-power consumption mode can be entered when namely storing high level signal in low-power consumption mode register, the signal that battery management chip 93 namely can be made to enter low-power consumption mode is high level signal, then when the first resistance unit 1011 does not receive control signal, first resistance unit 1011 cannot export control signal to output circuit 102, and receive setting voltage signal V due to one end of the second resistance unit 1021, i.e. ground connection, therefore, 3rd resistance unit 1022 can output low level signal, second resistance unit 1021 is pull down resistor.Therefore, output circuit 102 comprises negate circuit 1023, and the low level signal of input can be converted to high level signal by this negate circuit 1023.When preset signals V is the voltage signal presetting magnitude of voltage, when battery management chip 93 low-power consumption mode register wherein sets to 0, just low-power consumption mode can be entered when namely storing low level signal in low-power consumption mode register, the signal that battery management chip 93 namely can be made to enter low-power consumption mode is low level signal, then when the first resistance unit 1011 does not receive control signal, first resistance unit 1011 cannot export control signal to output circuit 102, and receive setting voltage signal V due to one end of the second resistance unit 1021, namely the voltage signal presetting magnitude of voltage is received, therefore, 3rd resistance unit 1022 can export high level signal, second resistance unit 1021 is pull-up resistor.Therefore, output circuit 102 comprises negate circuit 1023, and the high level signal of input can be converted to low level signal by this negate circuit 1023.
The embodiment of the present invention also provides a kind of energy conserving system, comprises arbitrary power control circuit that the controller of terminal, the battery management chip of this terminal and the embodiment of the present invention provide.
Through the above description of the embodiments, those skilled in the art can be well understood to the embodiment of the present invention can by hardware implementing, and the mode that also can add necessary general hardware platform by software realizes.Based on such understanding, the technical scheme of the embodiment of the present invention can embody with the form of software product, it (can be CD-ROM that this software product can be stored in a non-volatile memory medium, USB flash disk, portable hard drive etc.) in, comprise some instructions and perform method described in each embodiment of the present invention in order to make a computer equipment (can be personal computer, server, or the network equipment etc.).
It will be appreciated by those skilled in the art that accompanying drawing is the schematic diagram of a preferred embodiment, the module in accompanying drawing or flow process might not be that enforcement the present invention is necessary.
It will be appreciated by those skilled in the art that the module in the device in embodiment can carry out being distributed in the device of embodiment according to embodiment description, also can carry out respective change and be arranged in the one or more devices being different from the present embodiment.The module of above-described embodiment can merge into a module, also can split into multiple submodule further.
The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (16)
1. a Poewr control method, is characterized in that, comprising:
When not detecting the cyclic pulse signal of the controller of self terminal in preset duration, the not regeneration time delay signal of restarting;
Determine not generate in a delay duration signal that time delay is restarted, after this delay duration terminates, export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of described terminal, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode;
Wherein, start time of described delay duration early than or equal finish time of described preset duration, described delay duration is more than or equal to described preset duration, and described preset duration is greater than a pulse width of described cyclic pulse signal.
2. control method as claimed in claim 1, is characterized in that, before determining not generate in a delay duration signal that time delay restarts, described method also comprises:
When the number of the pulse of the described cyclic pulse signal detected in preset duration is less than N, the not regeneration time delay signal of restarting, wherein, preset duration equals the length in N number of cycle of described cyclic pulse signal.
3. control method as claimed in claim 2, it is characterized in that, described method also comprises:
When the number of the pulse of the described cyclic pulse signal detected in preset duration is more than or equal to N, generate the signal that time delay is restarted;
In a delay duration after the signal that generation time delay is restarted, export the adjustment signal of second electrical level to the low-power consumption mode register in described battery management chip, the adjustment signal of described second electrical level can make described battery management chip exit the signal of low-power consumption mode.
4. a Poewr control method, is characterized in that, comprising:
The control signal that the controller determining not receive terminal exports, the battery management chip that described control signal is provided for described terminal enters low-power consumption mode or exits low-power consumption mode;
Export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of described terminal, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode.
5. control method as claimed in claim 4, it is characterized in that, export the adjustment signal of the first level to the low-power consumption mode register in described battery management chip before, described method also comprises:
The control signal of the first predeterminated voltage that the controller determining to receive described terminal exports.
6. control method as claimed in claim 4, it is characterized in that, described method also comprises:
The control signal of the second predeterminated voltage that the controller determining to receive described terminal exports;
Export the adjustment signal of second electrical level to the low-power consumption mode register in described battery management chip, the adjustment signal of described second electrical level can make described battery management chip exit low-power consumption mode.
7. a power control circuit, it is characterized in that, comprise and detect generative circuit and output circuit, described detection generative circuit connects for exporting the port of cyclic pulse signal and described output circuit in the controller of terminal, and described output circuit connects the low-power consumption mode register in the battery management chip of described terminal;
Described detection generative circuit, during for not detecting the cyclic pulse signal of the controller of self terminal in preset duration, the not regeneration time delay signal of restarting; Described preset duration is greater than a pulse width of described cyclic pulse signal;
Described output circuit, for determining not generate in a delay duration signal that time delay is restarted, after this delay duration terminates, export the adjustment signal of the first level to the low-power consumption mode register in the battery management chip of described terminal, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode; Start time of described delay duration early than or equal finish time of described preset duration, described delay duration is more than or equal to described preset duration.
8. circuit as claimed in claim 7, is characterized in that, described detection generative circuit also for:
Before determining not generate in a delay duration signal that time delay restarts, if the number of the pulse of the described cyclic pulse signal detected in preset duration is less than N, the not regeneration time delay signal of restarting, wherein, preset duration equals the length in N number of cycle of described cyclic pulse signal.
9. circuit as claimed in claim 8, is characterized in that, described detection generative circuit also for:
When the number of the pulse of the cyclic pulse signal detected in preset duration is more than or equal to N, generate the signal that time delay is restarted;
Described output circuit, also in a delay duration after generating the time delay signal of restarting, export the adjustment signal of second electrical level to the low-power consumption mode register in described battery management chip, the adjustment signal of described second electrical level can make described battery management chip exit the signal of low-power consumption mode.
10. a power control circuit, it is characterized in that, comprise receiving circuit and transmission circuit, described receiving circuit connects for exporting the port of control signal and described transmission circuit in the controller of terminal, and described transmission circuit connects the low-power consumption mode register in the battery management chip of described terminal;
Described receiving circuit, the control signal that the controller for receiving described terminal exports, the battery management chip that described control signal is provided for described terminal enters low-power consumption mode or exits low-power consumption mode;
Described transmission circuit, during for determining the control signal not receiving the output of described controller at described receiving circuit, export the adjustment signal of the first level to the low-power consumption mode register in described battery management chip, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode.
11. circuit as claimed in claim 10, is characterized in that, described transmission circuit also for:
When the control signal receiving the first predeterminated voltage that described controller exports determined by described receiving circuit, export the adjustment signal of the first level to the low-power consumption mode register in described battery management chip, the adjustment signal of described first level can make described battery management chip enter low-power consumption mode.
12. circuit as claimed in claim 10, is characterized in that, described transmission circuit also for:
When the control signal of the second predeterminated voltage that the controller that described receiving circuit determines to receive described terminal exports, export the adjustment signal of second electrical level to the low-power consumption mode register in described battery management chip, the adjustment signal of described second electrical level can make described battery management chip exit low-power consumption mode.
13. circuit as claimed in claim 10, it is characterized in that, described receiving circuit comprises the first resistance unit;
One end of described first resistance unit connects for exporting the port of control signal in described controller, and the control signal received exports to described transmission unit by the other end of described first resistance unit.
14. circuit as claimed in claim 10, it is characterized in that, described transmission circuit comprises the second resistance unit and the 3rd resistance unit, one end of described second resistance unit receives setting voltage signal, the other end of described second resistance unit is connected with one end of the 3rd resistance unit, and receives the signal of described receiving element; If the adjustment signal of described setting voltage signal and the first level is high level signal, or be low level signal, then the other end of described 3rd resistance unit connects the low-power consumption mode register in the battery management chip of described terminal.
15. circuit as claimed in claim 14, is characterized in that, if described setting voltage signal is high level signal, the adjustment signal of the first level is low level signal, or described setting voltage signal is low level signal, the signal of the adjustment of the first level is high level signal; Then described output circuit also comprises negate circuit, and the other end of described 3rd resistance unit connects the low-power consumption mode register in the battery management chip of described terminal by described negate circuit.
16. 1 kinds of energy conserving systems, is characterized in that, comprise the controller of terminal, the battery management chip of this terminal and the power control circuit as described in any one of claim 7 ~ 15.
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| CN201310378463.7A CN103440018B (en) | 2013-08-27 | 2013-08-27 | Power control method, power control circuit and energy-saving system |
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| CN201310378463.7A CN103440018B (en) | 2013-08-27 | 2013-08-27 | Power control method, power control circuit and energy-saving system |
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| CN103440018B true CN103440018B (en) | 2015-07-08 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103746417B (en) * | 2013-12-23 | 2016-07-06 | 中国科学院微电子研究所 | The Low-power-consumptiocontrol control method of a kind of battery detection chip and system |
| CN109878377B (en) * | 2019-04-19 | 2024-03-22 | 惠州市盛微电子有限公司 | Battery management system |
| CN113268134A (en) * | 2021-04-19 | 2021-08-17 | 瑞芯微电子股份有限公司 | Power-down delay and power consumption saving method and device |
| CN113655843B (en) * | 2021-07-01 | 2022-11-18 | 济南安时能源科技有限公司 | Power chip management system and method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1781229A (en) * | 2003-03-18 | 2006-05-31 | 高通股份有限公司 | Battery management. |
| US20060221650A1 (en) * | 2005-03-30 | 2006-10-05 | Sanken Electric Co., Ltd. | DC-DC converter |
| US20070146038A1 (en) * | 2005-12-22 | 2007-06-28 | Carl Werner | Clock distribution network supporting low-power mode |
| CN101640476A (en) * | 2009-03-25 | 2010-02-03 | 杭州矽力杰半导体技术有限公司 | Power regulator and control method thereof |
| CN101640481A (en) * | 2008-11-20 | 2010-02-03 | 杭州矽力杰半导体技术有限公司 | Mixed power converter |
-
2013
- 2013-08-27 CN CN201310378463.7A patent/CN103440018B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1781229A (en) * | 2003-03-18 | 2006-05-31 | 高通股份有限公司 | Battery management. |
| US20060221650A1 (en) * | 2005-03-30 | 2006-10-05 | Sanken Electric Co., Ltd. | DC-DC converter |
| US20070146038A1 (en) * | 2005-12-22 | 2007-06-28 | Carl Werner | Clock distribution network supporting low-power mode |
| CN101640481A (en) * | 2008-11-20 | 2010-02-03 | 杭州矽力杰半导体技术有限公司 | Mixed power converter |
| CN101640476A (en) * | 2009-03-25 | 2010-02-03 | 杭州矽力杰半导体技术有限公司 | Power regulator and control method thereof |
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