CN103425437B - Initial writing address system of selection and device - Google Patents
Initial writing address system of selection and device Download PDFInfo
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Abstract
The invention discloses a kind of initial writing address system of selection, belong to electric digital data processing field. Described method comprises: receive the data that storage organization is sent and write instruction; According to the corresponding M of initial writing address last time1Individual memory cell is determined MOD(M1+ N, M) address of individual memory cell is as tentative initial writing address; Judge whether the current write request cumulative number in described counter of fixing tentatively initial writing address institute's corresponding stored unit is the maximum in all counters; If not, described tentative initial writing address is defined as to this initial writing address. The present invention passes through according to the tentative initial writing address of initial writing address last time, and when maximum in the not all counter of current write request cumulative number in counter of judging this tentative initial writing address institute's corresponding stored unit, determine that this tentative initial writing address is this initial writing address, reach even data writing, promote the object of bandwidth availability ratio.
Description
Technical field
The present invention relates to electric digital data processing field, particularly a kind of initial writing address system of selection and device.
Background technology
Memory is for storing the device of data in the hardware device such as computer or server. In prior art, conventional depositsReservoir has SRAM(StaticRandomAccessMemory, static RAM), DDR(DoubleDataRateSynchronousDynamicRandomAccessMemory, Double Data Rate synchronous DRAM), QDR(QuadDataRateSynchronousDynamicRandomAccessMemory, Quad Data Rate synchronous DRAM) etc. ManySheet memory can form the needs of jumbo storage organization when meeting big data quantity storage.
Please refer to Fig. 1, it shows a kind of structural representation of existing storage organization. This storage organization includes 6 PMC(PacketMemoryController, bag storage control), each PMC control two DDR, in every DDR, comprise againHaving 8 bank(is physical store body, for storing data, herein referred to as memory cell). Simultaneously to each PMC, eachBank in DDR in PMC and each DDR is independently numbered respectively, and 6 bag storage controls are numbered respectivelyPMC0-PMC5, comprises two random access memory of DDR0-DDR1 in each bag storage control, in each random access memory, comprise againEight physical store bodies of bank0-bank7. Based on the intrinsic memory mechanism of DDR, the write operation of each bank single can write 32BThe data of (Byte, byte), each PMC single operation can write the data of 64B.
In the time need to carrying out the read-write of big data quantity on storage organization, in order to ensure that data are at every DDR, and every DDRIn each bank, can write relatively uniformly, to reach minimizing read/write conflict, the maximum effect that improves bandwidth ability. ExistingTechnology provides a kind of initial writing address system of selection: the first, and external chip receives the data that storage organization is sent and writes fingerOrder; The second, external chip generate at random one No. PMC, No. DDR and No. bank, and by No. PMC that generates at random, DDRNumber and No. bank corresponding bank as initial writing address; The 3rd, external chip is initiated write request to PMC, request fromInitial bank corresponding to writing address starts to carry out data according to predetermined write sequence and writes. Predetermined write sequence refers to often and writesWhen 32B data, add one No. DDR; Often write 64B data and add one No. PMC; While often writing 64*6B data, add one No. bank.
Realizing in process of the present invention, inventor finds that prior art at least exists following problem:
In existing initial writing address system of selection, although can ensure the uniformity of data writing from long-term use procedure,But in short time use procedure, may there is writing inhomogeneous situation, such as: storage organization as shown in Figure 1, is connectingContinuous carrying out in the process of 96 data writings, certain several adjacent or close bank may be repeatedly chosen as initially and be write groundLocation, corresponding, some adjacent or close bank may be never selected in addition.
Summary of the invention
For solve data write inhomogeneous, the problem that bandwidth availability ratio is low, the embodiment of the present invention provides a kind of and has initially write groundLocation system of selection and storage control. Described technical scheme is as follows:
On the one hand, provide a kind of initial writing address system of selection, described method comprises:
Receive the data that storage organization is sent and write instruction, described storage organization comprises storage control and M memory cell,Each memory cell has address sum counter separately, and each counter tires out for the current write request of preserving corresponding stored unitMetering number;
According to the corresponding M of initial writing address last time1Individual memory cell is determined MOD(M1+ N, M) ground of individual memory cellLocation is as tentative initial writing address;
Judge whether the current write request cumulative number in described counter of fixing tentatively initial writing address institute's corresponding stored unit is instituteThere is the maximum in counter;
If not, described tentative initial writing address is defined as to this initial writing address;
Wherein, M is more than or equal to 2 integer; M1For being greater than 0, be less than or equal to the integer of M; N be 1 or N be positive integerAnd be not the approximate number of M.
On the other hand, provide a kind of initial writing address selecting arrangement, described device comprises:
Command reception module and address selection module;
Described command reception module, writes instruction for receiving the data that storage organization is sent, and described storage organization comprises storageA controller and M memory cell, each memory cell has address sum counter separately, and each counter is used for preserving correspondenceThe current write request cumulative number of memory cell;
Described address selection module comprises:
Address determining unit, for according to the corresponding M of initial writing address last time1Individual memory cell is determined MOD(M1+N,M）The address of individual memory cell is as tentative initial writing address;
The first judging unit, for the tentative initial writing address institute's corresponding stored unit that judges that described address determining unit is determinedWhether the current write request cumulative number in counter is the maximum in all counters;
Described address determining unit, if also judge that for described the first judging unit described tentative initial writing address institute correspondence depositsMaximum in the not all counter of current write request cumulative number in the counter of storage unit, initially writes described fixing tentativelyEnter address and be defined as this initial writing address;
Wherein, M is more than or equal to 2 integer; M1For being greater than 0, be less than or equal to the integer of M; N be 1 or N be positive integerAnd be not the approximate number of M.
The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is:
By to have data to write fashionable at every turn, according to the corresponding M of initial writing address last time1Individual memory cell is determined MOD（M1+ N, M) address of individual memory cell is as tentative initial writing address, and to judge this tentative initial writing address institute rightWhile answering the maximum in the not all counter of current write request cumulative number in the counter of memory cell, determine this tentative at the beginning ofBeginning writing address is this initial writing address, reaches even data writing in buffer memory, promotes the object of bandwidth availability ratio.
Brief description of the drawings
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, attached by required use during embodiment is described belowFigure is briefly described, and apparently, the accompanying drawing in the following describes is only some embodiments of the present invention, for this areaThose of ordinary skill, is not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation of the buffer structure that provides of background technology of the present invention;
Fig. 2 is the method flow diagram of the initial writing address system of selection that provides of the embodiment of the present invention one;
Fig. 3 is the method flow diagram of the initial writing address system of selection that provides of the embodiment of the present invention two;
Fig. 4 is the pointer repeating query schematic diagram that the embodiment of the present invention two provides;
Fig. 5 is the coordinate schematic diagram of the memory cell arrangement order that provides of the embodiment of the present invention two;
Fig. 6 is the structural representation of the initial writing address selecting arrangement that provides of the embodiment of the present invention three;
Fig. 7 is the another kind of structural representation of the initial writing address selecting arrangement that provides of the embodiment of the present invention three;
Fig. 8 is another structural representation of the initial writing address selecting arrangement that provides of the embodiment of the present invention three;
Fig. 9 is another structural representation of the initial writing address selecting arrangement that provides of the embodiment of the present invention three;
Figure 10 is also a kind of structural representation of the initial writing address selecting arrangement that provides of the embodiment of the present invention three;
Figure 11 is the structural representation of the request sending module that provides of the embodiment of the present invention three.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment of the present invention do intoOne step ground is described in detail.
Embodiment mono-
Refer to Fig. 2, it shows a kind of method flow diagram of initial writing address system of selection, and this initial writing address is selectedMethod can be applied to the storage organization shown in Fig. 1. The initial writing address system of selection that the embodiment of the present invention provides can comprise:
Step 101, receives the data that storage organization is sent and writes instruction;
Wherein, storage organization comprises storage control and M memory cell, and each memory cell has address and counting separatelyDevice, each counter is for preserving the current write request cumulative number of corresponding stored unit.
Step 102, according to the corresponding M of initial writing address last time1Individual memory cell is determined MOD(M1+ N, M) individual storageThe address of unit is as tentative initial writing address;
Wherein N is default step-length, and M is more than or equal to 2 integer, in addition, and in order to reach the initial writing address of uniform design,So that the object of even data writing in buffer memory need to can be taken turns in the process of Continuous Selection M tentative initial writing addressStream access (repeating query) each memory cell, therefore, N can be 1 or for be less than M and for the positive integer of M approximate number (M can not be divided exactly by N). MOD(M1+ N, M) represent (M1+ N)/M remainder number: if M1+ N is less than M, MOD(M1+N,M）=M1+ N, selects M1+ N the corresponding address of memory cell is tentative initial writing address; If M1+ N is greater than M, MOD（M1+N,M）=M1+ N-M, selects M1+ N-M the corresponding address of memory cell is tentative initial writing address.
In practical application, the method for the tentative initial writing address of this step 102 selection can be by arranging the finger that points to bank addressPin, progressively increases pointer (, when pointer progressively increases behind last bank address, to return to first according to predetermined step-length N repeating queryBank continues address to progressively increase) mode realize. By this step, can by each memory cell in a fixed order poll once,No matter can reach the short time or add up for a long time, it is all the effect evenly writing.
Step 103, the current write request cumulative number in the counter of the tentative initial writing address institute's corresponding stored of judgement unit isNo is maximum in all counters;
Consider the execution speed of hardware, have data to write fashionable at every turn, first calculate the numerical value of the counter that all bank are corresponding,Get the maximum in all counters, and obtain according to the numerical value of the current write request cumulative number in this maximum and individual count deviceWhether the current write request cumulative number obtaining in individual count device is the peaked bit sequence in all counters, this bit orderWhether the current write request cumulative number that the value of T numerical value in row characterizes in T counter is in all countersMaximum, wherein, T is greater than 0 integer that is less than or equal to M. By this step, can will realize the peaked mechanism of jumping,Make the write request cumulative number on each bank as far as possible even.
Step 104, if not, will fix tentatively initial writing address and be defined as this initial writing address, and initial according to thisWriting address sends write request to storage control.
If in bank corresponding to this tentative initial writing address in the not all counter of numerical value of write request cumulative numberLarge value, using this tentative initial writing address as this initial writing address.
In sum, the initial writing address system of selection that the present embodiment one provides, according to last time initial writing address correspondingM1Individual memory cell is determined MOD(M1+ N, M) address of individual memory cell as tentative initial writing address (because N is 1Or N is to be less than M and is not the positive integer of M approximate number, thus can be in the process of Continuous Selection M tentative initial writing addressIn, can repeating query to each memory cell), and at the counter of judging this tentative initial writing address institute's corresponding stored unitIn the not all counter of current write request cumulative number in maximum time, determine that this tentative initial writing address is at the beginning of thisBeginning writing address, reaches even data writing in buffer memory, promotes the object of bandwidth availability ratio; Storage organization as shown in Figure 1,Than prior art, the method that the present embodiment provides can repeating query in the process of continuous 96 tentative initial writing positions of selectionTo each bank, thereby provide than better uniformity and the higher bandwidth availability ratio of writing of prior art.
Embodiment bis-
For the initial writing address system of selection that more detailed description embodiment mono-provides, refer to Fig. 2, it shows oneThe method flow diagram of planting initial writing address system of selection, the method can be applied to all kinds of clothes that relate to Large Volume Data buffer memoryBusiness device. Still to be applied at the storage organization shown in Fig. 1 as example, this initial writing address system of selection can realize with depositStorage structure utilizes in the connected external chip of same bus, and the initial writing address system of selection that the embodiment of the present invention provides can be wrappedDraw together:
Step 201, external chip is received in the instruction of data writing in storage organization;
While having data flow will write in storage organization in bus, external core sector-meeting receives in storage organization data writingInstruction.
Step 202, according to the corresponding M of initial writing address last time1Individual memory cell is determined MOD(M1+ N, M) individual storageThe address of unit is as tentative initial writing address;
Wherein, storage organization comprises one or more storage controls, and M the bank(that storage control is controlled depositsStorage unit); N is default step-length, and M is more than or equal to 2 integer, N be 1 or N be positive integer and be not the approximate number of M.Concrete storage organization as shown in Figure 1, storage organization includes 6 storage controls, and M=6*2*8=96 bank. ItsIn, default step-length N can be 7.
The mode that complementation in this step can be progressively increased according to predetermined step-length by repeating query pointer in actual applications realizes equallyEffect. Concretely, each bank have separately one for the address read and write and one current for preserving corresponding bankThe counter of write request cumulative number, and the address sum counter of each bank is corresponding one by one. External chip sets in advance a wheelFollow counter corresponding to the each bank of pointed, and receiving after the instruction of data writing in storage organization, by repeating query pointerOn the counter basis of the corresponding bank of initial writing address last time, progressively increase by default step-length 7. Incorporated by reference to reference to 4, figureThe pointer repeating query schematic diagram showing, if default step-length is 7. Before progressively increasing, the 1st counter corresponding to bank of repeating query pointed;After progressively increasing, the 8th corresponding counter of bank of repeating query pointed, again progressively increasing, it is corresponding to point to the 15th bank instituteCounter; If progressively increased after the counter that any one bank is corresponding in last 6 bank, repeating query while again progressively increasingPointer returns to counter corresponding in the 1st to 6 bank.
In other words, if taking the storage organization that comprises 8 bank in the each DDR shown in Fig. 1 as example, before supposing to progressively increase,Counter corresponding to bank that repeating query pointed (PMC0, DDR0, bank0) is pointed; After progressively increasing for the first time, repeating queryCounter corresponding to bank that pointed (PMC0, DDR0, bank7) is pointed; And after progressively increasing for the second time, repeating query pointerPoint to (PMC0, DDR1, bank6) counter corresponding to bank pointed; After progressively increasing again, repeating query pointed (PMC1,DDR0, bank5) counter corresponding to bank pointed; ,,; So circulation is gone down. When repeating query pointer is by default step-length 7While progressively increasing, can ensure that repeating query pointer can repeating query arrive the corresponding counter of each bank. In actual applications, this is defaultStep-length also can be configured to other numerical value, can ensure that each bank is arrived in repeating query corresponding while needing only according to this default step-length repeating queryCounter, in theory, so long as not the approximate number of M, can serve as default step-length.
Before this writes, the address of the corresponding bank of counter that polling pointer points to is initial writing address last time; WhenAfter polling pointer progressively increases once, the address of the corresponding bank of counter of the current sensing of polling pointer can be used as temporary transient initialWriting address.
Step 203, judge this tentative initial writing address the reading of corresponding counter whether be maximum, if so, enterStep 204 if not, enters step 205;
Because the address sum counter of each bank is corresponding one by one, therefore, counter corresponding to each address is this address correspondenceThe counter of bank, this meter reading is the current write request cumulative number of this bank.
Concrete, external chip can also set in advance a maximum register, receives data writing in storage organization at every turnInstruction after, the current value of the counter that all bank are corresponding is obtained in external core sector-meeting, and maximum is wherein stored in to maximumIn register, by the numeric ratio in the numerical value of each counter and maximum register, obtain individual count according to comparative result simultaneouslyWhether the current write request cumulative number in device is the peaked bit sequence in all counters, the T in this bit sequenceWhether the current write request cumulative number that the value of individual numerical value characterizes in T counter is the maximum in all counters, itsIn, T is greater than 0 integer that is less than or equal to M. Server judges this tentative initial writing address institute by the bit sequence obtainingWhether the numerical value of corresponding counter is maximum, if so, returns to step 202, continues repeating query pointer to pass by default step-lengthAdd; If this tentative initial writing address the numerical value of corresponding counter be not maximum, enter step 204. Should be noted that, this section of details, for realize preferred scheme for hardware, if adopt software mode to realize, can not generate bit orderBe listed as and directly compare.
In addition, if all counter values all equate, such as the value of all M counter is 0, by repeating query pointerAfter progressively increasing once according to default step-length, directly enter step 204.
Step 204, according to the tentative corresponding M of initial writing address last time2Individual memory cell is determined MOD(M2+ N, M) individualThe address of memory cell is as tentative initial writing address, and returns to step 203;
When the counter values of the repeating query pointed after progressively increasing by default step-length is maximum, external chip can be according to last timeTentative M corresponding to initial writing address2Individual memory cell is determined MOD(M2+ N, M) at the beginning of individual memory cell is tentative as anotherBeginning writing address, wherein, M2=MOD（M1+ N, M); Then it is right that external chip rejudges another tentative initial writing address instituteAnswer whether the current write request cumulative number in the counter of memory cell is the maximum in all counters. Although statement slightlyDifference, but those skilled in the art can know, by looping step 203 and step 204, can search out correspondenceCounter is not peaked tentative initial writing address.
Step 205, using this tentative initial writing address as this initial writing address;
When the counter values of the repeating query pointed after progressively increasing by default step-length is not maximum, by corresponding this counterThe tentative initial writing address of bank is as this initial writing address.
Step 206, from this initial writing address, is sent in current writing to storage control successively according to predefined procedureAddress write the write request of a packet in corresponding bank.
Concrete, server can become one or more packet by Data Division to be written, and wherein, each packet comprisesData volume is not more than storage control write-once and operates the maximum amount of data that can write. Such as, DDR memory is example,The each write operation of PMC can write the data of 32B in DDR, and server can become multiple bags by Data Division to be writtenContaining the packet of 32B data, the data of not enough 32B are processed according to 32B.
For effective bandwidth is maximized, can be from initial writing address, according to the order of repeating query DDR, PMC and bankBe sent in the write request of asking in turn data writing bag in each bank to storage control successively. Concrete, for the ease of statement,Can represent putting in order of each bank or writing address by the form of coordinate, wherein, x axle represents X in storage organizationThe order of placement of DDR, y axle represents putting in order of Y bank in each DDR; One of the every transmission of server is write currentEnter in institute's corresponding stored unit, address and write after the write request of a packet, whether judge the middle x of current writing address (x, y)Equal X-1; If x is not equal to X-1 in current writing address (x, y), after the x in current writing address being added to 1, continueContinue to storage control and be sent in the write request that writes next packet in current writing address institute's corresponding stored unit; If worked asIn front writing address (x, y), x equals X-1, continues to judge in current writing address (x, y), whether y equals Y-1; IfY is not equal to Y-1 in current writing address (x, y), changes the x in current writing address into 0, and after y adds 1, continuesBe sent in the write request that writes next packet in current writing address institute's corresponding stored unit to storage control; If currentY equals Y-1 in writing address (x, y), after all changing the x in current writing address and y into 0, continues to storage controlDevice processed is sent in the write request that writes next packet in current writing address institute's corresponding stored unit.
Concrete, with 12 DDR that comprise shown in Fig. 1, the storage organization that every DDR comprises 8 bank is example, please joinSee Fig. 5 shown in the coordinate schematic diagram of memory cell arrangement order, be that (0,0) represented bank(is if select coordinateThe bank that in Fig. 1, (PMC0, DDR0, bank0) points to) as this initial writing address, external chip is to storage controlDevice PMC0 processed is sent in after the request of the packet that writes a 32B in this bank, and external chip continues to storage control PMC0Be sent in coordinate for the bank(of (0,1) be the bank that in Fig. 1, (PMC0, DDR1, bank0) points to) on write nextThe write request of the packet of 32B, until the whole requests of all packets are complete; If server judge current bank coordinate (x,Y) x in is 11, such as the coordinate of current bank is (11,0), selects to be sent in coordinate to storage control PMC0 and isThe bank relaying of (0,1) is continued the request into next 32B packet; When storage control judge current bank coordinate for (11,7), time, continuing to be sent in coordinate to storage control PMC0 please for what write next 32B packet in the bank of (0,0)Ask.
In addition, the operation such as storage control when data writing, need to refresh in each bank, precharge, due to this refresh,The operation of precharge time used is asked the time of data writing in much larger than storage control to each bank, therefore, and in dataWrite fashionablely, on counter corresponding to each bank, may accumulate and have multiple write requests. For the write request of the each bank of true reflectionAccumulative total situation, each external chip, should after storage control is sent in the write request that writes a packet in certain bankThe counter values that bank is corresponding adds 1; In the time that packet corresponding to this write request really writes this bank, storage control can be toExternal chip returns to a settling signal that writes corresponding to this write request, and external chip receives this writes after settling signal,Counter values corresponding bank is subtracted to 1.
In sum, the initial writing position system of selection of data that the present embodiment two provides, by fashionable whenever there being data to write, willThe mode that repeating query pointer progressively increases according to default step-length is chosen tentative initial writing position, simultaneously by this tentative initial writing position correspondenceCounter values and the mode of maximum comparison determine this initial writing address, and according to first repeating query DDR, PMC repeating query againThe order of bank is asked data writing in each bank, and in the time of request data writing, counter values is added to 1, true in dataJust writing and fashionable counter values is being subtracted to 1, reaching the each bank write request accumulative total of true reflection situation, in each bank, evenly writingData also improve the object of bandwidth availability ratio.
It should be noted that, although describe with storage organization shown in Fig. 1 herein always. But in practical application, storage nodeStructure can be not limited to the storage organization shown in Fig. 1, such as, storage control can be 10; Again such as memory can be11 QDR memories; For another example, the bank on every memory can not be 8, but 4, etc.
Embodiment tri-
Refer to Fig. 6, it shows the structural representation of the initial writing address selecting arrangement that the embodiment of the present invention three provides,This initial writing address selecting arrangement can be applied to the external chip that utilizes same bus to be connected with the storage organization shown in Fig. 1In. This initial writing address selecting arrangement can comprise: command reception module 620 and address selection module 640;
Command reception module 620 writes instruction for receiving the data that storage organization is sent, and storage organization comprises storage controlWith M memory cell, each memory cell has address sum counter separately, and each counter is used for preserving corresponding stored listThe current write request cumulative number of unit;
Address selection module 640 can comprise: address determining unit 642 and the first judging unit 644, as shown in Figure 7.
Address determining unit 642 is for according to the corresponding M of initial writing address last time1Individual memory cell is determined MOD（M1+ N, M) address of individual memory cell is as tentative initial writing address;
The tentative initial writing address institute corresponding stored unit of the first judging unit 644 for judging that address determining unit 642 is determinedCounter in current write request cumulative number whether be the maximum in all counters;
If address determining unit 642 is also for the first judging unit tentative initial writing address institute's corresponding stored of 644 judgement unitCounter in the not all counter of current write request cumulative number in maximum, will fix tentatively initial writing address determineFor this initial writing address;
Wherein, M is more than or equal to 2 integer; M1For being greater than 0, be less than or equal to the integer of M; N be 1 or N be positive integerAnd be not the approximate number of M.
If address determining unit 642 is also for the first judging unit tentative initial writing address institute's corresponding stored of 644 judgement unitCounter in current write request cumulative number be the maximum in all counters, by corresponding tentative initial writing addressM2Individual memory cell is determined MOD(M2+ N, M) individual memory cell is as another tentative initial writing address, wherein, M2=MOD（M1+N,M）。
The first judging unit 644 is also for continuing to judge that address determining unit 642 determines that another tentative initial writing address institute is rightAnswer whether the current write request cumulative number in the counter of memory cell is the maximum in all counters.
This initial writing address selecting arrangement also comprises: split module 662, request sending module 664 and accumulative total module 666, asShown in Fig. 8.
Split module 662 for Data Division to be written is become to one or more packet, wherein, the number that each packet comprisesBe not more than storage control write-once according to amount and operate the maximum amount of data that can write;
Request sending module 664 is for this initial writing address of determining from address determining unit 642, according to predetermined suitableOrder is sent in to storage control the request that writes a packet in current writing address institute's corresponding stored unit successively;
Accumulative total module 666 is accumulated for the current write request to counter. Accumulation module 666 can comprise: accumulative total is singleThe 666a of unit and the second judging unit 666b, as shown in Figure 9.
Accumulated unit 666a is sent in current writing address institute's corresponding stored unit for request sending module 664 to storage controlIn write after the request of a packet, by the current write request accumulative total in the counter of current writing address institute's corresponding stored unitNumber of times adds one;
The second judging unit 666b for judge whether to receive storage control feedback corresponding to right in current writing address instituteAnswer in memory cell, write a packet request write settling signal;
If accumulated unit 666a also receives and writes settling signal for the second judging unit judgement, will write settling signal instituteCurrent write request cumulative number in the counter of corresponding stored unit subtracts one.
Initial writing address selecting arrangement also comprises: sequence generation module 680. Sequence generation module 680 can comprise: obtainUnit 682, computing unit 684 and sequence generating unit 686, as shown in figure 10.
Acquiring unit 682 is for obtaining the current write request cumulative number of individual count device;
Computing unit 684 calculates institute for the current write request cumulative number of the individual count device that obtains according to acquiring unit 682There is the maximum in counter;
Sequence generating unit 686 for the current write request cumulative number of the individual count device that obtains according to acquiring unit 682 andMaximum in all counters that computing unit 684 calculates obtains current write request cumulative number in individual count devicePeaked bit sequence in all counters, the value of T numerical value in bit sequence characterizes in T counterWhether current write request cumulative number is the maximum in all counters, and wherein, T is greater than 0 integer that is less than or equal to M;
Accordingly, the first judging unit 644 judges tentative specifically for the bit sequence obtaining according to sequence generating unit 686Whether the current write request cumulative number in the counter of initial writing address institute's corresponding stored unit is the maximum in all countersValue.
Storage organization comprises that address number is followed successively by 0 to X-1 X memory, and each memory comprises that address number is followed successively by0 to Y-1 a Y memory cell, address determining unit 642, specifically for according to initial writing address (x last time1，y1) obtainMust fix tentatively initial writing address (x2，y2), wherein, (x2-x1）*Y+（y2-y1）=N。
Request sending module 664 comprises: transmitting element 664a and the 3rd judging unit 664b, as shown in figure 11.
It is right that transmitting element 664a starts to be sent in current writing address institute to storage control from this initial writing address (x, y)Answer the request that writes a packet in memory cell;
The 3rd judging unit 664b writes in current writing address institute's corresponding stored unit for one of the every transmission of transmitting element 664aEnter after the request of a packet, judge in current writing address (x, y), whether x equals X-1;
If transmitting element 664b also judges that for the 3rd judging unit 664b in current writing address (x, y), x is not equal to X-1,After the x in current writing address being added to 1, continue to be sent in current writing address institute's corresponding stored unit to storage controlWrite the request of next packet;
If the 3rd judging unit 664b also judges that for the 3rd judging unit 664b in current writing address (x, y), x equalsAfter X-1, continue to judge in current writing address (x, y), whether y equals Y-1;
If transmitting element 664a also judges that for the 3rd judging unit 664b in current writing address (x, y), y is not equal to Y-1,Change the x in current writing address into 0, and after y adds 1, be sent in current writing address institute correspondence to storage control and depositIn storage unit, write the request of next packet;
If transmitting element 664a also judges that for the 3rd judging unit 664b in current writing address (x, y), y equals Y-1,After all changing the x in current writing address and y into 0, continue to be sent in current writing address institute correspondence to storage control and depositIn storage unit, write the request of next packet.
In sum, the initial writing address selecting arrangement that the present embodiment three provides, by fashionable whenever there being data to write, according to upperInferior initial writing position is chosen tentative initial writing position, simultaneously by counter values corresponding this tentative initial writing position withLarge value mode is relatively determined this initial writing address, and in each bank, asks data writing according to predefined procedure, andRequest adds 1 by counter values when data writing, really writes and fashionable counter values is subtracted to 1 in data, reaches true reflection eachBank write request accumulative total situation, even data writing improve the object of bandwidth availability ratio in each bank.
It should be noted that: the initial writing address selecting arrangement that above-described embodiment provides is selecting when initial writing address, only withThe division of above-mentioned each functional module is illustrated, and in practical application, can as required above-mentioned functions be distributed by differenceFunctional module complete, be divided into different functional modules by the internal structure of device, with complete described above all orPartial function. In addition, the initial writing address selecting arrangement that above-described embodiment provides and initial writing address system of selection embodimentBelong to same design, its specific implementation process refers to embodiment of the method, repeats no more here.
One of ordinary skill in the art will appreciate that all or part of step that realizes above-described embodiment can complete by hardware,Also can carry out the hardware that instruction is relevant by program and complete, described program can be stored in a kind of computer-readable recording medium,The above-mentioned storage medium of mentioning can be read-only storage, disk or CD etc.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all the spirit and principles in the present invention itIn, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (8)
1. an initial writing address system of selection, is characterized in that, described method comprises:
Receive the data that storage organization is sent and write instruction, described storage organization comprises storage control and M memory cell,Each memory cell has address sum counter separately, and each counter tires out for the current write request of preserving corresponding stored unitMetering number;
According to the corresponding M of initial writing address last time1Individual memory cell is determined MOD (M1+ N, M) ground of individual memory cellLocation is as tentative initial writing address;
Judge whether the current write request cumulative number in described counter of fixing tentatively initial writing address institute's corresponding stored unit is instituteThere is the maximum in counter;
If so, according to described tentative M corresponding to initial writing address2Individual memory cell is determined MOD (M2+ N, M) individualMemory cell is fixed tentatively initial writing address as another, wherein, and M2＝MOD(M1+ N, M); And continue described another of judgement and fix tentativelyWhether the current write request cumulative number in the counter of initial writing address institute's corresponding stored unit is the maximum in all countersValue;
If not, described tentative initial writing address is defined as to this initial writing address;
Wherein, M is more than or equal to 2 integer; M1For being greater than 0, be less than or equal to the integer of M; N be 1 or N be positive integerAnd be not the approximate number of M.
2. initial writing address system of selection according to claim 1, is characterized in that, describedly tentative initially writes describedEnter after address is defined as this initial writing address, also comprise:
Data Division to be written is become to one or more packet, wherein, described in the data volume that each packet comprises is not more than, depositStorage controller write-once operates the maximum amount of data that can write;
From described this initial writing address, be sent in and currently write ground to described storage control successively according to predefined procedureIn institute's corresponding stored unit, location, write the write request of a packet;
Be sent in current writing address institute's corresponding stored unit and write after the write request of a packet to described storage control,Current write request cumulative number in the counter of described current writing address institute's corresponding stored unit is added to one;
Judge whether to receive the settling signal that writes corresponding to described write request being fed back by described storage control;
If so, the current write request cumulative number in the counter of said write settling signal institute's corresponding stored unit is subtracted to one.
3. initial writing address system of selection according to claim 1 and 2, is characterized in that, described judgement is described tentativeWhether the current write request cumulative number in the counter of initial writing address institute's corresponding stored unit is the maximum in all countersBefore value, also comprise:
Obtain the current write request cumulative number in individual count device;
Calculate the maximum in all counters according to the current write request cumulative number in described individual count device;
Obtain each meter according to the maximum in current write request cumulative number and described all counters in described individual count deviceWhether the current write request cumulative number in number device is the peaked bit sequence in described all counters, described bit sequenceIn the current write request cumulative number that characterizes in T counter of the value of T numerical value whether be in described all countersMaximum, wherein, T is greater than 0 integer that is less than or equal to M;
Accordingly, the current write request accumulative total in the counter of the described tentative initial writing address institute's corresponding stored of described judgement unitWhether number of times is the maximum in all counters, specifically comprises:
Judge that according to described bit sequence current the writing in described counter of fixing tentatively initial writing address institute's corresponding stored unit pleaseAsk whether cumulative number is the maximum in all counters.
4. initial writing address system of selection according to claim 1 and 2, described storage organization comprises that address number successivelyBe 0 to X-1 X memory, each memory comprises that address number is followed successively by 0 to Y-1 Y memory cell, its spyLevy and be, described from described this initial writing address, be sent in current writing to storage control successively according to predefined procedureEnter the write request that writes a packet in institute's corresponding stored unit, address, specifically comprise:
Start to be sent in current writing address institute corresponding stored list to storage control from described this initial writing address (x, y)In unit, write the request of a packet, one of every transmission writes a packet in current writing address institute's corresponding stored unitWrite request after, judge in current writing address (x, y) whether x equals X-1;
If current writing address (x, y) in x be not equal to X-1, after the x in current writing address being added to 1, continue toDescribed storage control is sent in the write request that writes next packet in current writing address institute's corresponding stored unit;
If x equals X-1 in current writing address (x, y), continue judge that whether etc. the middle y of current writing address (x, y)In Y-1;
If y is not equal to Y-1 in current writing address (x, y), change the x in current writing address into 0, and y adds 1After, continue to described storage control be sent in current writing address institute's corresponding stored unit, write writing of next packet pleaseAsk;
If y equals Y-1 in current writing address (x, y), after all changing the x in current writing address and y into 0,Continue to be sent in to described storage control the write request that writes next packet in current writing address institute's corresponding stored unit.
5. an initial writing address selecting arrangement, is characterized in that, described device comprises: command reception module and address choiceModule;
Described command reception module, writes instruction for receiving the data that storage organization is sent, and described storage organization comprises storageA controller and M memory cell, each memory cell has address sum counter separately, and each counter is used for preserving correspondenceThe current write request cumulative number of memory cell;
Described address selection module comprises:
Address determining unit, for according to the corresponding M of initial writing address last time1Individual memory cell is determined MOD (M1+N,M)The address of individual memory cell is as tentative initial writing address;
The first judging unit, for the tentative initial writing address institute's corresponding stored unit that judges that described address determining unit is determinedWhether the current write request cumulative number in counter is the maximum in all counters;
Described address determining unit, if also judge that for described the first judging unit described tentative initial writing address institute correspondence depositsCurrent write request cumulative number in the counter of storage unit is the maximum in all counters, described fixing tentatively is initially writeThe M that address is corresponding2Individual memory cell is determined MOD (M2+ N, M) individual memory cell is as another tentative initial writing address,Wherein, M2＝MOD(M1+N,M)；
Described the first judging unit, also for continuing to judge described address determining unit determines another tentative initial writing address instituteWhether the current write request cumulative number in the counter of corresponding stored unit is the maximum in all counters;
Described address determining unit, if also judge that for described the first judging unit described tentative initial writing address institute correspondence depositsMaximum in the not all counter of current write request cumulative number in the counter of storage unit, initially writes described fixing tentativelyEnter address and be defined as this initial writing address;
Wherein, M is more than or equal to 2 integer; M1For being greater than 0, be less than or equal to the integer of M; N be 1 or N be positive integerAnd be not the approximate number of M.
6. initial writing address selecting arrangement according to claim 5, is characterized in that, described device also comprises: splitModule, request sending module and accumulative total module;
Described fractionation module, for Data Division to be written is become to one or more packet, wherein, each packet comprisesData volume is not more than storage control write-once and operates the maximum amount of data that can write;
Request sending module, for from described this initial writing address, sends out to storage control successively according to predefined procedureSend the write request that writes a packet in current writing address institute's corresponding stored unit;
Described accumulative total module comprises:
Accumulated unit, is sent in current writing address institute corresponding stored list for described request sending module to described storage controlIn unit, write after the write request of a packet, by current the writing in the counter of described current writing address institute's corresponding stored unitRequest cumulative number adds one;
The second judging unit, for judging whether to receive having write corresponding to described write request of described storage control feedbackBecome signal;
Described accumulated unit, if also receive said write settling signal for described the second judging unit judgement, described in inciting somebody to actionThe current write request cumulative number writing in the counter of settling signal institute's corresponding stored unit subtracts one.
7. according to the initial writing address selecting arrangement described in claim 5 or 6, it is characterized in that, described device also comprises:Sequence generation module; Described sequence generation module comprises:
Acquiring unit, for obtaining the current write request cumulative number of individual count device;
Maximum value calculation unit, for the current write request cumulative number meter of the individual count device that obtains according to described acquiring unitCalculate the maximum in all counters;
Sequence generating unit, for current write request cumulative number and the institute of the individual count device that obtains according to described acquiring unitStating the current write request cumulative number that the maximum in all counters that maximum value calculation unit calculates obtains in individual count device isNo is peaked bit sequence in described all counters, and the value of T numerical value in described bit sequence characterizes TWhether the current write request cumulative number in individual counter is the maximum in described all counters, and wherein, T is little for being greater than 0In the integer that equals M;
Accordingly, described the first judging unit, judges institute specifically for the bit sequence obtaining according to described sequence generating unitWhether the current write request cumulative number of stating in the counter of fixing tentatively initial writing address institute's corresponding stored unit is in all countersMaximum.
8. according to the initial writing address selecting arrangement described in claim 5 or 6, described storage organization comprises that address number successivelyBe 0 to X-1 X memory, each memory comprises that address number is followed successively by 0 to Y-1 Y memory cell, its spyLevy and be, described request sending module comprises:
Transmitting element, starts to be sent in current writing address institute to storage control from described this initial writing address (x, y)In corresponding stored unit, write the write request of a packet;
The 3rd judging unit, writes one for one of the every transmission of described transmitting element in current writing address institute's corresponding stored unitAfter the write request of individual packet, judge in current writing address (x, y), whether x equals X-1;
Described transmitting element, if also judge that for described the 3rd judging unit in current writing address (x, y), x is not equal to X-1,After the x in current writing address being added to 1, continue to be sent in current writing address institute's corresponding stored unit to storage controlWrite the write request of next packet;
Described the 3rd judging unit, if also judge that for described the 3rd judging unit in current writing address (x, y), x equalsAfter X-1, continue to judge in current writing address (x, y), whether y equals Y-1;
Described transmitting element, if also judge that for described the 3rd judging unit in current writing address (x, y), y is not equal to Y-1,Change the x in current writing address into 0, and after y adds 1, be sent in current writing address institute correspondence to storage control and depositIn storage unit, write the write request of next packet;
Described transmitting element, if also judge that for described the 3rd judging unit in current writing address (x, y), y equals Y-1,After all changing the x in current writing address and y into 0, continue to be sent in current writing address institute correspondence to storage control and depositIn storage unit, write the write request of next packet.
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