CN103403701B - There is the integrated circuit of programmable circuit system and embedded processor system - Google Patents

Abstract

A kind of integrated circuit can include the processor system being configured to perform program code.Described processor system (202) can be hard-wired and include processor hardware resource (228,222,220,240,242,246,248).Described IC can also include the programmable circuit system (204) being configurable to implement different physical circuit.Described programmable circuit system can be couple to described processor system.Described programmable circuit system can be configured to share the right to use of the described processor hardware resource of described processor system.Described processor system can control each side of described programmable circuit system further, such as, energising and/or power-off, and also control the configuration of described programmable circuit system, to implement the one or more different physical circuit (280) in this Circuits System.

Description

There is the integrated circuit of programmable circuit system and embedded processor system

Technical field

One or more embodiments disclosed in this specification relate to integrated circuit (IC).And more precisely, one Or multiple embodiment relates to a kind of IC including programmable circuit system and embedded processor system.

Background technology

Integrated circuit (IC) can be implemented to perform to specify function.A type of IC is IC able to programme, such as, existing Field programmable gate array (FPGA).FPGA generally includes programmable unit chip arrays.These programmable unit sheets can include, example As, input/output block (IOB), configurable logic block (CLB), special random access memory blocks (BRAM), multiplier, numeral Signal processing block (DSP), processor, timer manager, delay locked loop (DLL) etc..

Each programmable unit sheet generally includes interconnection circuitry able to programme and Programmable Logic Device system.Able to programme Interconnection circuitry generally comprises a large amount of interconnection lines of different length, and these interconnection lines are interconnected by interconnection point able to programme (PIP).Can Program logic circuit system uses programmable element to implement the logic of user's design, and these programmable elements can include, example As, functional generator, depositor, arithmetical logic etc..

Configuration data stream usually, is added by the programming mode of interconnection circuitry able to programme and Programmable Logic Device system Being downloaded in internal configuration memory units, how programmable element is configured by described internal configuration memory units is determined Justice.Configuration data can read (such as, reading) from outside PROM from memorizer maybe can be by external device (ED) write FPGA. Subsequently, collective's state of each memory cell may determine that the function of FPGA.

Another type of IC able to programme is complex programmable logic device or CPLD.CPLD includes using interconnection box matrix Link together and be connected to two or more " functional devices " of input/output (I/O) resource.Each functional device of CPLD Including being similar to two grades of AND/ of structure used in programmable logic array (PLA) and programmable logic array (PAL) device OR structure.In CPLD, configuration data are commonly stored on chip in the nonvolatile memory.In some CPLD, configuration Data are initially stored on the chip in nonvolatile memory, then as initial configuration (programming) sequence a part by under It is downloaded to volatile memory.

For all these IC able to programme, the function of device is controlled with the data bit controlling apparatus function by being supplied to device System.Data bit can be stored in volatile memory (such as, as the static memory cell in FPGA and some CPLD), non- In volatile memory (such as, as the FLASH memory in some CPLD) or in the memory cell of any other type.

Other IC able to programme process layer (such as, metal level) by use and are programmed, and described process layer is programmably By each element interconnection on device.These IC able to programme are referred to as mask-programmable device.IC able to programme can also be in other ways Implement, such as, use fuse technique or antifuse technology.Phrase " IC able to programme " can include but not limited to these devices, And may further include the device of only part programmable, including, such as, special IC (ASIC).Such as, another kind of The IC able to programme of type includes the combination of hard coded transistor logic and Switching Fabric able to programme, and described Switching Fabric able to programme can Programmatically interconnect with hard coded transistor logic.

Some modern IC, including some in various IC discussed above, they include being able to carry out the embedding of program code Enter formula processor.Processor can produce as a part for same nude film, and described nude film includes Programmable Logic Device system System and interconnection circuitry able to programme, the two Circuits System is also referred to collectively as " the programmable circuit system " of IC.It will be appreciated that process In device, the execution to program code is different from IC " programming " or " configuration " that carry out programmable circuit system that can provide. The behavior that programmable circuit system in IC is programmed or is configured, can cause by configuring data in this programmable circuit system Specified different physical circuit systems are implemented.

Summary of the invention

One or more embodiments disclosed in this specification relate to integrated system (IC), more precisely, relate to bag Include the IC of programmable circuit system and embedded processor system.

One embodiment can include that following this IC, this IC include the processor system being configured to perform program code System.This processor system can be hard-wired, and can include processor hardware resource.Described IC can also include joining Put the programmable circuit system for implementing different physical circuit.Described programmable circuit system can be couple to described processor System.Programmable circuit system can also be configured to share the right to use of the processor hardware resource of processor system.

In certain embodiments, processor hardware resource can be to be positioned at input/output (I/O) dress of processor system Put.

In certain embodiments, processor hardware resource can be the memorizer being positioned at processor system.

In certain embodiments, processor hardware resource can be configured to generate interrupt signal be supplied to programmable circuit System and processor system.

In certain embodiments, processor hardware resource can be selectively coupled in integrated circuit be exclusively used in processor Input/output (I/O) pin of system or programmable circuit system.

In certain embodiments, the data generated from processor hardware resource can be provided to be exclusively used in integrated circuit The I/O pin of processor system, and described data genaration is on the data wire being coupled to structure input/output multiplexer, institute State structure input/output multiplexer and be coupled to programmable circuit system.

In certain embodiments, processor hardware resource can be selectively coupled in integrated circuit be exclusively used in processor Input/output (I/O) pin of system or programmable circuit system.

In certain embodiments, the described data generated from processor hardware resource can be provided to integrated circuit special secondary school For the I/O pin of processor system, and described data genaration is in the data wire being coupled to structure input/output multiplexer On, described structure input/output multiplexer is coupled to programmable circuit system.

In certain embodiments, processor system can include that clock unit, described clock unit are configured to generate First clock signal of distribution in described processor system, wherein said clock unit is configured to provide the second control signal To programmable circuit system.

In certain embodiments, processor system can include that clock unit, described clock unit are configured to generate First clock signal of distribution in described processor system, wherein said clock unit is configured to provide the second control signal To programmable circuit system.

In certain embodiments, integrated circuit may further include hardware lock mechanism, described hardware lock mechanism warp Configure the most only to allow the one in processor system and programmable circuit system can control processor hardware resource.

In certain embodiments, processor system or programmable circuit system are only being awarded processor hardware resource The interruption generated by processor hardware resource just can be served during control.

In certain embodiments, programmable circuit system can include subscriber's line circuit, and described subscriber's line circuit supplies via special Programmable circuit system use I/O pin and be communicatively linked to the process node of integrated circuit external, wherein said user electricity Road can be communicatively linked to I/O device via interface programmable circuit system and processor system being coupled, wherein Described process node can access described I/O device via described subscriber's line circuit.

In certain embodiments, programmable circuit system can include subscriber's line circuit, and described subscriber's line circuit is via interface coupling Being connected to processor system, wherein said processor system can be configured to enforcement standard I/O function, wherein said processor system System can be configured to respond to from described subscriber's line circuit via described interface to request, by described standard I/O function It is supplied to described subscriber's line circuit.

In certain embodiments, programmable circuit system can implement physical circuit under the control of processor system.

In certain embodiments, processor system can control the electric power thus supplied of programmable circuit system.

Another embodiment can include a kind of method of shared processor hardware resource.Described method may include that joins Put programmable circuit system to implement different physical circuits；And configure described programmable circuit system with shared processor system The right to use of the processor hardware resource of system, wherein said processor system is hard-wired and is configured to execution program generation Code.

In certain embodiments, described method may further include: receives the processor hardware to processor system and provides The request that source conducts interviews；Determine whether asked processor hardware resource can be used；If the processor hardware money asked Source is available, then: authorizes and accesses the processor hardware resource asked；The processor hardware resource that configuration is asked；And Initialize the operation in the processor hardware resource asked.

Another embodiment can include that following this IC, this IC include the processor system being configured to perform program code System.Described processor system can be hard-wired.Described IC can include programmable circuit system, described programmable circuit system System is configured to implement the physical circuit by specified by configuration data.Described programmable circuit system can be couple to described process Device system.Programmable circuit system can also implement physical circuit system under the control of processor system.

In certain embodiments, processor system can be configured to: by the configuration data specifying physical circuit being added It is downloaded to programmable circuit this physical circuit intrasystem implemented by the configuration memorizer of programmable circuit system.

In certain embodiments, processor system can be configured to: configuration data are loaded into configuration memorizer it Before, at integrated circuit external source, input/output (I/O) device via processor system receives described configuration number According to.

In certain embodiments, the source that processor system can be configured to integrated circuit external exists via I/O device Communicate on communication link, and configuration data can be obtained by this communication link.

Another embodiment can include that following this IC, this IC have the processor system being configured to perform program code System.Described processor system can be hard-wired.Described IC can also include programmable circuit system, described programmable circuit System is configurable to implement different physical circuits according to being loaded onto configuration data therein.Described programmable circuit system Described processor system can be couple to.Described programmable circuit system can carry out electricity under the control of described processor system Power operates, such as, and energising and/or power-off.

In certain embodiments, programmable circuit system can be led to from off-position under the control of processor system Electricity.

In certain embodiments, in response to determining programmable circuit system start-up course completely, processor system can So that configuration data are loaded in the configuration memorizer of programmable circuit system.

In certain embodiments, programmable circuit system can be de-energized under the control of processor system.

In certain embodiments, described integrated circuit may further include described processor system and described able to programme Multiple level translators that Circuits System is coupled, wherein, in response to described programmable circuit system in described processor system System controls lower power-off, and each in the plurality of level translator is placed in known state.

Accompanying drawing explanation

Fig. 1 is the first party illustrating integrated circuit (IC) framework according to an embodiment disclosed in this specification Block diagram.

Fig. 2 is the second party block diagram illustrating the IC according to another embodiment configuration disclosed in this specification.

Fig. 3 is to illustrate according to third party's block diagram of IC in Fig. 2 of another embodiment disclosed in this specification.

Fig. 4 is to illustrate according to the fourth block figure of IC in Fig. 2 of another embodiment disclosed in this specification.

Fig. 5 is to illustrate according to the 5th block diagram of IC in Fig. 2 of another embodiment disclosed in this specification.

Fig. 6 is to illustrate a kind of shared processor hardware resource according to an embodiment disclosed in this specification The first pass figure of method.

Fig. 7 is the 6th block diagram illustrating the system according to another embodiment disclosed in this specification.

Fig. 8 is illustrate a kind of IC electric power management method according to another embodiment disclosed in this specification Two flow charts.

Fig. 9 is illustrate a kind of IC electric power management method according to another embodiment disclosed in this specification Three flow charts.

Figure 10 is to illustrate according to the 7th block diagram of IC in Fig. 2 of another embodiment disclosed in this specification.

Figure 11 is to illustrate according to the eighth block diagram of IC in Fig. 2 of another embodiment disclosed in this specification.

Figure 12 is to illustrate a kind of IC electric power management method according to another embodiment disclosed in this specification 4th flow chart.

Figure 13 is to illustrate a kind of IC electric power management method according to another embodiment disclosed in this specification 5th flow chart.

Detailed description of the invention

Although this specification is summed up with claim, described claims define and are considered the one of novel embodiment Individual or the feature of multiple embodiment, it is believed that, can be by considering that the description of in conjunction with the accompanying drawings be more fully understood that described One or more embodiments.As required, this specification discloses one or more specific embodiment.It will be appreciated, however, that institute State what one or more embodiment was merely exemplary.Therefore, ad hoc structure disclosed in this specification and function detail are not Should be interpreted that it is restrictive, but as just claims according to and also be as representative foundation, in order to instruct Those skilled in the art uses the one or more in substantially any applicable detailed construction in every way Embodiment.Additionally, terms and phrases used herein is not intended with being restricted, but is intended to provide disclosed herein The intelligible description of one or more embodiments.

One or more embodiments disclosed in this specification relate to integrated system (IC), more precisely, relate to bag Include the IC of programmable circuit system and embedded processor system.Programmable circuit system is incorporated to embedded processor system On same IC and (such as) same nude film and/or substrate, this can help described programmable circuit system with described Various processor hardware resource can be shared between processor system.Such as, each as memorizer, interface etc in processor system Plant assembly and/or subsystem, such as, input/output (I/O) device of described processor system, can be for programmable circuit system System uses and can be shared.

The electrical management that one or more embodiments disclosed in this specification are directed in IC, described IC includes processing Device system and programmable circuit components of system as directed.Programmable circuit system can be configured to be energized independent of processor system And/or power-off.The task of processor system can be the power cycle of management programmable circuit system, and described processor system System can control configuration further, such as, controls configuration data be loaded in IC and controlled programmable circuit system In the configuration memorizer of system.Electric power between processor system and programmable circuit system independently makes the processor system can be Operate while the still power-off of programmable circuit system and perform program code.Can be by programmable circuit system with regard to processor hardware resource Uniting for enjoyed this respect, the electrical management of these resources can also be controlled by processor system.

Fig. 1 is the first party block diagram illustrating the IC framework 100 according to an embodiment disclosed in this specification.Frame Structure 100 can be, such as, implements in the IC of field programmable gate array (FPGA) type.As it can be seen, framework 100 can wrap Include some different types of programmable circuits, such as, logic, block.Such as, framework 100 can include the most different able to programme Dice (programmable tile), including many gigabits transceiver (MGT) 101, configurable logic block (CLB) 102, with Machine access memory block (BRAM) 103, input/output block (IOB) 104, configuration and clocked logic (CONFIG/CLOCK) 105, Digital signal processing block (DSP) 106, special I/O block 107(such as, configuration port and clock port), and other able to programme patrol Collect 108, as digital dock manager, A/D converter, system monitoring logic etc..

In some IC, each programmable unit sheet includes programmable interconnection element (INT) 111, described interconnection able to programme Element have guide into and quoted from INT111 corresponding in each adjacent unit sheet standardization connect.Therefore, INT111 implements together The programmable interconnection structure of shown IC.Shown in the example included by Fig. 1 top, each INT111 also include guiding into and quoted from The connection of the programmable logic element in same dice.

Such as, CLB102 can include configurable logic element (CLE) 112, and described configurable logic element can be with warp knit Journey is to implement user logic plus single INT111.In addition to one or more INT111, BRAM103 can also include BRAM Logic element (BRL) 113.Generally, the number of included in dice INT111 depends on the height of described dice. In the embodiment depicted, a BRAM dice has identical height with five CLB but it also may use other numbers (such as, four).In addition to appropriate number of INT111, DSP unit sheet 106 can also include DSP logic element (DSPL) 114.In addition to an example INT111, IOB104 can also include, such as, and two examples I/O logic element (IOL) 115. Those skilled in the art is it will be clear that the actual I/O plate being connected to such as IOL115 is generally not limited to IOL115 Region.

In the example that Fig. 1 is described, the cylindrical region (for dash area shown in Fig. 1) of nude film immediate vicinity is used for joining Put, clock and other control logic.The horizontal zone 109 that thus post extends is in order to be distributed on the whole width of IC able to programme Clock and configuration signal.

Some IC utilizing framework shown in Fig. 1 include that added logic block, described added logic block make the big portion of composition IC The regular columnar structure division divided.Added logic block can be programmable block and/or special circuit system.Such as, it is depicted as The processor block of PROC110 is across CLB and BRAM of some row.

PROC110 may be embodied as hard wired processor, and described hard wired processor is made as a part for nude film, described Nude film implements the programmable circuit system of IC.PROC110 can represent appointing in various different processor type and/or system One, says from complexity, contains from single processor (for instance, it is possible to performing the single core of program code) to having one Or multiple core, module, coprocessor, interface and the complete process device system of fellow.

In more complicated layout, such as, PROC110 can include one or more core, such as, center processing list Unit, cache memory, Memory Controller, unidirectional and/or bidirectional interface, described unidirectional and/or bidirectional interface can configure For being directly coupled to the I/O pin (such as, I/O plate) of IC and/or being couple to the programmable circuit system of IC.Phrase " programmable circuit system " can refer to the programmable circuit element in IC, such as, as herein described various able to programme or configurable Logical timer or dice, and interconnection circuitry, described interconnection circuitry is for according to the configuration number being loaded in IC According to optionally various logic block, dice and/or element being coupled.Such as, being positioned at outside PROC110 shown in Fig. 1 Those parts in portion can be considered a part for the programmable circuit system of IC.

Fig. 1 is intended to illustrate the exemplary architecture that may be used for implementing IC, and wherein said IC includes programmable circuit system (example As, programmable structure) and processor system.Such as, the logical block number in string, the relative width of these row, the number of row With at logical block type included in order, these row, the relative size of logical block, and Fig. 1 top included by interconnection/ Logical implementations, is all purely exemplary.In real ics, such as, no matter CLB occurs in where, generally all wraps herein Include the CLB of more than one adjacent column, with the effective enforcement promoting subscriber's line circuit to design.But, the number of adjacent C LB row can be with Total size variation of IC.Additionally, the size of PROC110 in IC and/or location are for illustration purposes only, and it is not intended to make Restriction for the one or more embodiments disclosed in this specification.

Fig. 2 is the second party block diagram illustrating the IC200 according to another embodiment configuration disclosed in this specification. IC200 can use any one of various different framework to implement, and described different frameworks include being coupled to able to programme The processor system (PS) 202 of Circuits System 204.Such as, IC200 can use frame same or similar with Fig. 1 framework 100 Structure is implemented, but is not necessarily this situation.In general, IC200 illustrate in more detail may be used for by PS202 with The various interfaces that the Circuits System implemented in programmable circuit system 204 is coupled.

In the example shown in figure 2, illustrated PS202 occupies nearly 2/3rds of IC200 nude film, and shown can Programmed circuit system 204 occupies nearly 1/3rd of same nude film.But, Fig. 2 is not intended to represent for the yardstick of IC200. On the contrary, the Fig. 2 provided is in order at descriptive purpose, and it be not intended as disclosed in this specification or The restriction of multiple embodiments.

In general, the hard-wired system in PS202 is embodied as IC200.Various assemblies or module in PS202 are passed through Line (such as, signal or communication link) with arrow couples this aspect, and these arrows are intended to direction or the flow direction that diagram controls. In this regard, the signal shown with the line chart of band direction arrow has generally indicated the source component produced by arrow rather than arrow points to Target element be exerted by the control on this signal.These arrows are typically not intended to indicate one-way flow or the letter of data Number directivity.Despite the presence of direction arrow, signal still may be implemented as two-way signaling or communication link.

In this manual, identical reference marks is for referring to terminal, holding wire, wire and their corresponding letter Number.In this respect, the term in this specification " signal ", " wire ", " connection ", " terminal " and " pin " is the most interchangeable makes With.Should also be clear that term " signal ", " wire " etc. can represent one or more signal, such as, solid conductor is passed through in single position Transmit or the transmission by many parallel conducting wires of multiple parallel position.Additionally, as the case may be, each wire or every noted Individual signal can represent the two-way communication between the two or more assemblies connected by this signal or wire.

As it can be seen, PS202 can include core complex 206.Core complex 206 can include core 208 He 210, floating point unit (FPU) 212 and 214, interrupt request unit (IRQ) 216 and pry control unit (SCU) 218.Core Each in 208 and 210 can include 1 grade of (L1) buffer (not shown) being embedded in.Although it is disclosed herein Embodiment can use any one of various dissimilar processor core of being able to carry out program code and/or FPU, Such as, math co-processor or DSP unit, but core 208 and 210 respectively may be embodied as ARM Cortex^TMThe place of-A9 type Reason device core, each of which has the Instruction Register of 32KB and the data buffer of 32KB.FPU212 and 214 can use energy The NEON of 128 DSP functions based on vector is enough provided^TMMedia format and/or floating-point process engine to be implemented.ARM Cortex^TM-A9 processor core and NEON^TMMedia and/or floating-point process engine all can be from the ARM skill of Britain Camb Art company limited (ARM Holdings of Cambridge, UK) (ARM) buys.

Although diagram for double-core or multiple nucleus system, but, in another embodiment, core complex 206 can wrap Include the monokaryon that can perform program code.In the case, core complex 206 can include being couple to IRQ216 and SCU218 Monokaryon or processor.It addition, be not necessarily to include FPU212 and 214, but single FPU unit can be included as required And this unit is couple to monokaryon.

Referring again to Fig. 2, core complex 206 is couple to various processor hardware resource, such as, 2 grades of (L2) buffers 220 and on-chip memory (OCM) 222.L2 buffer 220 may be embodied as the memorizer of 256KB.OCM222 can also be embodied as The memorizer of 256KB.Core 208 and 210 and FPU212 and 214 can directly access L2 buffer 220 and OCM222.Typically For, the local storage that OCM222 provides can be used for PS202 and/or programmable circuit system 204, such as, programmable circuit system The circuit implemented in system 204.By comparing, L2 buffer 220(it be also memorizer) be used as PS202 buffer.Correspondingly, L2 buffer 220 can store the data of fritter or fraction, such as, 256, and they are the data bit being stored in RAM Effectively copy, such as, performs memory chip.If such as, sending reading for being stored in data in L2 buffer 220 During request, data can read out at L2 buffer 220 rather than retrieve from RAM.

PS202 may further include hardware processor resource, such as, reset unit 224, clock unit 226 and storage Device controller 228.Reset unit 224 can be received from the one or more signals produced at the source outside IC200, such as signal 230.Signal 230 can instruct reset unit 224 to make the one or more assemblies in PS202 and/or PS202 or all component multiple Position.Reset unit 224 can receive request further makes programmable circuit system 204 be energized or the signal of power-off.

Clock unit 226 can receive one or more reference signal, such as signal 232 at the source outside IC200.Time Clock unit 226, for example, it is possible to be embodied as or may be configured to phase-locked loop circuit system synchronized with received signal 232. Clock unit 226 can generate one or more clocks of the one or more different frequencies can being distributed in whole PS202 Signal (not shown).It addition, clock unit 226 can generate one or more clock signals of one or more frequency, described One or more clock signals can be distributed to programmable circuit system 204 and use for the circuit wherein implemented.

Memory Controller 228 can be implemented to and be positioned at or many of IC200 outside (such as, " chip is outer ") Individual different types of RAM communicates.Such as, Memory Controller 228 can be implemented to access and (such as, reads and/or write Enter) various types of memorizeies, include but not limited to, double data rate (DDR) 2, DDR3, the depositing of low-power (LP) DDR2 type Reservoir, either 16,32,16 of band ECC etc..The different memory class that Memory Controller 228 can communicate The list of type is for illustration purposes only and provides out, and this list is not intended form restriction or accomplish exhaustive.

PS202 can also include hardware processor resource, such as, be couple to core switch 236 and programmable circuit system Direct memory access (DMA) (DMA) interface 234 of 204.PS202 farther includes the hardware handles of memory switch 238 type Device resource, its interface being couple in interface 256 (describing in detail in this specification is i.e. interface 256D), OCM222 and Memory Controller 228.

As it can be seen, core switch 236 can between each assembly of PS202 route signal.An embodiment In, core switch 236 can be directly coupled to the internal bus (not shown) of PS202.In this type of embodiment, in PS202 The each miscellaneous part being connected with core switch 236 can be couple to core switch 236 by this internal bus.Example As, other processor hardware resources, such as I/O device (e.g., interface) 240,242,246 and 248, each can be via inside Bus is couple to core switch 236.Internal bus may be embodied as any one of multiple different bus, such as, senior Peripheral bus (APB) etc..

As it was previously stated, PS202 can include hardware processor resource, such as, one or more different types of I/O devices Or interface.PS202 can provide flash memory type I/O device, high-performance I/O device, low performance interface, debug I/O device, and/ Or RAM I/O device.To RAM I/O device in this specification, i.e. Memory Controller 228 is described.

As for the I/O device of additional type, PS202 can include one or more flash interface 240, is shown as 240A in figure And 240B.Such as, one or more flash interfaces 240 may be embodied as being configured to carry out four serial peripherals of 4 bit walks and connect Mouth (QSPI).One or more flash interfaces 240 may be embodied as the interface of the NOR/SRAM type of parallel 8.One or many Individual flash interface 240 may be embodied as being configured to carry out 8 and/or the NAND Interface of 16 bit walks.It will be appreciated that described spy Stationary interface is in order at illustrative not limiting purpose and provides.Other interfaces with not bit widths can be used.

PS202 can include one or more I/O device 242, and the performance level that this device provides is than I/O device 240 more High.Each in I/O device 242A to 242C can be respectively coupled to dma controller 244A to 244C.Such as, one or many Individual I/O device 242 may be embodied as the interface of USB (universal serial bus) (USB) type.One or more I/O devices 242 can be real Execute the interface for gigabit Ethernet type.One or more I/O devices 242 may be embodied as connecing of secure digital (SD) type Mouthful.

PS202 can include one or more I/O device 246, such as, I/O device 246A to 246D, and these devices are carried The performance level of confession is less than I/O device 242.Such as, one or more I/O devices 246 may be embodied as general purpose I/O(GPIO) class The interface of type.One or more I/O devices 246 may be embodied as the interface of universal asynchronous receiver/emitter (UART) type. One or more I/O devices 246 can use the form of the interface of Serial Peripheral Interface (SPI) (SPI) bus type to implement.One Individual or multiple I/O devices 246 can use interface and/or the form of l2C style interface of controller zone network (CAN) type Implement.One or more I/O devices 246 can also use triple timer counter (TTC) and/or WatchDog Timer (WDT) form of the interface of type is implemented.

PS202 can include one or more debugging I/O device 248, such as, processor JTAG(PJTAG) port or connect Mouth 248A and tracking interface 248B.PJTAG port 248A can provide outside debugging interface to PS202.Following the tracks of interface 248B can To provide port for receiving debugging (such as, follow the tracks of) information at programmable circuit system 204, interface will be for will The tune-up data of PS202 sends out to programmable circuit system 204, and an intersection triggers port.The triggering port that intersects makes Obtain the Circuits System in programmable circuit system 204 and can trigger the debugging function in PS202, such as, follow the tracks of.Similarly, Debugging function in the circuit that PS202 implements in can initializing programmable circuit system 204.

As it can be seen, each in I/O device 240,242,246 and 248 can be couple to multiplexer 250.Multiplexer 250 provide the multiple outfans that can be routed directly to or be couple to IC200 external pin, and such as, positioned inside has IC200 Encapsulation in ball.Such as, multiple I/O pins of IC200, such as, and 53 pins, can be by interface 240,242,246 and 248 Shared.Multiplexer 250 can be configured to a part of PS202 for selecting will use in interface 240 to 248 by user Interface, and therefore, this interface is couple to via multiplexer 250 the I/O pin of IC200.

As it can be seen, the signal that I/O device 242 to 248 is couple to multiplexer 250 can also be couple to structure multiplexer Input/output (FMIO) interface 252.Correspondingly, user based on IC200 configures, and the user of more precisely PS202 joins Putting, in I/O device 242,246 and/or 248, any one all can be couple to the electricity able to programme of IC200 via FMIO interface 252 Road system 204.FMIO interface 252, for example, it is possible to include configurable switch, every signal line is both coupled to it, so that letter Number line can be selectively coupled to programmable circuit system 204 according to the state of this switch.FMIO interface 252 and its The switch included is configurable to a part of PS202, such as, via controlling depositor 254, for determining those signals Programmable structure 204 will be delivered to from I/O device 242 to 248.This makes the data from the communication of any one interface 242 to 248 The Circuits System in programmable circuit system 204 can be routed to, to be further processed and/or to monitor.Via being couple to The data that one or more I/O pins of I/O device 242,246 and 248 receive can be by one or more interfaces 256 It is routed to programmable circuit system 204, to be further processed.

FMIO interface 252 makes the data from I/O device 242,246 and 248 output can be supplied to one or more I/O pin, it is provided that give the selected circuit implemented in programmable circuit system 204, such as, subscriber's line circuit system 280, or same Time be supplied to one or more I/O pin and programmable circuit system 204 in the selected circuit implemented.It will be appreciated that for coupling Receiving FMIO interface 252, the circuit implemented in programmable circuit system 204 must be configured by loading and can be formed or implement The configuration data of physical circuit system, just can carry out this operation.

In one embodiment, each in I/O device 240,242,246 and 248 can be configured to generate interruption Signal, it is illustrated that for signal 290.Such as, I/O device 240A to 240B, 242A to 242C, 246A to 246D and 248A to 248B In each all can be configured on signal 290 generate interrupt.As it can be seen, signal 290 is couple to core complex The IRQ216 of 206, and also it is directly coupled to programmable circuit system 204.The interrupt signal 290 being positioned in PS202 is hard Line, such as, permanent wiring.Correspondingly, any one I/O device 240-248 the interrupt signal generated can carry Supply core complex 206 and/or programmable circuit system 204, thereby aid in programmable circuit system 204 and/or core Heart complex 206 uses I/O device 240 to 248.The interrupt signal of each in I/O device 240 to 248, such as, can To be simultaneously supplied to IRO216 and programmable circuit system 204.

Control depositor 254 and can be configured to control each side (if not major part) of PS202.Can be by one Or multiple order writes the running controlling depositor 254 to control or to regulate and control PS202.Such as, in programmable circuit system 204 Circuit can pass through interface (such as, interface 256B) and carry out write operation to controlling depositor 254, will carry out this into one herein Step describes in detail.Control depositor 254 can control or regulate and control following functions, such as, control intellectual property (IP) enable reset, Clock frequency, appointment I/O that setting is generated by clock unit 226 drive intensity, signal by interface route to programmable circuit The state of this FMIO interface 252 during system 204, and other system level function.Control depositor 254 and can regulate and control extra Function, such as, makes PS202 power-off, individually makes the special interface power-off of PS202 or disable, etc..Can be by bus to control Depositor 254 conducts interviews, such as, by not shown for the APB(that control depositor 254 is coupled to core switch 236).

PS202 can also include the one or more interfaces 256 directly coupled with programmable circuit system 204, is depicted as Interface 256A to 256D.In one embodiment, the one or more or total interface in interface 256 all can be according to by ARM AMBA AXI protocol specification (AXI) announced implements.Such as, in interface 256, each all can defer to the 3.0th edition AMBA AXI protocol specification is implemented, and this edition description is incorporated herein in entirety by reference.In general, AXI is a kind of high The high-frequency interface of performance, it is applicable to submicron interconnection.

Referring again to Fig. 2, interface 256A and 256B, such as, each can be implemented to provide two 32 bit ports, this Programmable circuit system 204 is coupled by two passages with core switch 236.Interface 256A may be embodied as General Main and connects Mouthful.Interface 256A, for example, it is possible to for performing from PS202 and/or dma controller therein to programmable circuit system 204 Conventional data is transmitted.Interface 256B may be embodied as general slave interface.Such as, interface 256B may be used for perform PS202 with Conventional data transmission between programmable circuit system 204.

By interface 256A to 256B and core switch 236, the circuit implemented in programmable circuit system 204 is permissible Access the multiple devices in I/O device 240,242,246 and 248.By interface 256A and/or 256B and core switch 236, the circuit in programmable circuit system 204 can directly access OCM222 and further by Memory Controller 228 Access chip external memory, etc..

Interface 256C may be embodied as 64 slave interfaces, and it is by direct for programmable circuit system 204 and core complex 206 are coupled, and more precisely, are directly coupled with SCU218.By interface 256C and SCU218, electricity able to programme The circuit implemented in road system 204 can directly access the L1 buffer of each in core 208 and 210, IRQ216, L2 caching Device 220 and OCM222.Correspondingly, these memorizeies can be read out and/or write by the circuit in programmable circuit system 204 Enter operation, and the interior interruption generating or concluding of core complex 206 can be detected.Such as, interface 256C can provide core The coherent access of heart complex 206, described core complex is applicable to be used as coprocessor by circuit.In the example shown, may be used The soft processor implemented with subscriber's line circuit system 280 form in programmed circuit system 204 can enter via interface 256C with PS202 Row communication.

Programmable circuit system 204 is configurable to directly detect the interruption from I/O device 240,242,246 and 248, Or it is used for detecting the interruption from IRQ216.It will be appreciated that IRQ216 allows programmable circuit system 204 to detect in core again The interruption that the processor produced in compound 206 is special or processor generates.Signal 290 can represent further from electricity able to programme One or more interruptions of road system 204, these interruptions can be supplied to IRQ216 as port or signal；And/or table Show that these interrupt copies can conduct from PS202 and especially from one or more interruption copies of core complex 206 Port or signal are supplied to programmable circuit system 204.

Interface 256D can be implemented to provide multiple, such as, four, 64 slave interfaces.Interface 256D may be used for Mass data between exchange PS202 and the interior circuit implemented of programmable circuit system 204 effectively.As it can be seen, interface The circuit that 256D implements in enabling programmable circuit system 204 accesses OCM222 can be through via memory switch 238 By memory switch 238 and Memory Controller 228 access chip external memory.

It addition, PS202 can include PS voltage detector 292.PS voltage detector 292 can monitor (to be described from power supply For signal 294) entrance voltage source.Predetermined voltage level, PS voltage detector is met in response to determining signal 294 voltage 292 can enable other assemblies one or more by sending control signal (not shown).Such as, in response to determining signal The voltage of 294 is at least minimum voltage level, and PS voltage detector 292 can enable one or more IOB of IC200.Separately In one example, meeting minimum voltage level in response to the voltage determining signal 294, PS voltage detector 292 can open simultaneously Use one or more level translator, it is illustrated that for level shifting circuit system 296.The further function of PS voltage detector 292 To be described referring to remaining accompanying drawing.

IC200 can include that level shifting circuit system 296 is adapted to assist between PS202 and programmable circuit system 204 Signal transmission.Level shifting circuit system 296 helps PS202 to be electrically isolated from programmable circuit system 204, and it is through joining Put the signal being converted to the second voltage level with the signal by the first voltage level.In some cases, the first voltage level with Second voltage level can be different magnitude of voltage.Such as, in some cases, PS202 can use certain electric power signal to enter Row running, the voltage potential that described electric power signal has is different from the electricity of the electric power signal being supplied to programmable circuit system 204 Piezoelectricity gesture.In other cases, PS202 can receive and be supplied to the electric power signal of programmable circuit system 204 and has or should There are one or more electric power signals of identical voltage potential.But, electric power signal can be independently controlled, to the greatest extent The voltage potential of pipe electric power signal is similar or identical, but still suffers from two different power domain.The independence of electric power signal May result in, compared to the electric power signal being supplied to programmable circuit system 204, it is provided that to the electricity of the electric power signal of PS202 A little little variation can be there is in piezoelectricity gesture.Level shifting circuit system 296 makes PS202 can serve as a power domain and programmable circuit System 204 can serve as the power domain that another is different and independent, thus so that programmable circuit system 204 can be independent of PS202 quilt Energising and power-off, such as, when PS202 still remains powered on and operates.

For bringing the potential change in electric power signal, and also for supporting that programmable circuit system 204 can be independent of PS202 carries out this ability of power cycle, and the signal intersected between PS202 with programmable circuit system 204 can pass through Level shifting circuit system 296 is transmitted.By being illustrated as single piece, it should be understood that each interface in the plurality of interface, Such as, FMIO interface 252, follow the tracks of interface 248B, interface 256A to 256D, processor configuration access port (PCAP) 258 and Any other signal of such as clock signal and DMA signal, may each comprise the level represented by level conversion Circuits System 296 Transducer, or transmitted by it.Level shifting circuit system 296 makes between PS202 and programmable circuit system 204 The voltage level of the signal propagated matches.

IC200 can include the level translator one or more the most at the same level in level shifting circuit system 296.Example As, first order level translator can be configured to signal, and such as, system level signal is (such as configuration signal, boundary scan letter Number and/or function) be directly connected to the assembly in programmable circuit system 204, such as, system monitor 262 from PS202, this This will be described in more detail by literary composition.The level translator belonging to first order level shifting circuit system 296 can at PS202 Reset (such as, entering operating mode) and have determined that the electric power of supply programmable circuit system 204 enough makes it enable when operating. The electric power enough making programmable circuit system 204 operate can include for configuring the abundance used by programmable circuit system 204 Electric power, and/or the sufficient electric power that any circuit implemented in making programmable circuit system 204 can operate after enforcement.

Second level level translator can be configured to from programmable circuit system 204, test signal is connected to PS202. Second level level translator can enable following time: PS202 has resetted and programmable circuit system 204 has enough electricity Power and being also configured to implementing circuit system.When disabled, second level level translator can be configured to export default logic High.In another embodiment, second level level translator disabling time can be configured to export default logic low.

Second level level translator can be configured to or can be used for connect PS202 and programmable circuit system 204 it Between subscriber signal.Third level level translator can enable following time: PS202 has resetted and programmable circuit system 204 have enough electric power and configured.In one embodiment, third level level translator can be configured to defeated when disabling Go out default logic low.In another embodiment, third level level translator disabling time can be configured to export acquiescence patrol Collect high.

Fourth stage level translator can be configured between programmable circuit system 204 and PS202 transmission one or Multiple system level signals.Fourth stage level translator can be configured to all moment and all enable, such as, and running 's.

PS202 farther includes PCAP258.As it can be seen, PCAP258 can be couple to Configuration Control Unit 260 and be System watch-dog block 262, these two pieces are respectively positioned in programmable circuit system 204.Although not shown, but PCAP258 can be couple to Core complex 236, so that PS202 can receive configuration data via any device in I/O device 240 to 248 and 228, This data are used during to stay in configuration programmable circuit system 204.

Programmable circuit system 204 can be implemented to include one or more programmable circuit block, and these blocks can make It is coupled together by interconnection circuitry able to programme.Programmable circuit block and interconnection circuitry able to programme can be configured To implement one or more different physical circuit, such as, subscriber's line circuit system based on the configuration data being loaded in IC200 280.It will be appreciated that programmable circuit system 204, except this (will be carried out into one by various hard-wired circuits herein that wherein implement Step describes in detail) outside, it is inoperative or operating, until having data to be loaded in configuration memorizer cause physical power system To implement in programmable circuit system 204, it just can operate.As it has been described above, the configuration data loaded are specified user's electricity Road system 280 is connected to the one or more signals in FMIO interface 252, interruption 290, interface 256 etc..

Configuration Control Unit 260 and system monitor block 262 can be implemented to use the form of hard-wired circuitry.Join Put controller 260 and have the right to write configuration data configuration memory cell, the most physically implement in programmable circuit system 204 By the Circuits System specified by configuration data.System monitor block 262 can perform following functions, such as, analog digital conversion, voltage Monitoring, current monitoring and/or monitoring temperature.

As it has been described above, programmable circuit system 204 can be to be configured to implement to use one of hard-wired circuit form Or multiple I/O device.Such as, jtag interface 264, one or more MGT266A to 266D, peripheral component interconnection are quickly (PCIe) Interface 268, internal configuration access port (ICAP) 270 and secure port 272 can be put into hard-wired circuit, although they It is positioned at the programmable circuit system 204 of IC200.Various I/O devices in programmable circuit system 204 illustrate exemplary connecing Mouthful, for one or more embodiments disclosed in this specification, described interface can carry out implementing and be not intended to be limited Property processed or formed limit.

Such as, configuration data can be loaded in IC200, and is received by Configuration Control Unit 260.In one embodiment, Configuration data can be received by PS202, and described PS can control the configuration process of IC200.Configuration Control Unit 260 is permissible The configuration data received via PCAP258 from PS202 are loaded in the configuration memorizer (not shown) of IC200.As loaded Specified by particular configuration data in the configuration memorizer of IC200, can implement in programmable circuit system 204 or be formed Different physical circuits, such as, subscriber's line circuit system 280.It will be appreciated that owing to employing hard-wired circuitry, by this Mode loads the configuration data initial configuration without programmable circuit system 204.Implement in programmable circuit system 204 Circuit, despite physical circuit, but they still can be sometimes called " soft " because being loaded with configuration data, is following Aspect, Circuits System is to be formed rather than hard-wired or be otherwise secured in programmable circuit system 204 In IC200, this is different from PS202.

IC framework shown in Fig. 2 contributes to cooperation and uses programmable circuit system 204 He under various multi-forms PS202, described form is beyond one's reach in other cases.Subscriber's line circuit system 280 can be by above-mentioned various interfaces Either interface and be couple to PS202.Can realize directly accessing via interface 256, but, can be helped by FMIO interface 252 Help and realize the further access to PS202.In an example, programmable circuit system 204 can be couple to have to define connect One or more external treatment nodes of mouth, such as, no-fix process node on IC200.Programmable circuit system 204 can To pass through, such as, the I/O pin that be reserved for programmable circuit system 204 uses accesses external treatment node.Able to programme Circuits System 204 can also access one or more I/O device via interface 256, such as, and I/O device 240 to 248 and/or deposit Memory controller 228.

In another example, PS202 can be configured to be supplied in programmable circuit system " standard I/O " function The circuit implemented in 204.PS202, for example, it is possible to be configured to load and perform to be inputted (stdin), standard output by standard (stdout) and/or standard error (stderr) function composition storehouse, this storehouse can as core complex 206 in execution behaviour Make the part of system for.In programmable circuit system 204 implement subscriber's line circuit system 280 can be configured to through Called or accessed the standard I/O function provided by core complex 206 by one or more interfaces 256.By making electricity able to programme Circuits System (such as, soft processor) in road system 204 can access standard I/O function from PS202, in programmable circuit system The expense that 204 endogenous causes of ill are implemented standard I/O function and produced generally can be implemented by standard I/O in holding PS202 and be able to Overcome.This makes not as controller that is original complicated but that more simplify can be implemented in programmable circuit system 204.

Fig. 3 is to illustrate according to third party's frame of IC200 in Fig. 2 of another embodiment disclosed in this specification Figure.Fig. 3 show the abstract view of IC200, and it depicts the operation of selected processor hardware resource.In Fig. 3, I/O device 305 and 310 are intended to indicate that any two device in I/O device 242 to 248, such as, 242A to 242C, 246A to 246D and/ Or any two in 248A to 248B.Additionally, for purposes of illustration only, shown I/O device 305 and 310 is via core switch 236 are coupled with core complex 206.Figure does not shows that device (such as, L2 buffer 220 He in PS202 OCM222) the various memorizeies that exchange data are passed through.Similarly, shown interface 256 is the various interfaces described with reference to Fig. 2 Typically represent.Such as, the one or more interfaces during interface 256 can represent interface 256A to 256D.

As it can be seen, PS202 can include multiple switch 315 and 320, signal can optionally be filled by they from I/O Put 305 and 310 be couple to I/O pin 325 or be couple to FMIO interface 252.Although not shown, it is to be understood that by the I/ of PS202 The each wire that O device (I/O device 242 to 248) and multiplexer 250 are coupled can be tradable, as shown in Figure 3. In one embodiment, it is provided that to the configuration data of PS202, such as, it is loaded in Fig. 2 the data controlled on depositor 254, can To determine that I/O device 305 and/or I/O device 310 is coupled to I/O pin 325 and is also coupled to FMIO interface 252.Ying Liao Solving, each device in I/O device 242 to 248 can be configured to be couple to I/O pin 325 or be couple to independently FMIO interface 252.

Switch 315 and 320 may be embodied as any one of multiple known switched circuit, such as, multiplexer etc..When opening When I/O device 305 is couple to I/O pin 325 by pass 315, I/O device 305 can be couple to external treatment node 330.At Fig. 3 In shown example, I/O pin 325 can be specially for PS202.In this regard, I/O pin 325 can be couple to multiplexer 250(is not shown) and cannot be for programmable circuit system 204 or (such as) subscriber's line circuit system 280.When switch 315 solution Except I/O device 305 and when coupling of I/O pin 325, I/O device 305 is couple to FMIO interface 252 and (such as) electricity able to programme The selected circuit implemented in road system 204 and programmable circuit system 204, such as, subscriber's line circuit system 280.

Similarly, when switching 320 and I/O device 310 being couple to I/O pin 325, outside I/O device 310 can be couple to Portion processes node 335.When switch 320 releasing I/O device 310 and when coupling of I/O pin 325, I/O device 310 is couple to FMIO interface 252 and the selected circuit of enforcement, example in (such as) programmable circuit system 204 and programmable circuit system 204 As, subscriber's line circuit system 280.In another embodiment, when serving data to external treatment node 330 and 335, data By switch 315 and 320 regenerations and subscriber's line circuit system 280 can be simultaneously provided to via FMIO interface 252.

Switch 315 and 320 can operate independently from each other.Correspondingly, I/O device 305 can be couple to I/O pin 325, I/O device 310 is couple to FMIO interface 252 simultaneously.Similarly, I/O device 305 can be couple to FMIO interface 252, simultaneously I/ O device 310 is couple to I/O pin 325.In other instances, I/O device 305 and 310 all can be couple to I/O pin 325, Or, all can be couple to FMIO interface 252.

External treatment node 330 and 335 can be multiple systems, the electricity being configured to use special interface to communicate Any one of road, calculating system.Such as, external treatment node 330 and/or 335 can implement l2C style interface, CAN connects Mouth, Serial Peripheral Interface (SPI) (SPI) etc..The interface of external treatment node 330 and/or 335 can be couple to pin 325.As above institute Stating, pin 325 can be couple to one or more I/O device 305 and 310 via multiplexer 250.

By accurately configuring PS202, the subscriber's line circuit system 280 of 204 instantiations in programmable circuit system can be led to Cross FMIO interface 252 be couple to the one in I/O device 305 and 310 or be each coupled to.In this way, subscriber's line circuit system System 280 can collaborative with I/O device 305 and/or 310 use, simultaneously without coupling the exterior I/O pin of IC200, such as, and electricity Road plate level trace etc., can the I/O pin being exclusively used in the I/O pin of PS202 and be exclusively used in programmable circuit system 204 it Between route data.

In one embodiment, subscriber's line circuit system 280 can be couple to FMIO interface 252.Such as, switch 315 is permissible It is in the state that I/O device 305 is couple to FMIO interface 252.Subscriber's line circuit system 280 can be via FMIO interface 252 coupling Receive I/O device 305, or by interface 256 and be couple to this I/O device by means of core switch 236.Therefore, it is input to I/O device 305 and/or the data exported from this device can carry out routeing and being processed by it by subscriber's line circuit system 280. Subscriber's line circuit system 280 can be couple to I/O pin 340 further.I/O pin 340 can be special for programmable circuit system 204 use, and herein, it just cannot be for PS202.Such as, data can receive via I/O pin 340, user It is processed in Circuits System 280, and is provided to I/O device 305.Similarly, the data received from I/O device 305 are permissible It is processed and output to I/O pin 340 by subscriber's line circuit system 280.

Such as, subscriber's line circuit system 280 the process data performed also refer to, and revise the data received and export Amended data, or, assess the data received for particular characteristics and datarams that output receives is specific This indication signal of characteristic.In the case of the data that monitoring receives, in addition to any indication signal, the data received Can also export at subscriber's line circuit system 280.

In an example, subscriber's line circuit system 280 can be configured to by via FMIO interface 252 from I/O device 305 The data received are the second form or agreement from the first form or protocol conversion.Received data can be by subscriber's line circuit system System 280 process is to format according to the first agreement, and exports with data after the process in the second different agreement.Number after process According to exporting from pin 340.

In another example, by expansion, the data received in subscriber's line circuit system 280 can be modified. Such as, subscriber's line circuit system 280 can be configured to timing information, such as, and timestamp, adds to and couples from I/O pin 340 To process in the data received via this pin at node.From processing the Ethernet data bag that node receives, for example, it is possible to Expand with timestamp, and export from subscriber's line circuit system 280 as data after processing.Subscriber's line circuit system 280 can be by Data arrive I/O device 305 via FMIO interface 252 and switch 315 output.In another example, subscriber's line circuit system 280 can So that data after process are exported PS202 via interface 256, and these data are supplied to I/O dress by means of core switch 236 Put 305.

In another example, the data received by subscriber's line circuit system 280 can be for the spy in received data Determine predetermined properties to process, such as, be estimated.In response to predetermined properties being detected, subscriber's line circuit system 280 can generate Notification signal, this signal can export and be supplied to I/O pin 340 or interface 256.Subscriber's line circuit system further can be through joining Put by FMIO interface 252, notification signal is exported one or both in I/O device 305 or 310, described I/O device It is couple to FMIO interface 252 respectively via each self-corresponding switch 315 and/or 320.

Fig. 4 is to illustrate according to the fourth block of IC200 in Fig. 2 of another embodiment disclosed in this specification Figure.Fig. 4 show the abstract view of IC200, and it shows the Circuits System (user e.g., implemented in programmable circuit system 204 Circuits System 280) enjoying processor hardware resource (e.g., the I/O device 305 of PS202).Described with reference to FIG. 3, for saying For the sake of bright succinct convenience, in IC200, there is one or more assembly not shown.Such as, FMIO interface 252 not shown in Fig. 4, open Close 315 and 320 and programmable circuit system 204 in other assemblies various.

In the example shown in fig. 4, appointing during I/O device 305 can represent I/O device 240,242,246 and/or 248 What one.In general, PS202 and programmable circuit system 204 need when sharing I/O device 305 to use a kind of locking mechanism Indicate when I/O device 305 can be used and indicate I/O device 305 the most unavailable further.In example shown in Fig. 4, can A kind of hardware lock mechanism it is implemented with in programmed circuit system 204.When subscriber's line circuit system 280 is awarded I/O device 305 During control, subscriber's line circuit system 280 can access I/O device 305 by interface 256 and core switch 236.Work as core Heart complex 206, the or when process wherein performed is awarded the control to I/O device 305, core complex 206 can be through Communicated by one or more memorizeies (not shown) and core switch 236.

As it can be seen, lock circuit 405 can be implemented in programmable circuit system 204.Lock circuit 405 can have One is defined interface, and by this interface, subscriber's line circuit system 280 can communicate with PS202.Such as, core complex 206 Can communicate with lock circuit 405 via interface 256.Suitable signal can be set up in programmable circuit system 204 Link, thus interface 256 is coupled with locking mechanism 405.By shared by programmable circuit system 204 and PS202 I/O device 305, can be associated with particular register, such as, is positioned at the depositor 410 of lock circuit 405.Lock circuit 405 can implement exclusive access, so that only one of which entity (such as, the particular electrical circuit in programmable circuit system 204, A kind of particular thread in core complex 206 or process etc.) access right to I/O device 305 or use can be awarded Power.Exclusive access is referred to as " load store is exclusive " function.

In the example shown, it is considered to situations below, wherein the I/O device 305 of the type such as Ethernet, UART will be for core complex 206 and subscriber's line circuit system 280 shared.Lock circuit 405 can include depositor 410, and this depositor is exclusively used in tracking I/O State when device 305 is enjoyed, such as, ownership or control.It is stored in the value in depositor 410, for example, it is possible to instruction I/O device 305 is available or busy.In one embodiment, that be associated and/or uniquely identify out be awarded right The identifier of the entity of I/O device 305 control can also be stored in depositor 410.Therefore, subscriber's line circuit system 280 or Whenever core complex 206 needs the control to I/O device 305, and the entity needing control can be from locking electricity The request control to I/O device 305 at road 405.

When request control I/O device 305 for the time being be available when, lock circuit 405 can be awarded with to request entity Give the control to I/O device 305 and be used as the response to request entity.Such as, lock circuit 405 can return certain value or Signal, described value or signal designation request entity herein below: this request entity has been received by the control to I/O device 305 Power.Additionally, lock circuit 405 can automatically store and store in response to request entity in depositor 410 with I/O device 305 certain value being associated, it is no longer available that this value indicates I/O device 305.As mentioned above, it is intended that the reality of control is awarded The identifier of body can also be stored in depositor 410.Therefore, ask same resource (such as same place when two entities simultaneously Reason device hardware resource, e.g., I/O device 305) time, only a request entity can be awarded the access right to asked resource.

When no matter lock circuit 405 (is positioned at PS202 from other entities and is also in programmable circuit system further In 204) place is when receiving the request to I/O device 305 control, and when the depositor 410 of I/O device 305 indicates I/O When device 305 is unavailable, lock circuit 405 can be responded and indicate for disabled other of I/O device 405 with mistake or content.When When having the entity no longer control right request of control to I/O device 305, this entity can notify lock circuit 405.As Response, lock circuit 405 can store instruction I/O device 305 in depositor 410 can value, thus discharge request entity Control to I/O device 305.Additionally, any identifier in also being stored in depositor 410 and for entity can be eliminated Or erasing.

As it can be seen, interrupt signal can be transferred to programmable circuit system 204 also via signal 290 from I/O device 305 It is transferred to core complex 206.I/O device 305 can be configured to, and (depends on I/O device 305 in response to various events Particular type and performed affairs or operation), trigger the interruption via signal 290.As it has been described above, I/O device 305 is permissible Being couple to hardwired interrupt signal (being labeled as signal 290), this signal can be supplied to core complex 206 and be supplied to compile Journey Circuits System 204.May cause to I/O device and generate the event instance interrupted, can include, lead to the most therewith from I/O device 305 The external treatment node of letter receives data, from I/O device 305 to the request timed out of ppu node, etc..

On signal 290, generate interruption in response to I/O device 305, there is the specific reality of control to I/O device 305 Body at that time can be according to responding by needs.Such as, when subscriber's line circuit system 280, there is the control to I/O device 305 Time, subscriber's line circuit system 280 can serve this interruption.Core complex 206, such as, any process wherein performed is permissible Ignore this interruption.Similarly, when the process performed in core complex 206 has the control to I/O device 305, this mistake Journey or another process can serve this interruption.Subscriber's line circuit system 280 can ignore this interruption.

In the case of shown in Fig. 4, the I/O device of PS202 is total to by the Circuits System implemented in programmable circuit system 204 Enjoy.In another embodiment, programmable structure 204, such as, and subscriber's line circuit system 280, can give I/O device 305 Exclusive control.In the case, i.e. programmable circuit system 204 has the exclusive control to I/O device 305, it is not necessary to Locking mechanism.PS202 does not attempts to obtain the control to I/O device 305, unless, such as, programmable circuit system 204 quilt Close.

Fig. 5 is to illustrate according to the 5th square frame of IC200 in Fig. 2 of another embodiment disclosed in this specification Figure.Fig. 5 show the abstract view of IC200, and it shows the Circuits System (user e.g., implemented in programmable circuit system 204 Circuits System 280) enjoying processor hardware resource (showing the I/O device 305 of PS202).Facilitate for illustrative simplicity See in IC200, have one or more assembly not shown.Such as, FMIO interface 252 not shown in Fig. 5, switch 315 and 320 and Other assemblies various in programmable circuit system 204.

Fig. 5 show an example of a kind of hardware lock mechanism, and wherein Memory Controller 228 can serve as locking machine Structure, for authorizing the control to I/O device 305.Memory Controller 228 can serve as locking mechanism further, for really Which entity fixed can access the memorizer outside IC200, and described memorizer is couple to IC200 via Memory Controller 228, Such as, externally-located ram set.

Memory Controller 228, for example, it is possible to be configured to implement the exclusive function of load-store.It is different from utilization to be positioned at Depositor (that situation of Fig. 4 lock circuit) in programmable circuit system 204, for each I/O device, Memory Controller 228 can utilize the storage position in the memorizer being positioned at outside IC200, including Memory Controller 228 itself, they To be shared with programmable circuit system 204 by PS202.Therefore, it is different to the locking being positioned at programmable circuit system 204 Circuit sends request, subscriber's line circuit system 280 and core complex 206 and can directly ask place to Memory Controller 228 The control of reason device hardware resource (such as, I/O device 305 and/or Memory Controller 228).

Request entity, such as subscriber's line circuit system 280 and core complex 206, can be generally as described in reference diagram 4 Like that, the request control to I/O device 305.But, to the request of control and the notice of release control power, can be by Guide to Memory Controller 228.As it has been described above, in one embodiment, it is positioned at IC200 outside and Memory Controller 228 The RAM being coupled to can also be shared by PS202 and programmable circuit system 204.Therefore, the request to control still may be used To be directed to Memory Controller 228.As it has been described above, when programmable circuit system 204 is endowed I/O device 305 or deposits During the exclusive access right of memory controller 228, such as, it is not necessary to utilize any locking mechanism, because during the running of IC200, Control the most dynamically will not change between PS202 and programmable circuit system 204.

In another embodiment, the task of core complex 206 can be locked out distributing to the I/O of specific request entity Device.As it has been described above, in interface 256 one, such as, 256C, can provide to Circuits System, such as subscriber's line circuit system 280 Coherent access to core complex 206.By interface 256C, subscriber's line circuit system 280 is it can be seen that the inner buffer of PS202 Device, such as, L1 buffer, L2 buffer 220 and OCM222.By using the interface 256C providing continuity, programmable circuit System 204, and the load store that more precisely subscriber's line circuit system 280 can utilize core complex 206 built-in is exclusive Function, it is possible to provide another form of hardware lock mechanism, it may be used for I/O device 305(is included I/O device 240) and/or Memory Controller 228 share in.Such as, the storage position in L1 buffer and/or L2 buffer 220 can For the availability following the tracks of I/O device (either I/O device 305 and/or Memory Controller 228).

Fig. 6 is the method 600 illustrating a kind of shared I/O device according to an embodiment disclosed in this specification First pass figure.More precisely, method 600 illustrates an embodiment, wherein can utilize the coarseness to I/O device altogether Enjoy.Method 600 can be implemented by the IC described in this specification, it may for example comprise is couple to the IC of the PS of programmable circuit system.

In embodiment shown in method 600, the one or more subscriber's line circuits implemented in programmable circuit system are configured To share the processor hardware resource of PS with one or more processes of execution in the core complex of PS.Such as, able to programme In Circuits System, soft processor, such as, it is purchased from company of match SEL of San Jose city (Xilinx, Inc.of San Jose, California) MicroBlaze^TMSoft processor, may be implemented as, such as, subscriber's line circuit system 280.Soft Processor can be coupled to hardware lock mechanism, and no matter this hardware lock mechanism is to implement in programmable circuit system, or Being implemented by core complex, wherein soft processor is via providing the coherent interface accessed to couple with described core complex, or It is to be implemented by Memory Controller.

Processor hardware resource can be for described in the I/O device 240 to 248 of reference PS and/or Memory Controller 228 Any one in resource.Such as, the processor hardware resource being shared can be flash type interface (e.g., QSPI) and The interface of row NOR/SRAM type, NAND Interface etc..In another example, processor hardware resource can be USB Type Interface, the interface of ethernet type, the interface of SD type, the interface etc. of UART type.The I/O device with reference to Fig. 2 can be shared Any one of various I/O type of device described in 240 to 248.Furthermore it is possible to share Memory Controller 228, to help PS and programmable circuit system share the RAM being positioned at outside chip.

Therefore, method 600 may begin at step 605, wherein locking mechanism can monitor from various entities send right The control request of the processor hardware resource of PS.The entity that can send request can include enforcement in programmable circuit system Circuit (such as, subscriber's line circuit system 280 and/or soft processor), or PS core complex in perform process.In step In 610, locking mechanism can receive the request to selected processor hardware resource access right at request entity.

In step 615, locking mechanism may determine that whether selected processor hardware resource can be used.Selected in response to determining Processor hardware resource is unavailable, and such as, on the jump, method 600 may be advanced to step 620.In step 620, locking Mechanism can respond request entity, and the selected processor hardware resource of instruction is the most on the jump and the most unavailable.Step 620 it After, method 600 can jump back to step 605, continues the monitoring further request to the processor hardware resources control of PS.

In response to determining that selected I/O device can be used, method 600 can continue to step 625.In step 625, in response to Locking mechanism determines that selected processor hardware resource can be used, and locking mechanism can authorize its control to respond request entity.Lock Determine mechanism and can notify request entity herein below: selected processor hardware resource can be used, and provides selected processor hardware The control in source has been delegated this request entity.Additionally, selected processor hardware resource mark can be busy by locking mechanism. In one embodiment, locking mechanism can store the mark of request entity, or its instruction further.In this regard, locking machine Structure can be configured to only respond request selected processor hardware resource to be discharged from request entity, unless authorized control Power can damage the policy being intended for reducing and/or eliminate mistake (such as, time limit etc.).

In act 630, request entity can optionally configure selected processor hardware resource.Situation shown in step 630 In, for two or more different entities of the control enjoyed processor hardware resource, shared processor hardware resource Different configurations can be carried out.For example, it is contemplated that situations below, UART can be with any one speed in multiple different pieces of information speed Rate communicates.First request entity, such as, the process performed in core complex, it is possible to use UART comes outside with first Process node to communicate with the first data rate (such as, 9600 baud rate).The intrasystem supple-settlement of programmable circuit of IC Device can utilize same UART to enter with different the second data rates (such as, 1200 baud rate) from the second external treatment node Row communication.

Therefore, on the one hand, request entity must first determine selected I/O device be appropriately configured the most as required for Communicate.Such as, required I/O device can be configured to use different from the request entity desired rate that control is awarded Data rate communicate.In the case, request entity must configure processor hardware resource and enters with desired data speed Row communication.

In step 635, in the case of processor hardware resource is appropriately configured, request entity can be with Initialize chosen Operation in processor hardware resource.In step 640, required processor hardware resource can be that request entity performs operation. Such as, request entity can instruct UART from target destination or to process Node extraction certain amount of data.Ask in response to this, UART can extract requested data.In step 645, selected processor hardware resource can generate interruption.This interruption is with letter Number informing request entity, operate executed, such as, in response to performed operation, data can use.

In step 650, interrupting in response to this, request entity can be retrieved and be performed operation by selected processor hardware resource And any data brought.If such as, request entity is the intrasystem soft processor of programmable circuit, then soft processor Can be served this interrupt, and retrieve data.In the case, core complex will recognize that, does not provides selected processor hardware Any process that source performs in making any request and/or core complex is all without providing the processor hardware sending interruption The control in source.Therefore, core complex can ignore the interruption of generation, thus permission programmable circuit intrasystem circuit system System serves interruption.Similarly, when core complex or process therein are request entity, the process in core complex Interruption can be served, and the intrasystem soft processor of programmable circuit can ignore this interruption.Soft processor, for example, it is possible to Knowing, described soft processor does not have the controller to the particular processor hardware resource sending interruption.

In step 655, request entity can discharge selected processor hardware resource.Such as, request entity can be to Locking mechanism sends releasing request.As response, locking mechanism can identify and (such as, be awarded selected place from request entity The entity of control of reason device hardware resource) releasing request that produces of place, and in step 660, selected processor hardware is provided Source marking is available.After step 660, method 600 can jump back to step 605, and continues to monitor the place to obtaining in PS The further request of reason device hardware resource control.

As it has been described above, Fig. 6 show between PS and programmable circuit system the one of the processor hardware resource sharing PS Coarseness method.In another embodiment, this sharing can be more fine-grained.In the example shown, it is considered to situations below, its The one or more processes performed in middle core complex are via selected processor hardware resource (such as UART interface or Ethernet Interface) communicate with particular procedure node.The Circuits System implemented in programmable circuit system, such as, soft processor, it is possible to To be configured to communicate with same process node via same required processor hardware resource.

In this case, it is possible to utilize substantially the same shared mechanism, such as locking mechanism.It is different from every time to institute The control selecting processor hardware resource reconfigures selected processor hardware resource when changing, both request entities can To use identical parameters to communicate with processing node.Such as, selected processor hardware resource is being held in by core complex When the process of row and programmable circuit system access and change, its configuration can remain constant or static state.Can The process performed in programmed circuit system and core complex can be by selected processor hardware resource with identical data Speed communicates with external treatment node.Therefore, when implementing fine granularity sharing method, it is not necessary to perform the step 630 of Fig. 6.

Fig. 6 also describes an embodiment, and wherein interrupt signal is used to notify have the control to processor hardware resource The special entity herein below of system power: data can use from processor hardware resource or specific operation completes to process.? In another embodiment, can be with the interrupt mechanism described in poll replacement.Such as, control to processor hardware resource has been awarded The entity of system power can be configured to polling processor hardware resource, such as, in order to checks the state of processor hardware resource, and Rather than waiting for notice or interrupt signal.The entity being possessed of control power can termly, continuously, or every now and then consulting processor hard Part resource, to determine the state of affairs or the operation just performed.

As it has been described above, one or more embodiments include the IC with multiple different power domain, these power domain help real Existing electric power independence between PS and programmable circuit system.Fig. 7 to Figure 10 collectively illustrates each side of electrical management in IC Face, wherein PS operates in the first power domain, and described first power domain and the second power domain are the most independent, described second electricity In power territory, running is programmable circuit system.Therefore, programmable circuit system can be de-energized independent of PS.An enforcement In example, PS can control energising and/or the power process of programmable circuit system.

In view of programmable circuit system has the ability to carry out power cycle independent of PS, power management capabilities can be included in can During in the energising of programmed circuit system and power-off these two one or two, the management to processor hardware resource.It addition, Power management capabilities can include the management to following relation: the processor hardware resource at PS is led to external treatment node Any relation can set up between both during letter, such as, when communication is route by programmable circuit system.

Fig. 7 is the 6th block diagram illustrating the system 700 according to another embodiment disclosed in this specification.As Shown in figure, system 700 can include IC705, power supply 730, and one or more switch, show switch 735,740 and 745.IC705 can substantially implement as described in the IC described in reference to Fig. 1 and Fig. 2.But, Fig. 7 shows the sketch of IC705 To be shown more clearly that power management capabilities.Correspondingly, IC705 can include PS710 and programmable circuit system 715.One In individual embodiment, programmable circuit 715 can be implemented to use the form of FPGA.PS710 and programmable circuit system 715 can To be depicted as 720A to 720C by one or more level translator 720() and be coupled together.

Power supply 730 can generate multiple electric power signal, such as electric power signal 750,752 and 754.In one embodiment, Each in electric power signal 750 to 754 can have different voltage potential.As it can be seen, electric power signal 750 to 754 coupling Receive the PS voltage detector 712 in the PS710 of IC705.

Each in electric power signal 750 to 754 can also be respectively coupled to the one switching in 735 to 745.Switch 735 to 745 can be configured to optionally electric power signal 750 to 754 be passed to the structure in programmable circuit system 715 Voltage detector 725.In response to the control signal 756 generated by PS710, each in switch 735 to 745 can be with selectivity Electric power signal 750 to 754 is passed to structure voltage detector 725 by ground.In embodiment shown in the figure 7, PS voltage detecting Device 712 can generate control signal 756.When switching 735 to 745 Guan Bi, electric power signal 750 to 754 travels to electricity able to programme Road system 715.Upon opening, the coupling of switch 735 to 745 releasing electric power signals 750 to 754 and programmable circuit system 715.

PS voltage detector 712 can be configured to monitor electric power signal 750 to 754 and determine each electric power signal When 750 to 754 meet one or more different voltage threshold, hereafter this will be described in further detail.As it can be seen, PS voltage detector 712 is couple to electric power signal 754 two positions.PS voltage detector 712 can be at power supply 730 and switch Position between 745 and the position between switch 745 and structure voltage detector 725 are couple to electric power signal 754.

Electric power signal 750 may be embodied as the electric power signal of 1.2 to 1.8 volts, and the I/O that it may be used for IC705 carries For electric power.Electric power signal 752 may be embodied as the electric power signal of 1.8 volts, and it may be used for providing pre-driver electricity to IC705 Pressure and bias.Such as, electric power signal 754 may be embodied as 1 Volt power signal, and it may be used for supplying the logic electricity of IC705 Road system.Described example and value for illustrative purposes, and similarly, be not intended as in this specification disclosing one or The restriction of multiple embodiments.

Level translator 720 can be implemented with reference to as described in the level shifting circuit system 296 in Fig. 2.Such as figure Shown in, level translator 720 can be couple to electric power signal 754 two positions, such as, before switch 745 and as opening Close the outfan of 745.In general, each in switch 735 to 745 will have a certain resistance causing voltage drop so that The voltage of the outfan of each switch will be less than the electric power signal inputted as this switch.Therefore, two power domain be intended to In the case of identical voltage operates, owing to switch 735 to 745 has resistance and other factors one or more, therefore carry The voltage of the electric power signal supplying each power domain can fluctuate.Level translator 720 may result in these in voltage Fluctuation, for transmission letter between the first power domain (that is, PS710) and the second power domain (that is, programmable circuit system 715) Number.

As it can be seen, programmable circuit system 715 can also include the voltage detecting showing structure voltage detector 725 Device.Structure voltage detector 725 can detect when each in signal 750 to 754 reaches predetermined voltage level and make Signal 758 is generated for response.Signal 758 can be supplied to PS710 via level translator 720A.Such as, level translator 720A may be embodied as fourth stage level translator.Although it will be appreciated that not shown, but electric power signal can be from PS voltage detecting Device 712 or from other components distributions one or more among PS710.Similarly, electric power signal can be from structure voltage detector 725 or from other components distributions one or more programmable circuit system 715.Although it addition, being positioned at programmable circuit system In system 715, but structure voltage detector 725 can be embodied as together with one or more other system level assemblies of IC700 Hardwired circuitry.

In operation, IC700 can be energized.Such as, power supply 730 can start to supply electric power to IC700.PS710 may Contribute to making programmable circuit system 715 be energized and the configuration of programmable circuit system 715.When supplying electric power to PS710, PS voltage detector 712 can start the voltage monitoring on electric power signal 750 to 754 at once.In response to determining electric power signal 750 In voltage on 754 one or more or all meet the first predetermined minimum voltage level (also referred to as minimum IOB voltage), PS voltage detector 712 can enable IOB728 via control signal 760.

In general, when PS voltage detector 712 enables IOB728, PS voltage detector 712 have determined that via In electric power signal 750 to 754 one or more or all and the voltage potential received be enough to drive IOB728, such as, Through meeting minimum IOB voltage.For example, it is possible to enable IOB728 by internal power signal is couple to IOB728.Minimum IOB voltage can be high enough that IOB728 operates, but without being high enough such that PS710 opens or starts (boot).Correspondingly, Minimum IOB voltage still can be less than the preferred or legal voltage range that PS710 can be made to operate under operating mode.

Once activating, IOB728 is just able to receive that electric power indication signal 762.Electric power indication signal 762 can be by power supply 730 Or another external source provides.Such as, when power supply 730 is stablized, therefore, when electric power signal 750 to 754 is stable and opens at PS710 Time in the scope needed for opening that begins, electric power indication signal 762 can arrange higher.Correspondingly, although PS710 utilizes PS voltage Detector 712 enables IOB728, but PS710 rely on electric power indication signal 762 indicate power supply 730 when in running and Stable.

Uprising in response to receiving electric power indication signal 762, such as signal, PS710 can start to enable or opening process. With reference to residue accompanying drawing, this opening process will be described in more detail.In one embodiment, as a part for opening process, PS voltage detector 712 can close switch 735 to 745 via control signal 756, so that programmable circuit system 715 It is coupled together with electric power signal 750 to 754.

Along with switch 735 to 745 Guan Bi, PS voltage detector 712 can be to the electric power signal 754 from switch 745 output On voltage be monitored.The second predetermined minimum voltage is met when PS voltage detector 712 determines the voltage on signal 754 Time (referred to as minimum levels transducer voltage), PS voltage detector 712 can enable one or more level translator 720, example Such as level translator 720A.Minimum levels transducer voltage can be or many be enough to make in programmable circuit system 715 The voltage that individual institute screening device (such as, level translator 720A) operates.

In one embodiment, minimum levels transducer voltage can be to be high enough such that programmable circuit and/or one Or multiple level translator 720(is such as, use the circuit that CMOS complementary metal-oxide-semiconductor (CMOS) device is implemented) fortune The voltage turned.Minimum levels transducer voltage can be such voltage, although big being enough to makes device operate, but still is less than Making a certain preferred or legal voltage range needed for the device running in programmable circuit system 715, this voltage range is supported (such as) configuration feature in operating mode and programmable circuit system 715.Minimum IOB voltage is permissible, but without with minimum Level translator voltage is identical or equal.

Additionally, along with switch 735 to 745 enables, structure voltage detector 725 can come into operation.Structure voltage detects Device 725 can start to monitor the voltage in each in electric power signal 750 to 754, to determine in electric power signal 750 to 754 one When person or many persons or whole voltage meet makes programmable circuit system 715 operate the 3rd required predetermined minimum voltage, it It is referred to as minimum programmable circuit system voltage.

One or more or whole voltage is determined in electric power signal 750 to 754 in response to structure voltage detector 725 Meeting minimum programmable circuit system voltage, structure voltage detector 725 can generate signal 758, such as programmable circuit Systematic electricity indication signal, is energized indicating programmable circuit system 715 to PS710.Such as, when electric power signal 750 to In 754 one or more or when all meeting minimum programmable circuit system voltage, structure voltage detector 725 can make letter Numbers 758 uprise.Minimum programmable circuit system voltage (such as, is maintained at running for making programmable circuit system 715 appropriately operate Under pattern) and carry out configuring the legal voltage level of required minimum.Minimum programmable circuit system voltage is usually above minimum IOB voltage and/or minimum levels transducer voltage.Determine in electric power signal 750 to 754 in response to structure voltage detector 725 One or more or all meet minimum programmable circuit system voltage and generate signal 758, indicate programmable circuit system System 715 is ready for configuration, such as, loads configuration data to implement physical circuit therein.

In one embodiment, structure voltage detector 725 can a kind of mode in two kinds of different modes. In response to the control signal 764 received from external source, can be with the AD HOC of choice structure voltage detector 725 running.Root According to the state of control signal 764, structure voltage detector 725 can operate in first mode or the second pattern.

In the first mode, structure voltage detector 725 can be in the one in determining electric power signal 750 to 754 or many Wait predetermined time amount, regeneration signal 758 after person or the most satisfied minimum programmable circuit system voltage, such as, make signal 758 uprise.Such as, this time quantum may be about 50 milliseconds, but can also use other times section.Under the second mode, ring Should in determine in electric power signal 750 to 754 one or more or all meet minimum programmable circuit system voltage, structure electricity Pressure detector 725 can generate signal 758 at once.Signal 758 indicates programmable circuit system 715 in operating, example to PS710 As, it is in operating mode, and can be configured to implement one or more different circuit.

Although described Fig. 7 uses the switch between PS710 and programmable circuit system 715 and public power signal to realize Independent power domain, but can realize, with various different modes, the result that is similar to.It is, for example possible to use two are completely independent Power supply.In the case, it is not to provide control signal to external switch, control signal 764 can be supplied to power supply, from And provide electric power to programmable circuit system 715 so that programmable circuit system 715 is energized and/or power-off.At another example In, switch can be contained in IC700.In the case, control signal 756 can be provided to be positioned at opening of IC700 Close, so that programmable circuit system 715 is energized and/or power-off.

Fig. 8 is the electric power management method 800 illustrating the IC according to another embodiment disclosed in this specification Second flow chart.More precisely, method 800 shows the illustrative methods making IC be energized.Method 800 can be by such as with reference to this IC described in Fig. 1 to Fig. 7 in description performs.

Correspondingly, in step 805, electric power can be applied or is couple to the PS of IC.In step 810, PS voltage inspection Surveying device and may determine that the electric power signal being supplied to PS meets voltage requirements, such as minimum IOB voltage, so that being couple to outside generation Electric power indication signal IOB running.Accordingly, in response to determining that these electric power signals meet minimum IOB voltage, in step In 815, PS voltage detector can make to be couple to the IOB energising of this electric power indication signal.In one embodiment, IOB is made to transport Voltage level needed for work can operate commonly required voltage level less than making PS.

In step 820, PS can detect this electric power indication signal and uprise, thus indicates power supply and reached steady Determine state.Such as, this electric power indication signal can be kept relatively low by the power supply outside IC, until realizing steady statue.One Denier achieves steady statue, and power supply just can make electric power indication signal uprise, thus instruction is sent as an envoy to, the voltage needed for PS running can Derive from power supply.PS voltage detector can detect the state change in the electric power indication signal caused due to the activation of IOB, its Middle electric power indication signal is coupled to described IOB in step 815.

In step 825, in response to the high state of electric power indication signal being detected, PS voltage detector can initialize PS In startup or opening process.In general, step 830 describes, to 850, the opening process that can be performed by PS.In step In 830, PS can use and be internally generated reference clock and come into operation.Such as, be internally generated reference clock can by Fig. 2 time Clock unit 226 generates.In general, internal reference clock is with a certain frequency operation, and this frequency is less than in normal operation (example Such as, operating mode) frequency of the period final clock signal that PS is carried out timing.Such as, in one embodiment, internal clocking Signal can have the frequency of about 30MHz.

In step 835, PS can enable band-gap circuit system or be allowed to be energized.Such as, band-gap circuit system can position In the clock unit of PS, and in general, it provides reference voltage to use for the PLL being similarly positioned in clock unit.Phase Ying Di, in step 840, PS can enable PLL and start to operate at full speed.Such as, it is internally generated reference clock when use During running, the PLL of clock unit is bypassed.When enabling band-gap circuit system and PLL, PLL is no longer bypassed, thus allows PS The outside that PLL according to clock unit can synchronize provides clock signal to operate with full speed.As it has been described above, exported by PLL The frequency of clock signal, once operates, just may be apparently higher than being internally generated reference clock.

In step 845, PS can enable RAM, described RAM and be couple to PS via Memory Controller.In step 850 In, PS can activate any terminal calibration program and/or circuit, thus Tong Bu with RAM.In general, after step 850, PS may be considered that and is in operating mode.Such as, after leaving reset state, PS can perform program code.At another In individual example, PS may also begin to manage the electric power of programmable circuit system.

In step 855, PS can start the electric power managing in the program of the programmable circuit components of system as directed of IC.Such as, In step 855, PS can close switch and be used to supply electrical power the programmable circuit system to IC or otherwise for can Programmed circuit system enables power supply.Such as, PS can instruct switch Guan Bi via control signal, thus allows to be received by switch Any electric power signal be output, and be transmitted to programmable circuit system.

In step 860, PS voltage detector determines that the electric power signal arriving programmable circuit system meets for making coupling Receive the minimum levels transducer voltage of the level translator running of programmable circuit systematic electricity indication signal.In step 865 In, programmable circuit system may determine that electric power signal meets minimum programmable circuit system voltage.In step 870, response In determining that electric power signal meets minimum programmable circuit system voltage, programmable circuit system signals notice PS programmable circuit System is ready for configuration.As it has been described above, programmable circuit system can be by programmable circuit systematic electricity instruction letter Number passing on configuration ready, described programmable circuit systematic electricity indication signal is couple to the system electricity enabled by PS One in flat turn parallel operation.

In step 875, PS can enable for passing on system level signal between PS and programmable circuit system Any level translator.In one embodiment, PS can enable the level not requiring to configure programmable circuit system Transducer.Can also enable between PS and programmable circuit system transmission clock signal propagate one or more Level translator.

When disabled, each level translator can be configured to export steady state value, such as, low or high.Once enable, electricity The output of flat turn parallel operation is by relevant for the input become to be supplied to this level translator.In one embodiment, level conversion is worked as When device receives logic high, this level translator can export logic high, when level translator receives logic low, and this level Transducer can export logic low.In another embodiment, level translator can be configured to export complementary.Such as, When level translator receives the logic high as input, this level translator can export logic low.

Similarly, when level translator receives the logic low as input signal, this level translator can be through joining Put to export logic high.In any case, when disabled, level translator can be configured to export constant logic high or constant Logic low.

In step 880, PS can be configured to carry out one or more circuit to programmable circuit system.At one In embodiment, the PS in running can be for programmable circuit system from the storage position access configuration data being positioned at chip. Such as, PS can be configured data from external memory storage retrieval or be sent joining by communication link (such as, Ethernet connects) Put the request of data.The configuration data received by PS can be supplied to PCAP interface and send it to programmable circuit system Interior Configuration Control Unit.Configuration Control Unit and then configuration data are loaded into configuration memory cell, thus implements by configuration data The physical circuit system specified.

In step 885, PS can enable the electricity that can be used for transmitting subscriber signal between PS and programmable circuit system Flat turn parallel operation.After step 885, whole IC is in running.As it has been described above, PS is in operating mode and is able to carry out journey Sequence code.Additionally, programmable circuit system is in operating mode.In one embodiment, programmable circuit system can be logical Cross after generation user specifies signal to configure and discharge from the state of reset types.User specify signal can be due to With reference to load as described in step 880 configuration data reason and by programmable circuit system in the signal of circuit evolving implemented.

Fig. 9 is the electric power management method 900 illustrating the IC according to another embodiment disclosed in this specification 3rd flow chart.More precisely, method 900 illustrates a kind of technology, it is used for making to enter with reference to described in this specification Fig. 1 to Fig. 8 The programmable circuit system cut-off of the IC of row configuration.Method 900 illustrates how PS can perform IC(is included programmable circuit System) electrical management.Method 900 may begin at certain state, and wherein PS and programmable circuit system are all runnings, example As, it is in operating mode.PS can perform program circuit, and the Circuits System implemented in programmable circuit system can be transported Make.In response to certain signal or event, PS may determine that programmable circuit system will be de-energized, and correspondingly, it is right to start The power-down procedure of programmable circuit system.

Starting from step 905, PS can initialize the intrasystem power-down procedure of programmable circuit, so that programmable circuit The Circuits System state implemented in system stored and, subsequently when programmable circuit system is once again powered up, have at least partly Can recover.Power-down procedure, owing to it relates to programmable circuit system, generally comprises step 905 to 925.

Correspondingly, in step 905, programmable circuit system can be placed in idle condition by PS.Such as, PS can be by can Programmed circuit system is placed in a certain state, the most ongoing or have been applied to programmable circuit system appoint What operation has been allowed to, and prevents any other or new affairs from entering programmable circuit system simultaneously.When to programmable circuit When the operation of system is complete, such as, PS can suspend programmable circuit system, such as, to being supplied to programmable circuit system Each clock signal of system etc. carries out lock control.Correspondingly, programmable circuit system is no longer on operating mode.

In step 910, PS implements in can optionally inquiring about programmable circuit system and determining programmable circuit system The status information of Circuits System (such as, subscriber's line circuit system).In one embodiment, it is stored in programmable circuit system Data configuration retaking of a year or grade function, boundary-scan function etc. can be used to obtain by PS.Such as, programmable circuit system it is stored in Data in interior one or more memorizeies can be obtained by PS or read.Such data can include coefficient table, or by can Other data required for the Circuits System implemented in programmed circuit system.In another example, when soft processor (such as, MicroBlaze^TM) when implementing in programmable circuit system, it is possible to obtain storage value in a register and programmable circuit Content in the program storage of intrasystem soft processor.

In step 915, the status information obtained from programmable circuit system optionally can be stored in memorizer by PS In.In one embodiment, this status information can be stored in the memorizer being positioned at outside die chip by PS.Such as, PS is permissible This status information is stored in external RAM.In another embodiment, this status information can be stored in storage inside by PS In device.

Such as, this status information can be stored in the OCM with reference to Fig. 2 description by PS, and described OCM is positioned at PS.

In step 920, PS, such as, and core complex, level translator can be placed in known state, described level Programmable circuit system is coupled together by transducer with PS.Such as, level translator can be placed in certain state to maintain Logical zero or logic one.In some cases, some level translators can be configured to maintain logical zero, and other level turn Parallel operation is configured to maintain logic one.Level translator is placed in known state can prevent spurious signal in PS internal trigger event. Such as, spurious signal may cause to be coupled to PS system or the assembly of level translator while programmable circuit system cut-off (such as, be coupled to FMIO interface I/O device, be coupled together by another interface and programmable circuit system another PS clock block) falsely generate event, such as interrupt.When interrupting obtaining service and the programmable circuit of programmable circuit system During system power-off, this interruption will not be serviced, thus there will be yet unresolved issue or other problems in causing PS.

In step 925, PS can make programmable circuit system cut-off.Such as, PS can instruct via control signal Switch to release coupling of programmable circuit system and electric power signal.Once programmable circuit system cut-off, PS just can continue Operate and under normal operating conditions, perform program code.Or, after making programmable circuit system cut-off, PS can appoint Selection of land is placed in low-power mode.When being in low-power mode, PS does not perform program code and the electric power that consumes is remote Less than the situation in operating mode, in operating mode, system clock (such as) is with running at full speed.

Correspondingly, step 930 to 950 can essentially be optional, and show (such as, PS is placed in low-power Sleep) step in pattern.In one embodiment, such as, PS can be configured to respond to make programmable circuit system break Electricity and initialize low-power mode.In another embodiment, in response to the signal being externally received from IC or interruption, can refer to Lead PS and enter low-power mode.

In step 930, PS can walk around the PLL of running in clock unit.When PLL is bypassed, PS can use It is internally generated reference clock and comes into operation.In step 935, PS can make band-gap circuit system cut-off.In step 940, RAM can be placed in self-refresh (self-refresh) pattern by PS.In step 945, PS can disable the terminal calibration merit of RAM Energy.In step s 950, reference clock can be carried out frequency partition to reduce the power consumption in PS further.Such as, frequency is about 30MHz is internally generated clock and can be down to about 1MHz by frequency partition.

It will be appreciated that PS can be taken out of from low-power mode to 930 generally through performing step 950 with reverse order Come.

Figure 10 is to illustrate according to the 7th square frame of IC200 in Fig. 2 of another embodiment disclosed in this specification Figure.The abstract graph of the be depicted as IC200 of Figure 10, it illustrates the I/O device when programmable circuit system 204 power-off to PS202 The management of 305.For the sake of illustrative simplicity convenience, in IC200, there is one or more assembly not shown.Such as, not shown in Figure 10 Switch 315 and 320 and programmable circuit system 204 in other assemblies various.

In embodiment shown in Figure 10, I/O device 305 is couple to external treatment by one or more I/O pins 325 and saves Point (not shown).As it can be seen, serve I/O device 305 and the principal entities that interacts is in programmable circuit system 204 The subscriber's line circuit system 280 of interior enforcement.In the example shown, I/O device 305 is by core switch 236 and interface 256 warp Communicated with subscriber's line circuit system 280 by the signal path being labeled as 1005.

In one embodiment, in response to determining that programmable circuit system 204 will be de-energized, core complex 206 is permissible It is configured to obtain the control to I/O device 305.When programmable circuit system 204 power-off in configuration shown in Figure 10, as Described in this specification, in the case of not changing control, process node no longer can be used by I/O device 305.

Such as, core complex 206 can signal the particular lock for following the tracks of the control to I/O device 305 Determine mechanism's herein below: core complex 206 just removes control at subscriber's line circuit system 280.In one embodiment, core Heart complex 206 can include or perform program code, and described program code provides can be implemented by subscriber's line circuit system 280 Some or all of specific functions.Therefore, when subscriber's line circuit system 280 is energized, core complex 206 can take over previously by with The function that family Circuits System 280 performs, the function the most relevant with I/O device 305.In an example, core complex 206 can maintain the communication link between I/O device 305 and external treatment node.

Figure 11 is to illustrate according to the eighth frame of IC200 in Fig. 2 of another embodiment disclosed in this specification Figure.Figure 11 illustrates IC200 state after programmable circuit system 204 power-off.The most disconnected for explanation programmable circuit system 204 Electric and unavailable, with shade, programmable circuit system 204 is shown.As it can be seen, core complex 206 has obtained to I/O device The control of 305, and have started to serve I/O device 305.Now by being labeled as the signal path of 1100 at core complex Communicate between 206 and I/O devices 305.Therefore, not it is to continue with from I/O device 305, communication is routed to programmable circuit System 204, but communication is supplied to core complex 206, in order to service.

In the example shown, it is considered to situations below, wherein I/O device 305 implements USB interface arrival external treatment node.Such as, The subscriber's line circuit system 280 implemented in programmable circuit system 204, it is possible to implement video processing circuits system is in order to process The video of delivery on USB communication link.In the case of I/O device 305 control is immovable, when programmable circuit system 204 During power-off, it is provided that stop to the video council of external treatment node.It is combined by the control of I/O device 305 is supplied to core Thing 206, core complex 206 can maintain USB communication link.

In one embodiment, core complex 206 can provide out original by user by the execution of program code The identical function that Circuits System 280 provides.Owing to this function (such as, for Video processing in the case of this) is being held by program code Can be performed by core complex 206 after row, therefore, compared with subscriber's line circuit system 280, its performance may tail off.At another In individual embodiment, core complex 206 can provide various or different function.Such as, not it is to continue with processing video, core Heart complex 206 can export video signal, and described video signal is pointed out to show the image that Video processing is temporarily unavailable.Permissible Tailing off or limited function of other forms is provided.But, in either case, can maintain between external treatment node Communication link, such as, retains electrical communication channel.

Figure 12 is to illustrate a kind of IC electric power management method according to another embodiment disclosed in this specification 4th flow chart of 1200.Method 1200 show and carries out electrical management in the IC in the control having I/O device A kind of technology, described I/O device can be couple to the intrasystem Circuits System of programmable circuit.Such as, shown in method 1200 For for reference to illustrated in this specification Figure 10 and Figure 11 and described IC carries out a kind of technology of electrical management.

Method 1200 may begin at certain state, and wherein IC has been energized and has been in work for the national games.Such as, at least one I/O device can be by being otherwise communicatively linked to external treatment node for one or more I/O pins of PS specially.I/O The Circuits System that device can also be implemented in being couple to programmable circuit system by core switch and interface.Such as, user Circuits System can be configured to serve I/O device.

In step 1205, core complex may determine that programmable circuit system will be de-energized.As explained above, PS can To be configured to control the electric power function of programmable circuit system.In an example, core complex itself can (such as, By to the execution of program code the application to certain programmed formula execution logic) determine that programmable circuit system will be de-energized. In another example, IC, such as, and core complex, request can be received from another external treatment node and make electricity able to programme The notice of road system cut-off or signal.

In step 1210, whether core complex comprises any I/O device by PS(such as in may determine that PS, and one Individual or multiple interfaces) it is couple to programmable circuit system.Such as, core complex can be via the control depositor being positioned at PS Check the configuration of I/O device, interface, core complex etc., with determine which I/O device (if any) obtains can The service of programmed circuit intrasystem subscriber's line circuit system.When one or more I/O devices are couple to programmable circuit by PS System, method can continue to step 1215.Being couple to programmable circuit system when there is not I/O device by PS, method can To proceed to step 1225.

In step 1215, PS can obtain the control to I/O device.Such as, core complex can be configured to Reconfiguring the link in PS, as with reference to shown in Figure 10 and Figure 11, therefore, the information received from I/O device can be directed to Core complex rather than programmable circuit system.Make use of in the event of locking mechanism in PS, core complex can refer to Leading locking mechanism, core complex has exclusive control to I/O device.For purposes of illustration, method 1200 suppose there is one Individual I/O device is couple to programmable circuit system by PS.It will be appreciated, however, that more than one I/O device can be had to be couple to Programmable circuit system, and can apply in this kind of situation with reference to the step described in Figure 12.

In step 1220, PS can start to maintain the communication link between external treatment node and I/O device.PS is permissible Serve external treatment node and I/O device, and can perform further once by the intrasystem subscriber's line circuit of programmable circuit The function that system is provided.As it has been described above, PS can provide the fully functioning of subscriber's line circuit system or can provide by user Functional finite subset that Circuits System provides.

In step 1225, programmable circuit system can be placed in idle condition by PS.In step 1230, PS can appoint Selection of land inquiry programmable circuit system is with the Circuits System (such as, subscriber's line circuit system) implemented in determining programmable circuit system Status information.As it has been described above, be stored in the intrasystem data of programmable circuit can be used configuration retaking of a year or grade function, border by PS Scan functions etc. obtain.In step 1235, the status information obtained from programmable circuit system can optionally be deposited by PS Storage is in memorizer.

In step 1240, PS, such as, and core complex, level translator can be placed in known state, described level Programmable circuit system is coupled together by transducer with PS.In step 1245, PS can make programmable circuit power-off.In step In rapid 1250, PS can continue running, such as, performs program code, and can maintain I/O device and the outside being coupled to it Process the communication link between node.PS can continue to serve I/O device.

Figure 13 is to illustrate a kind of IC electric power management method according to another embodiment disclosed in this specification 5th flow chart of 1300.Method 1300 show and carries out electrical management in the IC in the control having I/O device A kind of technology, described I/O device can be couple to the intrasystem Circuits System of programmable circuit.More precisely, method In example shown in 1300, programmable circuit system is energized, and is provided the control of I/O device from core complex Back to programmable circuit system.The system that method 1300 can be shown by the Figure 10 to Figure 12 with reference to this specification performs.

Method 1300 may begin at certain state, and wherein PS is running, and the power-off of programmable circuit system.More Exactly, method 1300 may begin at certain state, and wherein the core complex of PS has obtained the control to I/O device Power, described I/O device was come by the subscriber's line circuit system implemented in programmable circuit system before programmable circuit system cut-off Control, as described in reference to Figure 12.

Therefore, in step 1305, PS can close switch be used to supply electrical power the programmable circuit system to IC or Otherwise enable the power supply of programmable circuit system.In step 1310, PS voltage detector may determine that arrival can be compiled The electric power signal of journey Circuits System meets what the level translator making to be couple to programmable circuit systematic electricity indication signal operated Minimum levels transducer voltage.In step 1315, it is minimum able to programme that programmable circuit system may determine that electric power signal meets Circuits System voltage.

In step 1320, in response to determining that electric power signal meets minimum programmable circuit system voltage, programmable circuit System signals notice PS programmable circuit system is ready for configuration.In step 1325, PS can enable for Any level translator of system level signal is passed between PS and programmable circuit system.In one embodiment, PS is permissible Enable the level translator not requiring that programmable circuit system is configured.Can also enable in PS and programmable circuit system Between system, the clock signal of transmission carries out the one or more level translators propagated.

In step 1330, PS can be configured to carry out one or more circuit to programmable circuit.A reality Executing in example, the PS in running can be for programmable circuit system from the storage position access configuration data being positioned at chip.Example As, PS can be configured data from external memory storage retrieval or be sent configuration by communication link (such as, Ethernet connects) The request of data.The configuration data received by PS can be supplied to PCAP interface and send it in programmable circuit system Configuration Control Unit.Configuration Control Unit and then configuration data are loaded into configuration memory cell, thus implements to be referred to by configuration data Fixed physical circuit system.

In an example, identical circuit design, such as, and identical subscriber's line circuit design, can be re-loaded to In the programmable circuit system always also existed before described programmable circuit system cut-off.In another example, permissible Via loading the revision configuring the subscriber's line circuit system implemented in programmable circuit system before data implement power-off, example As, upgrade version.In another example, a diverse circuit design conduct can be implemented in programmable circuit system Subscriber's line circuit system, described subscriber's line circuit system differs markedly from before programmable circuit system cut-off in programmable circuit system The subscriber's line circuit system of interior enforcement.

In step 1335, PS can enable the level that can be used for transmitting subscriber signal between PS and programmable circuit and turn Parallel operation.In step 1340, the subscriber's line circuit that any storage status data can optionally be implemented in programmable circuit system Recover in system, such as, reload.After step 1340, whole IC is in running.As it has been described above, PS is in operating mode And it is able to carry out program code.Additionally, programmable circuit system is in operating mode.In one embodiment, electricity able to programme Road system can discharge after specifying signal to configure by generation user from the state of reset types.User specifies Signal be likely due to reference to load as described in step 1330 configuration data reason and by programmable circuit system in implement The signal that Circuits System generates.

In step 1345, discharge from reset state in response to programmable circuit system, PS, such as core complex, can With the subscriber's line circuit system implemented in the control of I/O device being passed to programmable circuit system.As described in reference to Figure 12, Core complex can assume that the control to I/O device is from the subscriber's line circuit system of enforcement in programmable circuit system.? Utilizing in the event of locking mechanism in PS, core complex can instruct locking mechanism, core complex by it to I/O device Control (such as, exclusive control) passes to subscriber's line circuit system.Core complex can be configured to reconfigure in PS Communication link so that I/O device can be coupled in one with subscriber's line circuit system again by core complex and interface Rise.Such as, data path can be from becoming such shown in Figure 10 as shown in Figure 11, so that information can be multiple via core Compound and interface and flow between I/O device and subscriber's line circuit system.

In step 1350, it is transferred to subscriber's line circuit system, subscriber's line circuit system from core complex in response to control System can start to serve I/O device.In this regard, I/O device and the process node being positioned at outside IC and being couple to I/O device Between communication link will not occur interrupt or otherwise lose.Only subscriber's line circuit system is compared at core complex In the case of less function is provided, global function can be combined and these functions can be via I/O device for processing used by node.

With reference to as described in Figure 12, for purposes of illustration, method 1300 suppose there is that an I/O device is couple to by PS can Programmed circuit system.It will be appreciated, however, that more than one I/O device can be had to be couple to programmable circuit system, and reference Step described in Figure 13 can apply in this kind of situation.

Flow chart illustration in accompanying drawing according to the system of one or more embodiments disclosed in this specification, method with And the structure of the viable solution of computer program, function and operation.In this regard, each square frame in flow chart can With representation module, fragment or a part for code, described code includes that the executable program code of logic function is specified in enforcement One or more parts.

It should be noted that in some alternate embodiment, the function mentioned in each square frame can be with inconsistent with figure Order occur.Such as, two square frames illustrated continuously can essentially substantially concurrently perform, or each square frame sometimes can be by Anti-order of taking a picture performs, and this depends on mentioned function.Should also be clear that each square frame in flow chart illustration, and The combination of the square frame in flow chart illustration can be implemented by hardware based dedicated system, and described dedicated system performs appointment Function or behavior, or specialized hardware and the combination of executable instruction.

One or more embodiments can be realized with the combination of hardware or hardware and software.One or more enforcements Example can realize the most in a centralised manner, or is dispersed in the distribution mode in some interconnection systems with different elements Realize.Any kind of data handling system or be adapted for carrying out method described herein other equipment at least one of and all may be used It is suitable for.

One or more embodiments can be embedded in the device of such as computer program etc further, this dress Put all features including implementing methods described herein.Described device can include data storage medium, such as, non-momentary meter Calculation machine can with or computer-readable media, be used for storing program code, described program code (includes memorizer being loaded into system And processor) in and when performing, system can be caused to perform at least some of of function described in this specification.Data storage medium Example can include, but not limited to optical media, magnetic medium, computer as random access memory or hard disk etc Memorizer, etc..

Term " computer program " herein, " software ", " application program ", " computer usable program code ", " program Code ", " executable code ", and variant and/or combination, refer to any representation of one group of instruction, either language, generation Code or symbol, described instruction is intended to make to have the system of information processing capability and performs specific function, the most directly performs, or Perform after one or both in following behavior: a) be converted to another kind of language, code or symbol；B) different materials is used Material form replicates.Such as, program code can include, but not limited to subroutine, function, program, goal approach, target Embodiment, executable application programs, applet, servlet, source code, object code, shared library/dynamic load Storehouse and/or be designed for other job sequences performed on the computer systems.

Term used herein " one " is defined as one or more.Term used herein " multiple " be defined as Two or more.Term " another " used herein is defined as at least two or more.Art used herein Language " comprises " and/or " having " is defined as comprising, i.e. open language.Term used herein " couples " and is defined as connecting, Either do not use being directly connected to or using being indirectly connected with of one or more intervening element of any intervening element, unless separately There is instruction.Two elements can also mechanically, electrically or communication linkage mode is by communication channel, path, network Or system couples.

One or more realities on the premise of without departing from the spirit or essential attributes of embodiment, disclosed in this specification Execute example to be implemented by other forms.Therefore, should with reference to above claim rather than with reference to above-mentioned instruction one or The description of the scope of multiple embodiments.

Claims (13)

1. an integrated circuit, comprising:

Including the processor system of the core complex with core, described core is configured to perform program code, Qi Zhongsuo State processor system to be hard-wired and include the processor hardware resource being positioned in described processor system；And

Being configurable to implement the programmable circuit system of different physical circuit, described programmable circuit system is couple to described place Reason device system；

Wherein said programmable circuit system is configured to share making of described processor hardware resource with described core complex By power；

Wherein said processor hardware resource is input/output (I/O) device in order to provide interface, and is configured to generate Interrupt signal gives described programmable circuit system and described core complex；

Wherein, in response to described interrupt signal:

When described core complex has the control to described processor hardware resource, described core complex serves institute State interrupt signal；And

When described programmable circuit system has the control to described processor hardware resource, described programmable circuit system Serve described interrupt signal；And

Wherein said core includes 1 grade of buffer memory, and described programmable circuit system directly institute to described core State 1 grade of buffer memory and read and write access.

Integrated circuit the most according to claim 1, is couple to described collection to wherein said processor hardware resource selection Become in circuit and be exclusively used in the input/output pin of described processor system or be couple to described programmable circuit system.

Integrated circuit the most according to claim 2, the data wherein generated from described processor hardware resource are provided to Described integrated circuit is exclusively used in the described input/output pin of described processor system, and described data genaration is in coupling To the data wire of structure input/output multiplexer, described structure input/output multiplexer is coupled to described programmable circuit system System.

Integrated circuit the most according to claim 1, wherein said integrated circuit includes:

Hardware lock mechanism, described hardware lock mechanism is configured to only allow described core complex or described able to programme every time One in Circuits System controls described processor hardware resource.

Integrated circuit the most according to claim 4, wherein said hardware lock mechanism is in described 1 grade of buffer memory Or the storage position in level 2 cache memory device memorizer.

Integrated circuit the most according to any one of claim 1 to 3, wherein said processor system includes being connected to described The level 2 cache memory device memorizer of core complex, and

Wherein said programmable circuit system directly reads and writes access to described level 2 cache memory device memorizer.

Integrated circuit the most according to any one of claim 1 to 3, wherein said programmable circuit system includes user's electricity Road, described subscriber's line circuit has the communication chain processing node through described processor hardware resource with described integrated circuit external Connect；

Wherein said core complex is configured to control described processor hardware resource, with in response to described programmable circuit system Unite the decision of power-off；And

During wherein said programmable circuit system cut-off, described core complex maintains through described processor hardware resource and institute State the described communication linkage processing node.

Integrated circuit the most according to any one of claim 1 to 3, wherein said programmable circuit system includes user's electricity Road, described subscriber's line circuit is coupled to described processor system via interface, and wherein said processor system is configured to implement mark Quasi-input/output function, wherein said processor system is configured to respond to connect via described interface from described subscriber's line circuit The request received, is supplied to described subscriber's line circuit by described standard input/output function.

Integrated circuit the most according to any one of claim 1 to 3, wherein said processor hardware resource is for described The use of core complex, and carry out different configurations to the use of described programmable circuit system；And

Wherein in response to controlling the described core complex of described processor hardware resource or described programmable circuit system, described Processor hardware resource can reconfigure.

Integrated circuit the most according to any one of claim 1 to 3, wherein said programmable circuit system is configured to The power-off independent of described processor system；And

Wherein said processor system controls power supply and the power-off of described programmable circuit system.

The method of the processor hardware resource of 11. 1 kinds of shared integrated circuits, comprising:

Configure the programmable circuit system of described integrated circuit to implement subscriber's line circuit；And

Configure the described programmable circuit system right to use with the described processor hardware resource of shared processor system, Qi Zhongsuo Stating processor system to be hard-wired and include the core complex with core, described core is configured to execution program generation Code；

Wherein said processor hardware Resource orientation is in described processor system；And

Wherein said processor hardware resource is for providing the input/output device of interface；

From described processor hardware resource generate interrupt signal and described interrupt signal be provided to described core complex and Described programmable circuit system；

Serve described interrupt signal, wherein:

When described core complex controls described processor hardware resource, interrupted letter by the service of described core complex is described Number；

When described programmable circuit system controls described processor hardware resource, by the intrasystem institute of described programmable circuit State subscriber's line circuit and service described interrupt signal；And

Described subscriber's line circuit directly 1 grade of buffer memory or described processor system to the described core of described core complex The level 2 cache memory device of system conducts interviews.

12. methods according to claim 11, it farther includes:

Receive the request that the described processor hardware resource to described processor system conducts interviews；

Determine whether asked processor hardware resource can be used；

If the processor hardware resource asked is available, then:

Authorize and access the processor hardware resource asked；

The processor hardware resource that configuration is asked；And

Initialize the operation in the processor hardware resource asked.

13. methods according to claim 11, wherein said subscriber's line circuit uses described processor hardware resource to have With the communication linkage of the process node of described integrated circuit external, described method farther includes:

Described core complex controls described processor hardware resource, with in response to the power-off journey in described programmable circuit system Sequence；And

During described programmable circuit system cut-off, described core complex maintains and described place through described processor hardware resource The described communication linkage of reason node.