CN103400764A - Forming method for bipolar transistor - Google Patents
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- CN103400764A CN103400764A CN2013103152374A CN201310315237A CN103400764A CN 103400764 A CN103400764 A CN 103400764A CN 2013103152374 A CN2013103152374 A CN 2013103152374A CN 201310315237 A CN201310315237 A CN 201310315237A CN 103400764 A CN103400764 A CN 103400764A
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Abstract
The invention discloses a forming method for a bipolar transistor. The method comprises the following steps of providing a semiconductor substrate; forming an N-type collector electrode in the semiconductor substrate; forming a P-type base electrode on the surface of the N-type collector electrode, wherein an oxidation layer formed by natural oxidation is arranged on the surface of the P-type base electrode; forming an N-type emitting electrode on the P-type base electrode; carrying out annealing treatment on the P-type base electrode and the N-type emitting electrode to reduce the resistance of the emitting electrode. According to the forming method for the bipolar transistor, the resistance of the emitting electrode can be reduced and the performances of the bipolar transistor are improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of bipolar transistor.
Background technology
Bipolar transistor is one of device architecture commonly used that forms in modern large scale integrated circuit, its service speed is fast, under saturation voltage drop, current density is large and production cost is low.
Please refer to Fig. 1 to Fig. 4 is the formation method schematic diagram of the bipolar transistor of prior art.
Please refer to Fig. 1, Semiconductor substrate 10 is provided, at the interior formation n type buried layer 11 of described Semiconductor substrate 10 and the collector electrode 12 that is positioned at described n type buried layer 11.
The material of described Semiconductor substrate 10 can be the semi-conducting materials such as silicon or germanium silicon.To in described Semiconductor substrate 10, carrying out the first N-type Implantation diffusion, form described n type buried layer 11, described the first N-type ion can be antimony ion; On described Semiconductor substrate 10, form and have the first mask layer (not shown) of opening, position and the figure of described opening definitions set electrode, take described the first mask layer as mask in described n type buried layer 11, carrying out the second N-type Implantation, form collector electrode 12, described the second N-type ion is phosphonium ion; Then remove described the first mask layer.
Please refer to Fig. 2, on described Semiconductor substrate 10 surfaces, form the P type epitaxial loayer 13 that covers described n type buried layer 11 and collector electrode 12.
The material of described P type epitaxial loayer 13 is germanium silicon, and described P type epitaxial loayer 13 is as base stage.
Please refer to Fig. 3, on described P type epitaxial loayer 13 surfaces, form and have the oxide layer 14 of opening, described opening has defined the emitter of follow-up formation and contact position and the figure of base stage, expose the surface of part P type epitaxial loayer 13, on described P type epitaxial loayer 13 surfaces, form and fill full described opening, and cover the N-type polysilicon layer 15 on described oxide layer 14 surfaces, and carry out planarization.
Please refer to Fig. 4, on described polysilicon layer 15 surfaces, form the second mask layer, described the second mask layer defines the figure of emitter, and described N-type polysilicon layer 15 and oxide layer 14 take described the second mask layer as mask etching form emitter 15a.
The performance of the bipolar transistor that prior art forms remains further to be improved.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of bipolar transistor, improves the performance of bipolar transistor.
For addressing the above problem, the invention provides a kind of formation method of bipolar transistor, comprising: Semiconductor substrate is provided; In described Semiconductor substrate, form the N-type collector electrode; On described N-type collector electrode surface, form P type base stage, described P type base surface has the oxide layer that autoxidation forms; On described P type base stage, form the N-type emitter; Described P type base stage and N-type emitter are carried out to annealing in process, reduce emitter resistance.
Optionally, described annealing in process employing is rapid thermal anneal process.
Optionally, the temperature range of described annealing in process is 500 ℃～1200 ℃, and the time of described annealing in process is 10s～30s.
Optionally, described P type base surface has oxide layer, and the thickness of described oxide layer is
Optionally, before forming described N-type polysilicon layer, described P type base surface is cleaned, then at described P type base surface autoxidation, form oxide layer.
Optionally, after annealing in process, some cavities in described oxide layer, occur, and the gross area in described cavity is 1%～20% of annealing in process oxide layer area before.
Optionally, the material of described P type base stage is the SiGe of P type doping.
Optionally, the method in described N-type collector electrode surface formation P type base stage comprises: at described semiconductor substrate surface, form the first insulating barrier; Described the first insulating barrier of etching, form the first opening on described N-type collector electrode surface, and described the first opening exposes the surface of described N-type collector electrode; Form the P type base stage of filling full described the first opening.
Optionally, the method that forms the N-type emitter in described P type base surface comprises: at described the first insulating barrier and P type base surface, form the base polysilicon layer, and the second insulating barrier that is positioned at described base polysilicon layer surface; Described the second insulating barrier of etching and base polysilicon layer, form the second opening that is positioned at described P type base surface, and described the second opening exposes the surface of part P type base stage; In described the second opening, form the N-type polysilicon layer, described N-type polysilicon layer covers inwall and second surface of insulating layer of the second opening; On described N-type polysilicon layer surface, form the pattern mask layer, take described pattern mask layer as mask, the described N-type polysilicon layer of etching and the second insulating barrier, expose the part surface away from the base polysilicon layer of described the second opening portion, remaining part N-type polysilicon layer is as the N-type emitter.
Optionally, the material of described the second insulating barrier is one or more in tetraethoxysilane, silicon oxynitride, silicon nitride, and described the second insulating barrier is individual layer or multiple-level stack structure.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, in the P type base stage that forms described bipolar transistor and after being positioned at the N-type emitter of described P type base surface, carry out annealing in process.Because P type base surface can be had layer of oxide layer by autoxidation, in annealing process, the N-type foreign ion in the N-type emitter can spread to oxide layer from the N-type emitter, clashes into described oxide layer, oxide layer is ruptured and produce small cavity.Electronics in the N-type emitter can directly enter in P type base stage by described cavity, so the existence in described cavity can reduce the emitter resistance that produces due to the oxidation of P type base surface.
further, the material of described N-type emitter is polysilicon, in annealing process, N-type foreign ion in the N-type emitter can clash into described oxide layer along the polysilicon grain boundary of emitter, crystal boundary and oxide layer contact position place at described emitter form cavity, so, the scope in the cavity that forms is less, the gross area in described cavity is 1%～20% of annealing in process oxide layer area before, this moment, the size in cavity was also very little, hole current mainly results from tunnelling mechanism, hole enters in the N-type emitter by the oxide layer tunnelling, so the curent change of base stage is little.Finally due to emitter resistance, reduce, and that base current changes is little, at emitter and base stage, applies same external bias voltage V
BE, can obtain larger collector current, thereby improve the performance of bipolar transistor.
The accompanying drawing explanation
Fig. 1 to Fig. 4 is the schematic diagram of the bipolar transistor forming process of prior art of the present invention;
Fig. 5 to Figure 15 is the schematic diagram of the bipolar transistor forming process of embodiments of the invention;
Figure 16 is that in the bipolar transistor of embodiments of the invention formation, electronics and hole are by the partial schematic diagram of oxide layer;
Figure 17 is the graph of a relation that the emitter resistance rate, base stage saturation current of the bipolar transistor that forms of embodiments of the invention changes with the coverage rate of oxide layer.
Embodiment
As described in the background art, the performance of existing bipolar transistor need further raising.
Research discovery, existing bipolar transistor are after forming described base stage, and before described base surface formed emitter, described base surface can be formed layer of oxide layer by autoxidation.Described oxide layer, between the emitter and base stage interface of bipolar transistor, can improve the emitter resistance of bipolar transistor, thereby can reduce the emitter current of bipolar transistor, affects the performance of bipolar transistor.
And, prior art can't be removed described oxide layer at present, even if after forming described base stage, described base surface is cleaned to the oxide layer of removing surface, but after form the process of described emitter, due to the change of technique, in the process of changing reaction chamber, entering the described base surface of non-vacuum environment still can oxidized formation layer of oxide layer.
Technical scheme of the present invention, by to having formed described emitter structure afterwards, carrying out annealing in process, make to produce hole in described oxide layer between emitter and base stage, thereby reduce emitter resistance, improves the performance of described bipolar transistor.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Please refer to Fig. 5, Semiconductor substrate 100 is provided, in described Semiconductor substrate, also have fleet plough groove isolation structure 101.
The material of described Semiconductor substrate 100 is the semi-conducting materials such as silicon, germanium, SiGe, GaAs.
The formation method of described fleet plough groove isolation structure 101 comprises: at the interior formation groove of described Semiconductor substrate 100, at described grooved inner surface, adopt thermal oxidation method to form pad oxide, then in described groove, fill silica, form fleet plough groove isolation structure 101.
Please refer to Fig. 6, at described semiconductor substrate surface, form the first mask layer 102, take described the first mask layer 102 as mask, described Semiconductor substrate 100 is carried out to the N-type Implantation, at the interior formation N-type of described Semiconductor substrate 100 collector electrode 110.
Concrete, in described the first mask layer 102, having opening, described opening defines position and the shape of N-type collector electrode 110.In the present embodiment, the material of described the first mask layer 102 is photoresist layer; In other embodiments of the invention, described the first mask layer 102 can be the stacked structure of silicon oxide layer and photoresist layer.
Take described the first mask layer 102 as mask, the ion that described Semiconductor substrate 100 is carried out to the N-type Implantation is phosphonium ion, at the interior formation collector electrode 110 of described Semiconductor substrate 100.
In other embodiments of the invention, can also first to described Semiconductor substrate 100, carry out N-type Implantation diffusion, in described Semiconductor substrate, form n type buried layer; And then form the first mask layer on described n type buried layer surface, take described the first mask layer as mask, in described n type buried layer, carry out the N-type Implantation, in n type buried layer in described Semiconductor substrate, form the N-type collector electrode, injection ion in described n type buried layer can be antimony ion, and the doping content of described n type buried layer is less than the doping content of N-type collector electrode.Form described n type buried layer, can improve the bipolar transistor of follow-up formation and the vertical isolation effect between Semiconductor substrate.
Please refer to Fig. 7, remove described the first mask layer 102(and please refer to Fig. 6), on described Semiconductor substrate 100 surfaces, form the first insulating barrier 103 that covers described Semiconductor substrate 100 surfaces, described the first insulating barrier 103 has the first opening 112, and described the first opening 112 exposes the surface of N-type collector electrode 110.
In the present embodiment, the material of described the first insulating barrier 103 is tetraethoxysilane, and in other embodiments of the invention, the material of described the first insulating barrier 103 can also be other insulating material such as silica, silicon nitride.The thickness of described the first insulating barrier 103 is 0.5nm～2nm, with the consistency of thickness of the P type base stage of follow-up formation.
Concrete, the method that forms described the first insulating barrier 103 in the present embodiment comprises: adopt spin coating proceeding to form the first insulation material layer at described semiconductor substrate surface, on described the first insulation material layer surface, form graphical photoresist layer, described the first insulation material layer take described graphical photoresist layer as mask etching, formation has the first insulating barrier 103 of the first opening 112, described the first opening 112 is positioned at N-type collector electrode 110 surfaces, position and the shape of the P type base stage of the follow-up formation of definition.
Please refer to Fig. 8, at described the first opening 112(, please refer to Fig. 7) in form P type base stage 120.
The material of described P type base stage 120 is germanium silicon, and in described P type base stage 120, doped with P type ion, the thickness of described P type base stage 120 is 0.5nm～2nm.
In the present embodiment, adopt epitaxy technique in the interior formation of described the first opening 112 P type base stage 120, described P type ion is the boron ion.In the present embodiment, adopt in-situ doped technique at the interior doped with boron ion of described P type base stage 120, in other embodiments of the invention, also can adopt ion implantation technology, at the interior doped with boron ion of described P type base stage 120.
Please refer to Fig. 9, at described the first insulating barrier 103 and P type base stage 120 surfaces, form base polysilicon layer 104, and the second insulating barrier 105 that is positioned at described base polysilicon layer 104 surface; Described the second insulating barrier 105 of etching and base polysilicon layer 104, form the second opening 106 that is positioned at described P type base stage 120 surfaces, and described the second opening 106 exposes the surface of part P type base stage 120.
Described base polysilicon layer 104 adopts epitaxy techniques to form, and the follow-up link as base stage of described base polysilicon layer 104 can reduce the contact resistance of base stage.The thickness of described base polysilicon layer 104 is 0.5nm～2nm.
The material of described the second insulating barrier 105 is one or more materials in tetraethoxysilane, silicon oxynitride, silicon nitride.Described the second insulating barrier 105 can be that single layer structure can be also the multiple-level stack structure.In the present embodiment, described the second insulating barrier 105 is the multiple-level stack structure, comprising: be positioned at described base polysilicon layer 104 surface silicon nitride layer, be positioned at described silicon nitride layer surface teos layer, be positioned at the silicon oxynitride layer on described teos layer surface.Described the second insulating barrier 105 is follow-up as the isolation structure between emitter and Semiconductor substrate.
At described the first insulating barrier 103 and the P type base stage described base polysilicon layer 104 of 120 surface formation with after being positioned at second insulating barrier 105 on described base polysilicon layer 104 surface, on described the second insulating barrier 105 surfaces, form the pattern mask layer, the graphical definition of described pattern mask layer goes out position and the shape of the N-type emitter of follow-up formation.Take described pattern mask layer as mask, described the second insulating barrier 105 of etching and base polysilicon layer 104, form the second opening 106 on described P type base stage 120 surfaces.The width of described the second opening 106, less than the width of P type base stage 120, exposes the surface of part P type base stage 120.
Please refer to Figure 10, after forming described the second opening 106, the surface of the P type base stage 120 of described the second opening 106 bottoms is cleaned, described cleaning solution is rare HF solution.
P type base stage 120 surfaces of described the second opening 106 bottoms, in entering the reaction chamber process of different process, touch non-vacuum environment, are easy to oxidized formation oxide layer.In the present embodiment, the surface of described P type base stage 120 is cleaned, can be removed the residue in described the second opening, the surface of clean described P type base stage 120, improve follow-up quality at the described P type base stage 120 surperficial emitters that form.But due to cleaning P type base stage 120 surface meeting residual moistures afterwards, and surface meeting formation matte, have dangling bonds, in the described P type base stage 120 surface easier oxidations of meeting, form the oxide layer 121 of layer.The thickness of described oxide layer 121 is generally
In other embodiments of the invention, also can not carry out described cleaning process, still can in described P type base surface, form oxide layer 121 due to autoxidation.
The thickness of described oxide layer 121 is lower, it is follow-up after described oxide layer 121 surfaces form the N-type emitter, due to the emission resistance that has the described emitter of oxide layer 121 meeting raising between described P type base stage and N-type emitter, although can satisfying break-through, electronics crosses described oxide layer 121 arrival P type base stages, but the electron amount that arrives base stage from emitter can descend, thereby reduces the performance of described NPN transistor.
Please refer to Figure 11, at the interior formation N-type of described the second opening 106 polysilicon layer 107, described N-type polysilicon layer 107 covers the inwall of the second opening 106 and the surface of the second insulating barrier 105.
Described N-type polysilicon layer adopts epitaxy technique to form, and is positioned at the N-type emitter of the described N-type polysilicon layer 107 on described oxide layer 121 surfaces as bipolar transistor.In the present embodiment, the doping ion of described N-type polysilicon layer 107 is arsenic, and in other embodiments of the invention, the doping ion of described N-type polysilicon layer 107 can also be other N-type ions such as phosphorus.In other embodiments of the invention, also can in described the second opening, form other materials, as emitter, such as monocrystalline silicon etc.
Please refer to Figure 12, after forming described N-type polysilicon layer 107, above-mentioned semiconductor structure is carried out to annealing in process, cavity 122 appears in the oxide layer 121 that annealing in process makes; After carrying out above-mentioned annealing in process, on described N-type polysilicon layer 107 surfaces, form pattern mask layer (not shown); Take described pattern mask layer as mask, the described N-type polysilicon layer 107 of etching and the second insulating barrier 105, expose the part surface away from the base polysilicon layer 103 of described the second opening portion, and remainder N-type polysilicon layer 107 is as the N-type emitter; In described base polysilicon layer 104, N-type polysilicon layer 107 and the first insulating barrier 105 sidewall surfaces, form protective layer 108.
Described annealing in process is rapid thermal anneal process, and annealing temperature is 800 ℃～1000 ℃, and annealing time is 10s～50s.In the present embodiment, described annealing temperature is 900 ℃, and annealing time is 30s.Described annealing in process can be carried out in one or more gases such as nitrogen, helium, argon gas, xenon.Annealing in process makes the interior appearance of described oxide layer 121 cavity 122, and a large amount of electronics can directly enter in P type base stage from N-type polysilicon layer 107 by described cavity, thereby reduces the emitter resistance of bipolar transistor.
Described second graphical mask layer can be the mask materials such as photoresist, silica.The material of described protective layer 108 is silicon nitride.Follow-up part polysilicon layer 107 surfaces being positioned at above the second insulating barrier 105 form plug structures, avoid directly on the polysilicon layer 107 on P type base stage 120 surfaces, forming the described P type of over etching base stage 120 in the connector process, and the performance of the bipolar transistor that forms is impacted.Simultaneously, described part base polysilicon layer 104 surface that do not covered by the second insulating barrier 105 form plug structure, and described connector is connected with P type base stage 120 by base polysilicon layer 104.
In other embodiments of the invention, also can after the described N-type polysilicon layer of etching and the second insulating barrier, carry out annealing in process, make the interior appearance of described oxide layer 121 cavity 122.
Described empty 122 between described P type base stage 120 and N-type polysilicon layer 107, and described empty 122 is the vacuum cavity.Because the size in described cavity is minimum, the electrons in N-type polysilicon layer 107 directly arrives described P type base stage 120 by described cavity.
In other embodiments of the invention, carrying out annealing in process, form in described empty 122 process, the lattice structure of described N-type polysilicon layer 107 is recombinated, and with the N-type polysilicon layer 107 on oxide skin(coating) 122 contact-making surfaces, can fill full described empty 122 and directly contact with P type base stage 120.
Please refer to Figure 13 to Figure 15, be the annealing in process process, the interior process schematic diagram that cavity occurs of described oxide layer 121.
Please refer to Figure 13, before carrying out annealing in process, described oxide layer 121 and the partial schematic diagram that is positioned at the N-type polysilicon layer 107 on described oxide layer 121 surfaces.
The material internal of described N-type polysilicon layer 107 has the crystal grain of different crystal orientations and size, and there is crystal boundary in different intergranules.Crystal boundary is the transitional region of different intergranules, is also the zone of the intensive existence of defect, and near grain boundary structure, atomic arrangement is comparatively loose, and foreign atom is easily assembled in the crystal boundary position.When temperature raise, this aggregation tendency can be more obvious.
The surface of described oxide layer 121 is comparatively smooth, and Thickness Ratio is more even.Described oxide layer 121 can form a potential barrier for hole, stops P type base stage 120(to please refer to Figure 12) in hole to the interior diffusion of described N-type polysilicon layer 107, thereby can reduce base current I
b, the multiplication factor of raising bipolar transistor.But because described oxide layer 121 can improve the emitter resistance of emitter, thereby can improve the power consumption of described bipolar transistor, affect transistorized performance.
So, when utilizing described oxide layer 121 to improve the multiplication factor of bipolar transistor, further reduce described emitter resistance, can further improve the performance of described bipolar transistor.
In the present embodiment, after forming described N-type polysilicon layer 107, above-mentioned semiconductor structure is carried out to annealing in process, reduce emitter resistance.
Described annealing in process adopts rapid thermal anneal process, and annealing temperature is 800 ℃～1000 ℃, and annealing time is 10s～50s.In the present embodiment, described annealing temperature is 900 ℃, and annealing time is 30s.Described annealing in process can be carried out in one or more gases such as nitrogen, helium, argon gas, xenon.
Please refer to Figure 14, for carrying out the annealing in process initial stage, described oxide layer 121 and the partial schematic diagram that is positioned at the N-type polysilicon layer 107 on described oxide layer 121 surfaces.
Because N-type polysilicon layer 107 is interior doped with the N-type ion, described N-type ion is easily assembled near crystal boundary, and in the annealing in process process under above-mentioned parameter, the energy of N-type ion increases, and diffusion velocity increases.Near the contact-making surface of described N-type polysilicon layer 107 and oxide layer 121, N-type ion in N-type polysilicon layer 107 spreads downwards, and because the atomic mass of described N-type ion is larger, described atom has certain energy, clash into described oxide layer 121, make described oxide layer 121 surfaces depression occur; And because the concentration of the N-type ion of the crystal boundary position of described N-type polysilicon layer 107 is higher, the thickness of described oxide layer 121 near described crystal boundary position obviously descends, the silica at this place shifts to both sides under the effect of impact of N-type ion, make surperficial depression of oxide layer 121 near the N-type polysilicon layer 170 of grain boundaries.
Simultaneously, in annealing process, the inner atom increased activity of oxide layer 121, under effect of impact due to the silica N-type ion in the N-type polysilicon layer near the N-type polysilicon layer 170 of grain boundaries, to both sides, shift, oxide layer 121 rearranges at the annealing process Atom, makes the thickness away from the oxide layer 121 of the N-type polysilicon layer 170 of grain boundaries improve.
Please refer to Figure 15, for after described annealing in process completes, described oxide layer 121 and be positioned at the partial schematic diagram of the N-type polysilicon layer 107 on described oxide layer 121 surfaces.
After the process annealing in process of certain hour, the interior thickness near N-type polysilicon layer 107 positions of described oxide layer 121 continues to descend, and occurs empty 122.Described empty 122 cover 1%～20% of P type base stage and N shape emitter interface, and preferably, described empty 122 cover 20% of P type base stage and N shape emitter interface.The coverage rate in described cavity can be by the temperature and time adjustment of annealing.
After the interior appearance of described oxide layer 121 cavity 122, a large amount of electronics can directly enter in P type base stage from N-type polysilicon layer 107 by described cavity, thereby reduce the emitter resistance of bipolar transistor.
But due to the mobility in the hole mobility less than electronics, and the coverage rate in described cavity is lower, so, the quantity that hole in P type base stage enters into the N-type polysilicon layer by described cavity seldom, majority still enters into the N-type polysilicon layer by the described oxide layer 121 of tunnelling, forms base current I
b, described base current I
bSize remains unchanged substantially.
Between emitter and base stage, apply bias voltage V
BESituation under, the actual voltage V that is added on emitter and base stage
Be=V
BE-I
e* R
e-I
b* R
b, Ie emitter current wherein, R
eFor emitter resistance, I
bFor base current, R
bFor base resistance.Due to emitter resistance R
eReduce I
bAnd R
bRemain unchanged, so between emitter and base stage, apply bias voltage V
BEIn identical situation, after the employing embodiments of the invention carry out annealing in process, the actual voltage V that is added on emitter and base stage
BeImprove the collector current I that makes
cIncrease, and then make the magnificationfactorβ=I of described bipolar transistor
c/ I
bImprove, thus the performance of raising bipolar transistor.
Please refer to Figure 16, after the interior formation of described oxide layer 121 cavity 122, the partial schematic diagram of electronics and hole flow.
After annealing in process, the interior formation of described oxide layer 121 cavity 122, electronics flows in from N-type polysilicon layer (N-type emitter) to P type base stage by described empty 122, the formation emitter current.Tunneling effect is mainly still passed through in hole in P type base stage, by oxide layer 121 tunnellings, enter in N-type polysilicon layer (N-type emitter), described tunneling effect is to be determined by the thickness of oxide layer 121, because the thickness surface of described oxide layer 121 is very little, so hole current does not have to change substantially.So on the whole, quantity that electronics passes through increases and the quantity in hole not have variation substantially, thereby can improve the emitter current of bipolar transistor.
Please refer to Figure 17, for the emitter resistance rate of bipolar transistor, the base stage saturation current graph of a relation with the coverage rate of oxide layer, wherein, curve 1 is the base stage saturation current curve of bipolar transistor, and curve 2 is the curve of the emitter resistance rate of bipolar transistor.
Adopt the method in the above embodiment of the present invention, by the temperature and time that control is annealed, can adjust empty area, namely adjust the coverage rate of oxide layer on P type base stage and N shape emitter interface.Annealing temperature is higher, annealing time is longer, and the coverage rate of oxide layer is lower.
As can be seen from Figure 17, when the oxide layer coverage rate, reduce to 80% process from 100%, the emitter resistance rate declines by a big margin; And base stage saturation current amplitude of variation is very little.So in the present embodiment, preferred, the coverage rate of described oxide layer is 80%, namely the coverage rate in cavity is 20%, the emitter resistance rate of reduction bipolar transistor that can be by a relatively large margin, and improve multiplication factor.
In the forming process of the bipolar transistor of the present embodiment, described P type base stage and N-type emitter are annealed, make the oxide layer fracture of described P type base surface, produce cavity, improve the multiplication factor of bipolar transistor, reduce emitter resistance.
Although the present invention discloses as above, the present invention not is defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (10)
1. the formation method of a bipolar transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form the N-type collector electrode;
On described N-type collector electrode surface, form P type base stage, described P type base surface has the oxide layer that autoxidation forms;
On described P type base stage, form the N-type emitter;
Described P type base stage and N-type emitter are carried out to annealing in process, reduce emitter resistance.
2. the formation method of bipolar transistor according to claim 1, is characterized in that, what described annealing in process adopted is rapid thermal anneal process.
3. the formation method of bipolar transistor according to claim 1, is characterized in that, the temperature range of described annealing in process is 500 ℃～1200 ℃, and the time of described annealing in process is 10s～30s.
4. the formation method of bipolar transistor according to claim 1, is characterized in that, the thickness of described oxide layer is
5. the formation method of bipolar transistor according to claim 4, is characterized in that, before forming described N-type polysilicon layer, described P type base surface cleaned, and then at described P type base surface autoxidation, forms described oxide layer.
6. the formation method of bipolar transistor according to claim 4, is characterized in that, after annealing in process, some cavities in described oxide layer, occur, and the gross area in described cavity is 1%～20% of annealing in process oxide layer area before.
7. the formation method of bipolar transistor according to claim 1, is characterized in that, the material of described P type base stage is the SiGe of P type doping.
8. the formation method of bipolar transistor according to claim 1, is characterized in that, the method that forms P type base stage on described N-type collector electrode surface comprises: at described semiconductor substrate surface, form the first insulating barrier; Described the first insulating barrier of etching, form the first opening on described N-type collector electrode surface, and described the first opening exposes the surface of described N-type collector electrode; Form the P type base stage of filling full described the first opening.
9. the formation method of bipolar transistor according to claim 8, is characterized in that, the method that forms the N-type emitter in described P type base surface comprises:
At described the first insulating barrier and P type base surface, form the base polysilicon layer, and the second insulating barrier that is positioned at described base polysilicon layer surface;
Described the second insulating barrier of etching and base polysilicon layer, form the second opening that is positioned at described P type base surface, and described the second opening exposes the surface of part P type base stage;
In described the second opening, form the N-type polysilicon layer, described N-type polysilicon layer covers inwall and second surface of insulating layer of the second opening;
On described N-type polysilicon layer surface, form the pattern mask layer, take described pattern mask layer as mask, the described N-type polysilicon layer of etching and the second insulating barrier, expose the part surface away from the base polysilicon layer of described the second opening portion, remaining part N-type polysilicon layer is as the N-type emitter.
10. the formation method of bipolar transistor according to claim 9, is characterized in that, the material of described the second insulating barrier is one or more in tetraethoxysilane, silicon oxynitride, silicon nitride, and described the second insulating barrier is individual layer or multiple-level stack structure.
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| CN103730357A (en) * | 2014-01-07 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | NPN transistor and forming method |
| CN113474878A (en) * | 2018-10-12 | 2021-10-01 | 瑟其福耐斯特有限公司 | Method of fabricating transistor device |
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| CN113474878A (en) * | 2018-10-12 | 2021-10-01 | 瑟其福耐斯特有限公司 | Method of fabricating transistor device |
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