CN103400749B - MIM capacitor device failure analysis method - Google Patents
MIM capacitor device failure analysis method Download PDFInfo
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- CN103400749B CN103400749B CN201310312454.8A CN201310312454A CN103400749B CN 103400749 B CN103400749 B CN 103400749B CN 201310312454 A CN201310312454 A CN 201310312454A CN 103400749 B CN103400749 B CN 103400749B
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Abstract
The present invention relates to a kind of MIM capacitor device failure analysis method, MIM capacitor device is on a silicon substrate and comprise a top crown, the insulating barrier of a bottom crown and between top crown and bottom crown, silicon substrate also at least comprises one and be positioned at metal level above MIM capacitor device, upper and lower pole plate is electrically connected with first, second circuit region of metal level respectively, the method comprises the steps: a), it is no ground to determine that bottom crown has, if no, then perform step b); Otherwise, perform steps d); B), to find and the nearest power bus of MIM capacitor device interfloor distance; Wherein, power bus comprises a ground lead; C), the circuit pathways that connects bottom crown and power bus is formed; D) the electric leakage region determining MIM capacitor device, is detected by voltage contrast.Its by voltage contrast detect MIM capacitor electric leakage region time, the situation that electric leakage degree is less can not be leaked through, be convenient to observation, also more reliable.
Description
Technical field
The present invention relates to field of semiconductor processing and manufacturing, more particularly, relate to a kind of MIM capacitor device failure analysis method.
Background technology
MIM (metal-insulator dielectric-metal) capacitance structure is the capacitance structure formed between the interconnection layer of semiconductor device, and it can be better compatible with the postchannel process of semiconductor manufacturing.Thus be widely used in the such as CMOS such as radio frequency integrated circuit and semiconductor memory processing procedure.
In the mim capacitor structure using the definition of two-layer light shield, its basic structure is distributed as step/intermetallic dielectric layer/the second metal level under the first metal layer/intermetallic dielectric layer/MIM capacitor top crown/MIM insulating barrier/MIM capacitor from top to bottom successively, and wherein upper and lower pole plate is drawn by Via (vertical through hole interconnection technique) or backhaul connection.
As shown in Figure 1, a kind of MIM capacitor device in prior art, comprising: the first metal layer 110, and it comprises the first circuit region 1100 and second circuit district 1101; Second metal level 111, itself and the first metal layer about 110 are oppositely arranged, and separate between the two with a dielectric layer 112; One top crown 120 and a bottom crown 121, is relatively arranged in dielectric layer 112 up and down, does not directly contact, separate between top crown 120 and bottom crown 121 with an insulating barrier 122 with the first metal layer 110, second metal level 111.First circuit region 1100 is connected with a circuit connection 130 (such as by Via or backhaul connection) with top crown 120, and second circuit district 1101 is connected with a circuit connection 131 with bottom crown 121.Namely top crown 120 is formed as a MIM capacitor with bottom crown 121 and insulating barrier 122.
MIM capacitor can be caused to puncture or the technological problems of drain conditions if may exist in preparation technology, namely need to detect MIM capacitor and exist with or without electric leakage region.Passing through voltage contrast (VoltageContrast, be called for short VC) when observing semiconductor element, the VC effect that different elements shows is different, such as, the VC effect of every one deck of PMOS layer metal line on a silicon substrate is bright, and be dark in the VC effect of every one deck of NMOS layer metal line, every one deck VC of the metal line on poly is then the darkest.When MIM capacitor has electric leakage region to exist, MIM capacitor top crown can demonstrate spot zone, otherwise, then occur without spot zone.
In above-mentioned MIM capacitor device, whole MIM capacitor is surrounded by dielectric substantially, even if the dielectric between upper and lower pole plate has drain region, but because be not formed into a leakage path of substrate, the electric leakage region less to electric leakage degree, be difficult to be detected by voltage contrast observe, be also difficult to the relative position accurately determining the electric leakage region of MIM capacitor.
Therefore, providing effectively a kind of and reliable MIM capacitor device failure analysis method, is the technical issues that need to address of the present invention.
Summary of the invention
The object of the present invention is to provide one MIM capacitor device failure analysis method effectively and reliably.
For achieving the above object, technical scheme of the present invention is as follows:
A kind of MIM capacitor device failure analysis method, MIM capacitor device is on a silicon substrate and comprise a top crown, the insulating barrier of a bottom crown and between top crown and bottom crown, silicon substrate also at least comprises one and be positioned at metal level above MIM capacitor device, upper and lower pole plate is electrically connected with first, second circuit region of metal level respectively, the method comprises the steps: a), it is no ground to determine that bottom crown has, if no, then perform step b); Otherwise, perform steps d); B), to find and the nearest power bus of MIM capacitor device interfloor distance; Wherein, power bus comprises a ground lead; C), grind MIM capacitor device to expose the metal connecting line connecting second circuit district and bottom crown, form the metal connecting line that connects second circuit district and power bus, to form the circuit pathways of a connection bottom crown and power bus by FIB technique; D) the electric leakage region determining MIM capacitor device, is detected by voltage contrast.
Preferably, the element injected in FIB technique is Ka, Pt or W.
Preferably, step a) comprising: determine that bottom crown has by layout analysis no ground; Step b) comprising: find the power bus nearest with MIM capacitor device interfloor distance by layout analysis.
Preferably, steps d) specifically comprise: carry out voltage contrast detection by focused ion beam microscope or scanning electron microscopy, determine that top crown is with or without bright spot.
MIM capacitor device failure analysis method provided by the invention, guarantee the circuit pathways of formation one bottom crown to ground, when MIM capacitor has electric leakage region, further define a leakage path from top crown to ground, thus when being detected electric leakage region by voltage contrast, the situation that electric leakage degree is less can not be leaked through, be convenient to observation, also more reliable.
Accompanying drawing explanation
Fig. 1 illustrates MIM capacitor device structural representation in prior art;
Fig. 2 illustrates the MIM capacitor device failure analysis method schematic flow sheet of first embodiment of the invention;
Fig. 3 illustrates the MIM capacitor device failure analysis method schematic flow sheet of second embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
It should be noted that, in any embodiment of the present invention, MIM capacitor device is positioned on a silicon substrate, become Multi-layers distributing, it at least comprises a top crown, the insulating barrier of a bottom crown and between top crown and bottom crown, on silicon substrate, also vertical distribution has multiple metal level, is filled with dielectric layer between adjacent metal; Wherein, upper and lower pole plate can be respectively a wherein metal level, is made up of metal material, also can be formed between two adjacent metal, be made up of TiN or TaN material; Upper and lower pole plate is electrically connected by Via line with first, second circuit region of the first metal layer on silicon substrate respectively.MIM capacitor device similar in prior art shown in said structure and Fig. 1.
As shown in Figure 2, the MIM capacitor device failure analysis method that first embodiment of the invention provides comprises the steps:
Step S10, to determine that bottom crown has no ground, if do not have, then performs step S11; Otherwise, perform step S13.
Particularly, determine that the bottom crown of MIM capacitor device has by layout analysis instrument or architecture design in this step no ground, if there is ground path, then namely skip to following step S13, detected the electric leakage region determining MIM capacitor device by voltage contrast; If there is no ground path, then perform step S11 downwards.
The power bus that step S11, searching and MIM capacitor device are nearest; Wherein, power bus comprises a ground lead.
Particularly, find the power bus nearest with MIM capacitor device in this step by layout analysis, wherein, this power bus at least comprises a ground lead, nearestly refers to that interfloor distance is nearest.
Further, the silicon substrate at MIM capacitor device place also comprises a PMOS transistor, power bus one end is connected with the P+ district of PMOS transistor, and then is connected with substrate, using as ground lead.
The circuit pathways of step S12, formation one connection bottom crown and power bus.
In this step, MIM capacitor device bottom crown and the power bus with ground lead are coupled together, thus when having electric leakage region in MIM capacitor device (insulating barrier between upper and lower pole plate has electric leakage region), arrive again except the circuit pathways of bottom crown to electric leakage region except being formed with a top crown, also be formed with the circuit pathways of a bottom crown to ground, and then define a leakage path again to ground from top crown to bottom crown.
Step S13, to be detected by voltage contrast and determine the electric leakage region of MIM capacitor device.
Particularly, in this step, the electric leakage region of MIM capacitor device can be bright spot at voltage contrast detection display, and the region of leakproof is shown as dark areas.By focused ion beam microscope or scanning electron microscopy, voltage contrast detection is carried out to MIM capacitor device top crown, to determine that top crown is with or without bright spot, thus determine that MIM capacitor device is with or without electric leakage region.
The MIM capacitor device failure analysis method that above-mentioned first embodiment provides, when MIM capacitor device has electric leakage region, define a leakage path again to ground from top crown to bottom crown, when utilizing voltage contrast detection to determine the electric leakage region of MIM capacitor device, the situation that electric leakage degree is less can not be leaked through, be convenient to observation, more reliable.
As shown in Figure 3, the MIM capacitor device failure analysis method that second embodiment of the invention provides is improved by above-mentioned first embodiment and obtains, and it comprises the steps:
Step S20, to determine that bottom crown has no ground, if do not have, then performs step S21; Otherwise, perform step S24.
The power bus that step S21, searching and MIM capacitor device are nearest; Wherein, power bus comprises a ground lead.
Particularly, the power bus nearest with MIM capacitor device interfloor distance is found by layout analysis instrument.
Further, the silicon substrate at MIM capacitor device place also comprises a PMOS transistor, this power bus one end is connected with the P+ district of PMOS transistor, and then is connected with silicon substrate, is formed as ground lead.
Step S22, grinding MIM capacitor device are to expose the metal connecting line connecting second circuit district and bottom crown.
MIM capacitor device in this embodiment, its upper and lower pole plate is electrically connected by Via line with first, second circuit region of the first metal layer on silicon substrate respectively, this the first metal layer can be any layer in more metal layers, but is positioned at the top of MIM capacitor device.For ease of forming the metal connecting line connecting second circuit district and power bus in subsequent process steps S23, and be convenient to carry out voltage contrast detection, in this step, grinding MIM capacitor device connects the second circuit district of the first metal layer and the Via line of MIM capacitor device bottom crown to expose.
Step S23, form by focused ion beam (FocusedIonBeam, be called for short FIB) technique the metal connecting line that connects second circuit district and power bus.
MIM capacitor device in this embodiment, its bottom crown is electrically connected by Via line with the second circuit district of this metal level.In this step, particularly, inject Ka, Pt or W element by FIB technique, deposition formation one connects the metal connecting line of second circuit district and this power bus (with ground lead), and then forms one from bottom crown to second circuit district again to the circuit pathways of this power bus; When MIM capacitor device exists electric leakage region, the leakage path again to ground from top crown to bottom crown can be formed, be convenient to the accuracy rate improving voltage contrast detection.
Wherein, FIB technique realizes by the FIB machine operations provided in prior art, and the voltage contrast that this FIB board also can be further used in subsequent process steps S24 detects.
Step S24, to be detected by voltage contrast and determine the electric leakage region of MIM capacitor device.
In this step, carry out voltage contrast detection by focused ion beam microscope or scanning electron microscopy, determine that top crown is with or without bright spot.As observed bright spot, namely represent that MIM capacitor device exists electric leakage region.Wherein, focused ion beam microscope directly can be provided by FIB board.
Further, in this embodiment, the silicon substrate at MIM capacitor device place is P type semiconductor substrate.
The MIM capacitor device failure analysis method that above-mentioned second embodiment provides, when being detected MIM capacitor electric leakage region by voltage contrast, the situation that electric leakage degree is less can not be leaked through, Detection accuracy is higher, and the method directly realizes by the FIB board provided in prior art, realize simple, operation facility.
Above-describedly be only the preferred embodiments of the present invention; described embodiment is also not used to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (6)
1. a MIM capacitor device failure analysis method, described MIM capacitor device is on a silicon substrate and comprise a top crown, the insulating barrier of a bottom crown and between described top crown and bottom crown, described silicon substrate also at least comprises one and be positioned at metal level above described MIM capacitor device, described upper and lower pole plate is electrically connected with first, second circuit region of described metal level respectively, and described method comprises the steps:
A), to determine that described bottom crown has no ground, if do not have, then performs step b); Otherwise, perform steps d);
B), to find and the nearest power bus of described MIM capacitor device interfloor distance; Wherein, described power bus comprises a ground lead;
C) described MIM capacitor device, is ground to expose the metal connecting line connecting described second circuit district and bottom crown, the metal connecting line that one connects described second circuit district and described power bus is formed, to form the circuit pathways of the described bottom crown of a connection and described power bus by FIB technique;
D) the electric leakage region determining described MIM capacitor device, is detected by voltage contrast.
2. the method for claim 1, is characterized in that, the element injected in described FIB technique is Ka, Pt or W.
3. the method for claim 1, is characterized in that, described step a) comprising: determine that described bottom crown has by layout analysis no ground; Described step b) comprising: find the power bus nearest with described MIM capacitor device interfloor distance by layout analysis.
4. method as claimed in claim 3, it is characterized in that, described silicon substrate also comprises a PMOS transistor, described power bus one end is connected with the P+ district of described PMOS transistor, to form described ground lead.
5. the method for claim 1, is characterized in that, described steps d) specifically comprise: carry out voltage contrast detection by focused ion beam microscope or scanning electron microscopy, determine that described top crown is with or without bright spot.
6. the method according to any one of claim 1 to 5, is characterized in that, described silicon substrate is P type semiconductor substrate.
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| CN104020408B (en) * | 2014-05-26 | 2016-07-06 | 武汉新芯集成电路制造有限公司 | Storage chip bit line failure analysis method |
| CN105810606A (en) * | 2016-04-19 | 2016-07-27 | 上海华虹宏力半导体制造有限公司 | Method for positioning failure point at contact hole level of memory circuit |
| CN106770502A (en) * | 2017-01-03 | 2017-05-31 | 航天科工防御技术研究试验中心 | A kind of position finding and detection method of capacitance short-circuit failure |
| CN114333961B (en) * | 2022-01-10 | 2023-09-05 | 长鑫存储技术有限公司 | Method, device, equipment and storage medium for testing memory array |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1925154A (en) * | 2005-08-31 | 2007-03-07 | 台湾积体电路制造股份有限公司 | Capacitor with metal-insulation-metal structure, semiconductor device and manufacturing method |
| CN101025427A (en) * | 2006-02-17 | 2007-08-29 | 台湾积体电路制造股份有限公司 | Method for judging leakage current in integrated circuit and MOS element |
| CN101577227A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Forming methods of silicon nitride film and MIM capacitor |
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| US20030146492A1 (en) * | 2002-02-05 | 2003-08-07 | International Business Machines Corporation | Nitride etchstop film to protect metal-insulator-metal capacitor dielectric from degradation and method for making same |
| KR100548517B1 (en) * | 2003-12-15 | 2006-02-02 | 매그나칩 반도체 유한회사 | Method for fabricating metal-insulator-metal capacitor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1925154A (en) * | 2005-08-31 | 2007-03-07 | 台湾积体电路制造股份有限公司 | Capacitor with metal-insulation-metal structure, semiconductor device and manufacturing method |
| CN101025427A (en) * | 2006-02-17 | 2007-08-29 | 台湾积体电路制造股份有限公司 | Method for judging leakage current in integrated circuit and MOS element |
| CN101577227A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Forming methods of silicon nitride film and MIM capacitor |
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