CN103383947B - Image device and forming method thereof - Google Patents

Image device and forming method thereof Download PDF

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Publication number
CN103383947B
CN103383947B CN201310022694.4A CN201310022694A CN103383947B CN 103383947 B CN103383947 B CN 103383947B CN 201310022694 A CN201310022694 A CN 201310022694A CN 103383947 B CN103383947 B CN 103383947B
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China
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described
region
grid lamination
substrate
doping
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CN201310022694.4A
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Chinese (zh)
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CN103383947A (en
Inventor
陈思莹
高敏峰
刘人诚
洪丰基
杨敦年
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台湾积体电路制造股份有限公司
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Priority to US61/642,883 priority
Priority to US13/595,494 priority
Priority to US13/595,494 priority patent/US8883544B2/en
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Abstract

The method forming image sensor devices is included in the pixel region of substrate to form isolation well. This isolation well has the first conduction type. Substrate above isolation well is formed grid lamination. Mask layer is formed in the top of isolation well and covers at least most of of grid lamination. Use grid lamination and mask layer as mask, multiple hotchpotch is injected pixel region, to form doping isolation parts. This multiple hotchpotch has the first conduction type. Form source region and the drain region of the phase offside being positioned at grid lamination in the substrate. 2nd conduction type of source region and drain region is contrary with the first conduction type. Present invention also offers image device and forming method thereof.

Description

Image device and forming method thereof

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the right of priority of No. 61/642,883 US provisional patent in order submission May 4 in 2012, its whole content is hereby expressly incorporated by reference.

Technical field

The present invention relates to image sensor devices and the method for the formation of image sensor devices.

Background technology

Image sensor devices is in the digital imaging system of such as digital still camera or Digital Video composition parts. Image sensor devices comprises for detection light and records the picture element matrix (or grid) of the intensity (brightness) of the light detected. Such as, this picture element matrix passes through stored charge (the more many electric charges of light are more high) in response to light. Such as, then, it may also be useful to the electric charge (by other circuit) accumulated is to be provided in suitable applications (such as digital camera) color and brightness used. One type of image sensor devices is back-illuminated type (BSI) image sensor devices. BSI image sensor devices projects the amount of the light of the back surface (its image sensor circuit supporting BSI image sensor devices) of substrate for detecting. Grids of pixels is positioned at the front side of substrate, and substrate is enough thin, thus the light projecting substrate dorsal part can arrive grids of pixels. Compared with front illuminated (FSI) image sensor devices, BSI image sensor devices provides the harmful interference reduced.

Unicircuit (IC) technology is constantly modified. This kind of improvement generally includes scaled device geometries to obtain lower manufacturing cost, higher device integration density, faster speed and good performance. Except geometrical dimension except reducing is obtained advantage, also directly image sensor devices is improved.

Due to device bi-directional scaling, therefore, carry out image sensor devices technology constantly improving the picture quality improving image sensor devices further. Although the manufacture method of existing image sensor devices and image sensor devices is usually enough for expectation target, but, along with device continues scaled, they can not be completely satisfactory in all respects.

Summary of the invention

In order to solve defect existing in prior art, according to an aspect of the present invention, it provides a kind of method forming image sensor devices, described method comprises: form isolation well in the pixel region of substrate, wherein, described isolation well has the first conduction type; Described substrate above described isolation well forms grid lamination; Above described isolation well, form mask layer and described mask layer cover described grid lamination at least major part; Described grid lamination and described mask layer being used as a part that mask injects described pixel region to form doping isolation parts, wherein, described doping is isolated parts and is had described first conduction type; And in described substrate, form source region and the drain region of the phase offside being positioned at described grid lamination, wherein, described source region and described drain region have two conduction type contrary with described first conduction type.

In the method, implementing described implantation step with the tiltangle�� relative to the front of described substrate, described tiltangle�� is in the scope of about 75 to about 90 degree.

In the method, described doping isolation parts extend length L in the lower section of described grid lamination from the edge of described grid lamination.

In the method, described length L is less than about 0.1 ��m.

In the method, described mask layer covers whole grid lamination.

In the method, described isolation well below the front of described substrate with described front distance W1, wherein, described doping isolation parts have the degree of depth D entering described substrate1, and described distance W1Substantially described degree of depth D is equaled1��

In the method, parts are isolated around described source region and described drain region by described doping.

In the method, the region covered by described mask layer is defined described source region and described drain region.

The method comprises further: formed in described pixel region by described doping isolation parts around at least one photoelectric detector.

According to a further aspect in the invention, provide a kind of method forming image sensor devices, described method comprises: arranging the pixel region with front in the substrate, wherein, the 2nd axis by the first axis with described first axes normal limits described front; Forming grid lamination along described first axis on described front in described pixel region, wherein, described grid lamination has the length X along described first axis1With the 2nd length Y along described 2nd axis1; Mask layer is formed to be limited with source region above the part at least major part and the described front of described grid lamination; And with tiltangle��, multiple hotchpotch is injected in the substrate not covered by described mask layer, to form doping isolation parts in described pixel region, wherein, described doping isolation parts are around described active region.

In the method, described active region has the length X along described first axis2, and described length X2It is not more than described length X1��

In the method, described tiltangle�� at about 75 degree in the scope of 90 degree.

In the method, described doping isolation parts extend length L in the lower section of described grid lamination from the edge of described grid lamination.

In the method, described length L is less than about 0.1 ��m.

In the method, after injecting the step of described multiple hotchpotch, comprise further: source region and the drain region forming the phase offside being positioned at described grid lamination in described active region.

The method comprises further: formed in described substrate by described doping isolation parts around at least one photosensitive region, wherein, the conduction type of at least one photosensitive region described with described doping isolate parts conduction type contrary.

According to another aspect of the invention, it provides a kind of image sensor devices, comprising: substrate, there is the first surface; Isolation well region, be arranged in described substrate and at the lower section on described first surface and the described first surperficial distance W1; Grid lamination, be arranged on above described isolation well region described substrate described first on the surface, described grid lamination has edge; And doping isolation parts, it is arranged in described substrate and around active region, wherein, described grid lamination is arranged on described active region, and described doping isolation parts have the corner, top alignd at the described edge with described grid lamination and extend length L from the edge of described grid lamination below described grid lamination.

In this image sensor devices, described doping isolation parts have the protruding part at the described edge of contiguous described grid lamination.

In this image sensor devices, described length L is less than about 0.1 ��m.

In this image sensor devices, described isolation well region and described doping isolation parts have identical conduction type.

Accompanying drawing explanation

According to the following detailed description with the accompanying drawing each side that the present invention may be better understood. It should be emphasized that according to the standard practices in industry, various parts are not drawn to scale. In fact, in order to clearly discuss, the size of various parts can be arbitrarily increased or reduce.

Fig. 1 is the vertical view of the image sensor devices of the multiple embodiments according to the present invention;

Fig. 2 A is the amplification plan view of the pixel region in the image sensor devices of Fig. 1;

Fig. 2 B is the amplification plan view in the one part of pixel region in the image sensor devices of Fig. 2 A;

Fig. 2 C is the pixel region (the line B-B ' along Fig. 2 A intercepts) of the image sensor devices of the one or more embodiments according to the present invention and the sectional view of outer peripheral areas;

Fig. 3 is the schema of the method for the formation image sensor devices of the one or more embodiments according to the present invention;

Fig. 4 A to Fig. 7 B is vertical view and the sectional view in the one part of pixel region of the image sensor devices of Fig. 2 A being in each manufacturing stage of multiple embodiments of the method according to Fig. 3.

Embodiment

It can be appreciated that the following disclosure provides the multiple different embodiment of the different characteristics for realizing the present invention or example. Below by parts and layout described specific example to simplify the present invention. Certainly, these are only example and are not intended to restriction the present invention. And, in the following description, above the 2nd parts, form the first parts can comprise the embodiment forming the first parts and the 2nd parts in the way of directly contacting, it is also possible to comprise the embodiment that other parts can be formed between the first parts and the 2nd parts the first parts are not directly contacted with the 2nd parts. And, use such as " at ... top ", " ... above ", " in ... bottom " and " ... the term of relative space position below " is to provide the relative space position relation between element, and these terms are not intended to implicit any absolute direction. For the purpose of simply clear, it is possible to draw arbitrarily various parts with different ratios.

Fig. 1 is the vertical view of the image sensor devices 100 of the many aspects according to the present invention. In the embodiment shown, this image sensor devices is back-illuminated type (BSI) image sensor devices. This image sensor devices 100 comprises the array of pixel region 101. Such as, each pixel region 101 is all arranged to row (C1To Cx) and row (such as, R1To Ry). Term " pixel region " refers to the unit comprising parts (such as, photoelectric detector and various circuit), and these parts can comprise the various semiconducter device for electromagnetic radiation converts to electrical signal. Photoelectric detector in pixel region 101 can comprise photorectifier, complementary metal oxide semiconductor (CMOS) image sensor, charge coupled device (CCD) sensor, active sensor device, passive sensing device and/or other sensors. This pixel region 101 can be designed to have multiple sensors type. Such as, a group in pixel region 101 can be cmos image sensor and another group in pixel region 101 can be passive sensing device. Such as, in the embodiment shown, each pixel region 101 can comprise the photoelectric detector (grating type photoelectric detector) of the intensity for recording light (radiation) or brightness.Each pixel region 101 can comprise various semiconducter device, such as, comprises transfering transistor, reset transistor, source follower transistor, selection transistor, the various transistor of other suitable transistors or their combination. Other circuit, input terminus and/or output terminal can be arranged in the outer peripheral areas of image sensor devices 100. Be arranged in these circuit of outer peripheral areas, input terminus and/or output terminal and be connected to pixel region 101, be provided for the operating environment of pixel region 101 and support with the communication external of pixel region 101. In order to for simplicity, the present invention describes the image sensor devices comprising single pixel region; But, the array of this kind of pixel region can form the image sensor devices 100 shown in Fig. 1 usually.

Fig. 2 A is the amplification plan view of the pixel region 101 in the image sensor devices 100 on substrate (not illustrating in fig. 2). This pixel region 101 refers to comprise at least one photoelectric detector 106 and the unit for multiple circuit that electromagnetic radiation converts to electrical signal. In the embodiment shown, this photoelectric detector 106 comprises the photorectifier of the intensity for recording light (radiation) or brightness. This pixel region 101 can comprise the multiple transistor or their combination with transfering transistor 110, reset transistor 112, source follower transistor 114, selection transistor 116 or other suitable transistors. Pixel region 101 can also comprise the various doped regions in substrate, such as, and doped region 118A, 118B and 120. Doped region 118A and 118B is arranged to the regions and source/drain of aforementioned transistor. Doped region 120 is also called as floating diffusion zone 120. This floating diffusion zone 120 is between the grid lamination and the grid lamination of reset transistor 112 of transfering transistor 110, and is in the regions and source/drain of each in transfering transistor 110 and reset transistor 112. The grid lamination of conductive component 132 and source follower transistor 114 a part of overlapping, and it is connected to floating diffusion zone 120. Such as, image sensor devices 100 also comprises the multiple isolation parts (the dielectric isolation parts 126 in parts 108 and Fig. 2 C are isolated in the doping in Fig. 2 A) formed in the substrate and prevents leakage current between each region with the multiple regions at the bottom of isolation liner. In the embodiment shown, doping isolation parts 108 are formed in pixel region 101 with by mutually isolated to photoelectric detector 106, transfering transistor 110, reset transistor 112, source follower transistor 114 and selection transistor 116. Fig. 2 B illustrates the amplification plan view of the part 200 of pixel region 101. The corresponding grid lamination of source follower transistor 114 is arranged on pixel region 101. The doped region 118B being arranged as regions and source/drain is set to be close to the grid lamination of source follower transistor 114. Doping isolation parts 108 are around the grid lamination of doped region 118B and source follower transistor 114.

Fig. 2 C is the pixel region 101 (intercepting along the line B-B ' in Fig. 2 A) of image sensor devices 100 and the sectional view of outer peripheral areas 102. Image sensor devices 100 comprises the substrate 104 with front 104A and back side 104B. In the embodiment shown, substrate 104 is the semiconducter substrate comprising silicon. Can selection of land or additionally, this substrate 104 comprises: another kind of elemental semiconductor, such as, germanium and/or diamond;Compound semiconductor, comprises silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; Alloy semiconductor, comprises SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP or their combination. Substrate 104 can be semiconductor-on-insulator (SOI). Semi-conductor 104 can have the various doped structures based on design requirement (such as p-substrate or n-type substrate). In certain embodiments, p-type refers to make hole as the majority carrier in semiconductor material, and n type refers to make electronics as the majority carrier in semiconductor material. In the embodiment shown, substrate 104 is p-substrate. The P type hotchpotch that substrate 104 adulterates comprises boron, gallium, indium, other suitable p-type dopant or their combination.

Pixel region 101 comprises at least one photoelectric detector 106 of such as photorectifier, and this photoelectric detector comprises photosensitive region 106A and immovable bed (pinnedlayer) 106B. This photosensitive region 106A forms the doped region with the first conduction type hotchpotch (especially along the front 104A of substrate 104) in the substrate 104. In the embodiment shown, photosensitive region 106A is n type doped region. Immovable bed 106B is the doped layer overlapping with photosensitive region 106A at the 104A place, front being positioned at substrate 104. The conduction type of the hotchpotch of immovable bed 106 is contrary with the conduction type of the hotchpotch of photosensitive region 106A. In the embodiment shown, immovable bed 106B is p-type input horizon.

Pixel region 101 comprises various transistor further, such as, transfering transistor 110 (as shown in Figure 2 A), reset transistor 112 (as shown in Figure 2 A), source follower transistor 114 and selection transistor 116 (as shown in Figure 2 A). Each transistor all has the corresponding grid lamination being arranged on above the front 104A of substrate 104. In the embodiment shown, the grid lamination of source follower transistor 114 is positioned at the top in isolation well region 109. The end face in isolation well region 109 is away from front 104A distance W1. This distance W1Between aboutTo aboutScope in. The bottom surface in isolation well region 109 extends in substrate 104 further towards back side 104B. 2nd conduction type in this isolation well region 109 is contrary with first conduction type of photosensitive region 106A. In the embodiment shown, isolation well region 109 is p-type doped region. The dosage that isolation well region 109 uses is about 1 �� 1011To 3 �� 1011atoms/cm3. Isolation well region 109 is around the photosensitive region 106A of photoelectric detector 106. The grid lamination of each transistor includes gate dielectric and gate electrode layer. Such as, gate dielectric comprises dielectric materials (silicon-dioxide, high-k (high k) dielectric materials), other dielectric materialss or their combination. The example of high-k dielectric material comprises HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium dioxide, aluminium sesquioxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy or their combination. Gate electrode layer comprises polysilicon and/or metal (comprising Al, Cu, Ti, Ta, W, Mo), TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN or their combination.

Outer peripheral areas 102 can comprise and is connected to pixel region 101 and thinks that pixel region 101 provides sensing circuit and/or the pilot circuit of operating environment. In the embodiment shown, PMOS transistor 122 and nmos pass transistor 124 is shown.The regions and source/drain 122B with p-type conductivity that PMOS transistor 122 comprises grid lamination 122A and is formed in n type trap 122C. The regions and source/drain 124B with n-type conductivity that nmos pass transistor 124 comprises grid lamination 124A and is formed in p-type trap 124C.

Multiple dielectric isolation parts 126 that image sensor devices 100 comprises the multiple doping isolation parts 108 in the substrate 104 being formed in pixel region 101 further and is formed in the substrate 104 of outer peripheral areas 102. At the bottom of doping isolation parts 108 and dielectric isolation parts 126 isolation liner, multiple region of 104 is to prevent leakage current between each region. In the embodiment shown, doping isolation parts 108 and dielectric isolation parts 126 by PMOS transistor 122 and nmos pass transistor 124, photoelectric detector 106, transfering transistor 110 (as shown in Figure 2 A), reset transistor 112 (as shown in Figure 2 A), source follower transistor 114 and select transistor 116 (as shown in Figure 2 A) to keep apart.

Each in doping isolation parts 108 all has the degree of depth D extending to substrate 104 from front 104A1. This degree of depth D1AboutTo aboutScope in. Doping isolation parts 108 have two conduction type identical with isolation well region 109. The degree of depth D of doping isolation parts 1081Substantially the distance W of the front 104A of isolation well region 109 with substrate 104 is equaled1. Doping isolation parts 108 and isolation well region 109 are around the photosensitive region 106A of photoelectric detector 106 to prevent lateral leakages path between photoelectric detector 106 and other regions. In the embodiment shown, doping isolation parts 108 are p-type doped region. The P type hotchpotch of doping isolation parts 108 comprises boron (B), BF2, gallium, indium, other suitable p-type dopant or their combination etc. The dosage of this hotchpotch is about 2 �� 1012To about 8 �� 1012atoms/cm3. Can selection of land, when isolation well region 109 is n type doped region, doping isolation parts 108 be also n type doped region. The N-type dopant of doping isolation parts 108 comprises phosphorus, arsenic, other suitable n-type dopant or their combination.

Dielectric isolation parts 126 comprise silicon-dioxide, silicon nitride, silicon oxynitride, other insulating material or their combination. Each dielectric isolation parts 126 all has the degree of depth D extending to substrate 104 from front 104A2. This degree of depth D2AboutTo aboutScope in. Such as, the formation of dielectric isolation parts 126 can comprise photoetching process, etching from front 104A to the etch process of the groove substrate 104 and the depositing operation carrying out filling groove (with the use of chemical vapor deposition process) with dielectric materials.

Image sensor devices 100 comprises the multilayer interconnection part (MLI) 128 being arranged on and (being included in above photoelectric detector 106) above the front 104A of substrate 104 further. MLI128 is connected to multiple parts of the image sensor devices 100 of such as photoelectric detector so that multiple parts of image sensor devices 100 can suitably in response to irradiation light (image-forming radiation). Such as, MLI128 comprises the multiple conductive components 130 and 132 being respectively vertical interconnect 130 (contact element and/or through hole 130) and horizontal interconnect 132 (such as line 132). Multiple conductive component 130 and 132 comprises the electro-conductive material of such as aluminium, aluminium/silicon/copper alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide or their combination.

Multiple conductive components 130 and 132 of MLI128 are in interlayer dielectric (ILD) layer 134.ILD layer 134 can comprise silicon-dioxide, silicon nitride, silicon oxynitride, TEOS oxide, mix phosphorosilicate glass (PSG), mix boron-phosphorosilicate glass (BPSG), mix fluorine silex glass (PSG), carbon-doped silicon oxide, BLACK(black brill) (is manufactured by the AppliedMaterialsofSantaClara company in California), amorphous fluorocarbon, high-k (high k) dielectric materials, polyimide or their combination. ILD layer 134 can be multilayered structure.

Carrier wafer 136 is arranged on the top of the front 104A of substrate 104. In the embodiment shown, carrier wafer 136 is bonded to MLI128. Carrier wafer 136 comprises silicon or glass. Carrier wafer 136 can provide protection for the multiple parts (such as, photoelectric detector 106) on the front 104A being formed in substrate 104, and can also be provided for processing physical strength and the support of the back side 104B of substrate 104.

Image sensor devices 100 comprises the doped layer 138 at the 104B place, the back side being arranged on substrate 104 further. This doped layer 138 is formed by injection technology, diffusion technique, thermal treatment process or their combination. In the embodiment shown, doped layer 138 comprises p-type (the 2nd conduction type) hotchpotch, such as, and boron, gallium, indium or their combination. This doped layer 138 has the doping depth d that the back side 104B from substrate 104 extends to substrate 104. The doping depth of doped layer 138, doping content, doping profile or their combination can be selected to optimize picture quality by increasing quantum yield, reduce dark current or reduce white pixel defect.

Image sensor devices 100 may further include and is arranged on anti-reflecting layer 140 above the back side 104B of substrate 104, colour filter 142 and lens 144. This anti-reflecting layer 140 comprises the dielectric materials of such as silicon nitride or silicon oxynitride.

Colour filter 142 is arranged on the top of anti-reflecting layer 140, and is directed at the photosensitive region 106A of photoelectric detector 106. Colour filter 142 is designed to the visible ray that filtering is in predetermined wavelength outside. Such as, this colour filter 142 filtering arrives the visible ray except the light of red wavelength, green wavelength or blue wavelength of photoelectric detector 106. In an embodiment, colour filter 142 comprises the polymkeric substance based on dyestuff (or based on pigment) for filtering special frequency channel (for example, it may be desirable to light of wavelength).

Lens 144 are arranged on the top of colour filter 142 and are also directed at the photosensitive region 106A of photoelectric detector 106. Lens 144 can be in the multiple position being furnished with photoelectric detector 106 and colour filter 142 so that incident radiation 146 is focused on the photosensitive region 106A of photoelectric detector 106 by lens 144. Can selection of land, it is possible to put upside down colour filter 142 and the position of lens 144 so that lens 144 are arranged between anti-reflecting layer 140 and colour filter 142.

In the operation of the image sensor devices 100 according to one or more embodiment, image sensor devices 100 is designed to receive the radiation 146 transmitted towards the back side 104B of substrate 104. Then, this incident radiation 146 arrives substrate 104 and corresponding photoelectric detector 106 from colour filter 142 through anti-reflecting layer 140, specifically, arrives photosensitive region 106A. When photoelectric detector 106 is exposed in incident radiation 146, this photoelectric detector 106 is in response to incident radiation 146 stored charge. Referring again to Fig. 2 A, when the gate turn-on of transfering transistor 110, electric charge is sent to floating diffusion zone 120 from photoelectric detector 106.By the connection of conductive component 132 (as shown in Figure 2 A), the charge conversion from floating diffusion zone 120 can be become voltage signal by source follower transistor 114. Select transistor 116 can allow to read electron device and read single row of pixels array. Reset transistor 112 is used as switch so that floating diffusion zone 120 resets. When reset transistor 112 conducting, floating diffusion zone 120 is connected to power supply effectively, to remove all stored charges.

Fig. 3 is the schema that the one or more embodiment according to the present invention forms the method 300 of image sensor devices. At operation 301 place of the schema of the method 300, substrate has pixel region. This pixel region is formed isolation well region. This isolation well region has the first conduction type. In the embodiment shown, the first conduction type is p-type polarity. Can selection of land, the first conduction type is n type polarity. In an embodiment, isolation well region is away from the front distance W of substrate1. This distance W1AboutTo aboutScope in. Next, method 300 proceeds to operation 302, wherein, the top in isolation well region on substrate, form grid lamination. Method 300 proceeds to operation 303, and wherein, mask layer is formed in the top in isolation well region and covers at least most of of grid lamination. Method 300 proceeds to operation 304, and wherein, multiple hotchpotch is injected into not to be had in pixel region that masked layer covers, to form the doping isolation parts around grid lamination. This multiple hotchpotch has the first conduction type. In the embodiment shown, the first conduction type is p-type polarity. Can selection of land, the first conduction type is n type polarity. Method 300 proceeds to operation 305, wherein, forms the regions and source/drain being positioned on the phase offside of grid lamination in the substrate. This regions and source/drain has two conduction type contrary with the first conduction type. In the embodiment shown, the 2nd conduction type is n type polarity. Can selection of land, the 2nd conduction type is p-type polarity. Further, it is to be understood that can before method 300, period and extra step is provided afterwards.

Fig. 4 A to Fig. 7 B is vertical view and the sectional view that the various embodiments of the method according to Fig. 3 are in the part 200 of the pixel region 101 in image sensor devices 100 of each manufacturing stage. For the ease of understanding the inventive concept of the present invention, simplify each accompanying drawing.

Referring again to Fig. 3, method 300 is from operation 301 and proceeds to operation 302.

Fig. 4 A is the vertical view of the part 200 of the pixel region 101 after implementation and operation 301 and 302. Fig. 4 B is the sectional view of the part 200 intercepted along the line A-A ' in Fig. 4 A. Substrate 104 has front 104A and back side 104B. The 2nd axis (along line A-A ') by the first axis (along line B-B ') with the first axes normal limits front 104A. Substrate 104 is the semiconducter substrate comprising silicon. In the embodiment shown, substrate 104 is p-type silicon substrate. The P type hotchpotch that substrate 104 adulterates comprises boron, gallium, indium, other suitable p-type dopant or their combination. Can selection of land, substrate 104 is included in the suitable material mentioned in earlier paragraphs.

Pixel region 101 is formed the isolation well region 109 with the first conduction type. Isolation well region 109 is positioned at the distance W of the lower section of the front 104A of substrate1Place. This distance W1?To aboutScope in. The bottom surface in isolation well region 109 extends in substrate 104 towards back side 104B.This isolation well region 109 is formed by lithographic patterning and injection technology. In the embodiment shown, isolation well region 109 is p-type doped region. The P type hotchpotch in isolation well region 109 comprises boron, gallium, indium or their combination. The dosage of hotchpotch is from about 1 �� 1011atoms/cm3To about 3 �� 1011atoms/cm3. Can selection of land, such as, this isolation well region 109 is for comprising the n type doped region of n-type dopant (phosphorus, arsenic, other suitable n-type dopant or their combination).

Next, above isolation well region 109 and on the front 104A of substrate 104, form grid lamination. In the embodiment shown, for illustrative purposes, the grid lamination of source follower transistor 114 is shown. The grid lamination of source follower transistor 114 is also referred to as grid lamination 114. Grid lamination 114 has the length X along the first axis (along line B-B ')1With the length Y along the 2nd axis (along line A-A ')1. Isolation well region 109 is formed grid lamination 114. The length Y of grid lamination 1141It is restricted to the trench length of source follower transistor 114. Grid lamination 114 is formed by comprising the appropriate process of deposition, lithographic patterning and etch process. Grid lamination 114 comprises gate dielectric and gate electrode layer. Gate dielectric comprises dielectric materials, such as, and silicon-dioxide, high-k dielectric material, other dielectric materialss or their combination. The example of high-k dielectric material comprises HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium dioxide, aluminium sesquioxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy or their combination. Gate electrode layer comprises polysilicon and/or metal (comprising Al, Cu, Ti, Ta, W, Mo), TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN and their combination.

Referring again to Fig. 3, method 300 proceeds operation 303. Mask layer is formed in the top in isolation well region and covers at least most of of grid lamination.

Fig. 5 is the vertical view carrying out operating the part 200 of the pixel region 101 after 303. Mask layer 202 (shown in broken lines) is formed in the top in isolation well region 109 and covers at least most of of grid lamination 114. Mask layer 202 is configured to limit the active region 203 of source follower transistor 114. The regions and source/drain (being depicted as 118B in fig. 7) of source follower transistor 114 can be formed in active region 203 in technique subsequently. The active region 203 that masked layer 203 covers has the length X along the first axis (along line B-B ')2With the length Y along the 2nd axis (along line A-A ')2. The length X of active region 2032It is restricted to the groove width of source follower transistor 114. The length X of active region 2032No longer than the length X along the first axis (along line B-B ') of grid lamination 1141. The regions and source/drain (being 118B as shown in Fig. 7 A) formed subsequently is defined by active region 203. In an embodiment, the masked layer 202 of whole grid lamination 114 covers, and the edge of mask layer 202 aligns along the first axis (along line B-B ') with the edge of grid lamination 114 substantially. In another embodiment, as shown in Figure 5, along the first axis (along line B-B '), the sub-fraction of grid lamination 114 does not have masked layer 202 to cover. Mask layer 202 is formed, to limit the parts being positioned at above isolation well region 109 and grid lamination 114 by photoengraving pattern metallization processes.Such as, photoengraving pattern metallization processes comprises coating photoresist material, soft baking, mask registration, exposure, postexposure bake, lithographic glue, cleans (rising), dries (firmly toasting) or their combination.

Referring again to Fig. 3, the method 300 proceeds operation 304. Multiple hotchpotch is injected in the pixel region not having masked layer to cover to form the doping isolation parts around grid lamination. This multiple hotchpotch has first conduction type identical with the conduction type in isolation well region. In the embodiment shown, the first conduction type is p-type polarity. Can selection of land, the first conduction type is n type polarity.

Fig. 6 A is at the vertical view carrying out operating the part 200 of the pixel region 101 after 304. Fig. 6 B is the sectional view of the part 200 intercepted along line A-A ' in Fig. 6 A. Fig. 6 C is the sectional view of the part 200 intercepted along line B-B ' in Fig. 6 A. With reference to Fig. 6 B and Fig. 6 C, multiple hotchpotch 204 is injected in the part 200 of the pixel region 101 not having masked layer 202 to cover, to form doping isolation parts 108. This multiple hotchpotch has first conduction type identical with isolation well region 109. Doping isolation parts 108 are formed as the active region 203 of the source follower transistor 114 covered around masked layer 202. In the embodiment shown, doping isolation parts 108 are p-type doped regions. The P type hotchpotch of doping isolation parts 108 comprises boron (B), BF2, gallium, indium, other suitable p-type dopant or their combination. The dosage of hotchpotch is about 2 �� 1012To about 8 �� 1012atoms/cm3Scope in. Implement to inject with the tiltangle�� (about 75 degree to about 90 degree) between the plane parallel with front 104A and the incoming beam of ion implantation. Each doping isolation parts 108 all has and extends to the degree of depth D substrate 104 from front 104A1. This degree of depth D1AboutTo aboutScope in. The degree of depth D of doping isolation parts 1081Substantially the distance W of the front 104A of isolation well region 109 with substrate 104 is equaled1. Doping isolation parts 108 and isolation well region 109 around source follower transistor 114 active region 203 and also around the photosensitive region 106A (as shown in Fig. 2 A and 2C) of photoelectric detector 106. The lateral leakages path that may exist can be eliminated between photoelectric detector 106 and source follower transistor 114. As degree of depth D1It is less thanTime, doping isolation parts 108 can not each region of electric isolution. Therefore, the device performance of image sensor devices 100 can reduce. As degree of depth D1It is greater thanTime, mask layer 202 can not effectively prevent from damaging during high energy ion injection technology below e grid lamination to obtain degree of depth D1��

Owing to implementing to inject with tiltangle��, therefore, as shown in Figure 6 C, doping isolation parts 108 can extend length L in the lower section of grid lamination 114 from the edge 114E of grid lamination 114 along the first axis (along line B-B '). Grid lamination 114 is positioned at above the part of doping isolation parts 108 with length L. Length L is less than about 0.1 ��m. The profile of doping isolation parts 108 has along the first axis (along line B-B ') from the protruding part of the edge 114E of grid lamination 114. Corner, top (topcorner) 108C of this profile aligns with the edge 114E of grid lamination 114. When tiltangle�� is greater than 90 degree, grid lamination 114 is not positioned at the part top of doping parts 108. May the edge section of good isolation gate stack 114, it is possible to can not well control the device performance of image sensor devices 100.In some cases, there is the electric current leakage paths of the edge 114E (along the 2nd axis A-A ' direction) along grid lamination 114, such that it is able between the working life of image sensor devices 100 period cause the short circuit between the regions and source/drain formed after a while. When tiltangle�� is less than 75 degree, doping isolation parts 108 can extend too many in the lower section of grid lamination 114, can shorten channel width X2, and device performance can be affected. In certain embodiments, doping isolation parts 108 are comprise n-type dopant (such as phosphorus, arsenic), other suitable n-type dopant or their combination.

Referring again to Fig. 3, method 300 proceeds operation 305, in this operation, forms the regions and source/drain being positioned on the phase offside of grid lamination in the substrate. Regions and source/drain has two conduction type contrary with the first conduction type. In the embodiment shown, the 2nd conduction type is n type polarity. Can selection of land, the 2nd conduction type is p-type polarity.

Fig. 7 A is the vertical view carrying out operating the part 200 of the pixel region 101 after 305. Fig. 7 B is the sectional view of the part 200 intercepted along the line A-A ' in Fig. 7 A. Regions and source/drain 118B is formed on the opposition side of the grid lamination 114 above isolation well region 109 on a substrate 104. Regions and source/drain 118B has the length X along the first axis (along line B-B ')2. The length X of regions and source/drain 118B2It is defined as the channel width of source follower transistor 114. As mentioned by above-mentioned paragraph, mask layer 202 is limited with source region 203, defines regions and source/drain 118B by active region 203. Along the first axis (along line B-B '), the length X of active region 2032It is not more than the length X of grid lamination 1141. As shown in Figure 7 A, along the first axis (along line B-B '), outside the edge 118C of regions and source/drain 118B is not projected into the edge 114E of grid lamination 114. By this kind of structure, between the working life of image sensor devices 100, leakage current path can not along the edge 114E of grid lamination 114 from arrival source region, drain region. This kind of structure prevents image sensor devices 100 to be shorted. Therefore, it is defined at grid width (channel width) X along the electric current between the regions and source/drain 118B of the 2nd axis (along line A-A ')2In. Can the performance of accurately control device.

2nd conduction type of regions and source/drain 118B is contrary with the first conduction type of doping isolation parts 108 and isolation well region 109. And, the floating diffusion zone 120 in Fig. 2 A has the 2nd conduction type, to be configured to for one in the regions and source/drain of each of transfering transistor 110 and reset transistor 112. In the embodiment shown, transistor 114 is nmos pass transistor. Regions and source/drain 118B is n type doped region. The N-type dopant of regions and source/drain 118B comprises phosphorus, arsenic, other suitable n-type dopant or their combination. Can selection of land, transistor 114 is PMOS transistor. Regions and source/drain 118B is p-type doped region. The P type hotchpotch of regions and source/drain 118B comprises boron (B), BF2, gallium, other suitable p-type dopant or their combination.

It is appreciated that such as, as shown in Figure 2 C, it is possible to extra step was provided before and after, during the operation 305 of method 300. Image sensor devices 100 comprises the photoelectric detector 106 (such as photorectifier) with photosensitive region 106A and immovable bed 106B further.This photosensitive region 106A forms the doped region with the 2nd conduction type hotchpotch (especially along the front 104A of substrate 104) in the substrate 104. 2nd conduction type of photosensitive region 106A is contrary with the first conduction type of doping isolation parts 108 and isolation well region 109. In the embodiment shown, photosensitive region 106A is n type doped region. Immovable bed 106B is the doped layer overlapping with the photosensitive region 106A at the 104A place, front being positioned at substrate 104. The conduction type of the hotchpotch of immovable bed 106B is contrary with photosensitive region 106A's. In the embodiment shown, immovable bed 106B is p-type input horizon. By doping isolation parts 108 and isolation well region 109 around photoelectric detector 106.

Image sensor devices 100 comprises the multilayer interconnection part (MLI) 128 being arranged on above the front 104A of substrate 104 further. Such as, MLI128 comprises the multiple conductive components 130 and 132 being respectively vertical interconnect 130 (contact element and/or through hole 130) and horizontal interconnect 132 (such as line 132). Conductive component 130 and 132 is formed by the appropriate process formation vertical interconnect and horizontal interconnect comprising depositing operation, photoengraving pattern metallization processes and etch process.

Multiple conductive components 130 and 132 of MLI128 are arranged in interlayer dielectric (ILD) layer 134. ILD layer 134 can comprise silicon-dioxide, silicon nitride, silicon oxynitride, TEOS oxide, mix phosphorosilicate glass (PSG), mix boron-phosphorosilicate glass (BPSG), mix fluorine silex glass (FSG), carbon-doped silicon oxide, low k dielectric or their combination. The suitable technique that can revolve painting, chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) by comprising forms ILD layer 134. In an embodiment, it is possible to form MLI128 and ILD layer 134 in the integrated technique comprising inlay.

In certain embodiments, the other processing step after MLI128 is formed it is included in. As shown in Figure 2 C, carrier wafer 136 is combined on MLI128. The back side 104B that carrier wafer 136 is process substrate 104 provides physical strength and support. The back side 104B of substrate 104 is applied the flatening process of such as chemically machinery polished (CMP) technique, to reduce the thickness of substrate 104. The doped layer 138 through back side 104B is formed by injection technology, diffusion technique, annealing process or their combination. Anti-reflecting layer 140, colour filter 142 and lens 144 are set above the back side 104B of substrate 104. Colour filter 142 and lens 144 are directed at the photosensitive region 106A of photoelectric detector 106.

In the above-described embodiment, image sensor devices 100 comprises p-type doped substrate 104. Determine that the above-mentioned various doped structures for various parts (such as photosensitive region 106A, doping isolation parts 108, isolation well region 109 and floating diffusion zone 120) are consistent with the formation of the image sensor devices 100 with p-type doped substrate. Can selection of land, image sensor devices 100 can comprise the n-type material in n type doped substrate 104 or substrate 104. Determine that the above-mentioned various doped structure for various parts is consistent with the formation of the image sensor devices 100 with n type doped substrate.

The various embodiments of the present invention all may be used for improving the performance of image sensor devices. Such as, doping isolation parts 108 are formed in pixel region 101 by injection technology. This invention removes the defect produced during forming shallow trench isolation off member (STI) in traditional method in pixel region due to etching damage.When not having etching damage, the present invention can reduce dark current or reduce the white pixel defect of image sensor devices. In another example, before the injection technology for the formation of doping isolation parts 108, grid lamination 114 is formed. Grid lamination 114 provides the physics parts with sharp edge, for carrying out better lithography alignment between mask layer 202 Formation period. This of mask layer 202 is aligned between grid lamination 114 and the doping isolation parts 108 formed after a while to provide accurate coverage control. The injection for the isolation parts 108 that adulterate is implemented with tiltangle��. This doping isolation parts 108 can extend length L in the lower section of grid lamination 114 from the edge 114E of grid lamination 114 along the first axis (along line B-B '). Eliminate along the edge 114E of the grid lamination 114 electric current leakage paths possible to source region from drain region. Prevent the short circuit between regions and source/drain 118B.

An aspect of the present invention describes the method forming image sensor devices. The pixel region of substrate forms isolation well. This isolation well has the first conduction type. Substrate above isolation well is formed grid lamination. Mask layer is formed in the top of isolation well and covers at least most of of grid lamination. Multiple hotchpotch is injected into not to be had in pixel region that masked layer covers, to form the doping isolation parts around active region. Grid lamination is arranged on active region. Multiple hotchpotch has the first conduction type. Form the source region being positioned on the phase offside of grid lamination and drain region in the substrate. Source region and drain region have two conduction type contrary with the first conduction type.

The another aspect of the present invention describes a kind of method forming image sensor devices. Pixel region has front in the substrate. The 2nd axis by the first axis with the first axes normal limits this front. The front of pixel region forms grid lamination along the first axis. Grid lamination has the length X along the first axis1With the 2nd length Y along the 2nd axis1. The part top of at least major part and front that mask layer is formed in grid lamination is to be limited with source region. With tiltangle�� multiple hotchpotch is injected into and do not have in substrate that masked layer covers, thus in pixel region, form doping isolation parts. Doping isolation parts are around grid lamination and active region.

Invention further describes image sensor devices. This image sensor devices comprises the substrate with the first surface. It is provided with isolation well region in the substrate. The distance W of this isolation well region in the lower section on the first surface1. Grid lamination is arranged on the isolation well overlying regions on the first surface of substrate. Grid lamination has edge. Doping isolation parts be arranged in substrate and around active region. Grid lamination is arranged on active region. Doping isolation parts have the corner, top alignd at the edge with grid lamination, and extend length L in the lower section of grid lamination from the edge of grid lamination.

Although having describe in detail the present embodiment and advantage thereof, it is understood that when not deviating from present subject matter and the scope that claims limit, various different change can be made, replace and change. And, the specific embodiment of technique that the scope of the application is not limited in this specification sheets describing, machine, manufacture, material component, device, method and step. Should understand as those of ordinary skill in the art, by the present invention, existing or develop from now on for performing and the function substantially identical according to described corresponding embodiment of the present invention or obtain the technique of substantially identical result, machine, manufacture, material component, device, method or step and can be used according to the present invention.Therefore, claims should be included in the scope of such technique, machine, manufacture, material component, device, method or step.

Claims (19)

1. forming a method for image sensor devices, described method comprises:
Forming isolation well in the pixel region of substrate, wherein, described isolation well has the first conduction type;
Described substrate above described isolation well forms grid lamination;
Above described isolation well, form mask layer and described mask layer cover described grid lamination at least major part;
Described grid lamination and described mask layer are used as a part that mask injects described pixel region to form doping isolation parts, wherein, described doping isolation parts have the protruding part below at least partially in described grid lamination, and described doping isolation parts have described first conduction type; And
Forming source region and the drain region of the phase offside being positioned at described grid lamination in described substrate, wherein, described source region and described drain region have two conduction type contrary with described first conduction type.
2. method according to claim 1, wherein, implements described implantation step with the tiltangle�� relative to the front of described substrate, and described tiltangle�� is in the scope of 75 to 90 degree.
3. method according to claim 2, wherein, described doping isolation parts extend length L in the lower section of described grid lamination from the edge of described grid lamination.
4. method according to claim 3, wherein, described length L is less than 0.1 ��m.
5. method according to claim 1, wherein, described mask layer covers whole grid lamination.
6. method according to claim 1, wherein, described isolation well below the front of described substrate with described front distance W1, wherein, described doping isolation parts have the degree of depth D entering described substrate1, and described distance W1Substantially described degree of depth D is equaled1��
7. method according to claim 1, wherein, isolates parts around described source region and described drain region by described doping.
8. method according to claim 1, wherein, defines described source region and described drain region in the region covered by described mask layer.
9. method according to claim 1, comprises further:
Described pixel region is formed by described doping isolation parts around at least one photoelectric detector.
10. forming a method for image sensor devices, described method comprises:
Arranging the pixel region with front in the substrate, wherein, the 2nd axis by the first axis with described first axes normal limits described front;
Forming grid lamination along described first axis on described front in described pixel region, wherein, described grid lamination has the length X along described first axis1With the 2nd length Y along described 2nd axis1;
Mask layer is formed to be limited with source region above the part at least major part and the described front of described grid lamination; And
With tiltangle��, multiple hotchpotch is injected in the substrate not covered by described mask layer, to form doping isolation parts in described pixel region, wherein, described doping isolation parts have the protruding part below at least partially in described grid lamination, and described doping isolation parts are around described active region.
11. methods according to claim 10, wherein, described active region has the length X along described first axis2, and described length X2It is not more than described length X1��
12. methods according to claim 10, wherein, described tiltangle�� is in the scope of 75 degree to 90 degree.
13. methods according to claim 10, wherein, described doping isolation parts extend length L in the lower section of described grid lamination from the edge of described grid lamination.
14. methods according to claim 13, wherein, described length L is less than 0.1 ��m.
15. methods according to claim 10, after injecting the step of described multiple hotchpotch, comprise further:
Described active region is formed source region and the drain region of the phase offside being positioned at described grid lamination.
16. methods according to claim 10, comprise further:
Described substrate is formed by described doping isolation parts around at least one photosensitive region, wherein, the conduction type of at least one photosensitive region described with described doping isolate parts conduction type contrary.
17. 1 kinds of image sensor devices, comprising:
Substrate, has the first surface;
Isolation well region, be arranged in described substrate and at the lower section on described first surface and the described first surperficial distance W1;
Grid lamination, be arranged on above described isolation well region described substrate described first on the surface, described grid lamination has edge; And
Doping isolation parts, it is arranged in described substrate and around active region, wherein, described grid lamination is arranged on described active region, described doping isolation parts have the corner, top alignd at the described edge with described grid lamination and extend length L from the edge of described grid lamination below described grid lamination, wherein, described doping isolation parts have the protruding part at the described edge of contiguous described grid lamination.
18. image sensor devices according to claim 17, wherein, described length L is less than 0.1 ��m.
19. image sensor devices according to claim 17, wherein, described isolation well region and described doping isolation parts have identical conduction type.
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