This application claims the priority for the 61/625th, No. 530 U.S. Provisional Application submitted on April 17th, 2012,
Disclosure is fully incorporated in this by reference.
Background technology
HSDPA (High Speed Downlink Packet Access, high-speed slender body theory) is that a kind of movement is logical
Believe agreement.The agreement can be used for providing Packet data service in WCDMA downlinks, the transmission on a 5MHz carrier wave
Rate is up to 8-10Mbit/s (as used MIMO technology, then up to 20Mbit/s).In the concrete realization, adaptive tune is used
System and coding (AMC), multiple-input and multiple-output (MIMO), hybrid automatic repeat-request (HARQ), fast dispatch, fast cell selection
Etc. technologies.
In data transmission link, such as downlink, physical layer (L1) need will come from UE (user equipment,
User equipment) decoding data be reported to high level, such as L1C layers (physical layer control layers) or (the media access control of MAC layer/rlc layer
Preparative layer/wireless chain control layer), wherein reported data amount is larger under HSDPA business.
DMA (Direct Memory Access, direct memory access (DMA)) is the valuable feature of modern computer, it allows
The hardware device of friction speed is communicated, a large amount of interrupt loads without CPU to be depended on (central processing unit).If no
Using DMA, then CPU needs to copy to buffer from source the data of each segment, then they is written back to new
Place.During this process, CPU can not be used for others work.Wherein, object is realized using dma controller
Manage the data transmission between layer and high level.Dma controller is substantially the controller in channel, by DMA channel directly by data from
Physical layer moves high level.
Referring to Fig.1, it is to be reported to decoding data high-rise traditional moving data mode, wherein L1 to be moved using DMA
Data, L1C/MAC responding DMAs are interrupted, and L1 data are handled.Specifically, L1 is obtained after decoding data by configuring DMA controls
Device, moving data;After DMA, high level response is interrupted, and L1 data are handled.
More specifically, it is shown in Fig. 1 go out decoding data is reported to high-rise traditional moving data mode pass through
Following steps are realized:
First, ASIC (Application Specific Integrated Circuit, application-specific integrated circuit) will be
The decoding data exported by decoder stored in buffer (not shown) in ASIC is transferred to the L1 buffers in L1
(L1BUFF) in.Wherein, the capacity of L1 buffers is greater than or equal to the capacity of the buffer in ASIC.
Then, L1 configures dma controller and is transferred to the decoding data being stored in L1 buffers by dma controller
In the shared memory of high-rise (L1C/MAC).Wherein, L1 configures source address, destination address and the size of data of dma controller.
After dma controller is judged to be transmitted whole decoding datas by the size of data configured, one can be triggered
All decoding datas are transferred to high level by a interruption (Interrupt) to high level, notice high level.Due to dma controller category
In hardware, therefore above-mentioned down trigger belongs to hardware trigger.
When high level receives the interruption of triggering, which is responded, the decoding to being transferred in shared memory
Data are read out and for example sort the processing of splicing etc.
In above-mentioned traditional moving data mode that decoding data is reported to high level, due to the shared storage in high level
The write-in and reading of device carry out respectively, therefore the shared memory only needs to support single port operation, i.e., same time
The operation that can only be written or be read, and both can not be carried out at the same time.
It is above-mentioned according to Fig. 1 decoding data is reported to high-rise traditional moving data mode for single-carrier system row it
Effectively.But when in face of multicarrier system, UE has multipath decoding data and reports, per road if supporting high order modulation
Data volume bigger is reported, therefore there are many disadvantages for which.
Invention content
It is therefore desirable to have many drawbacks of traditional approach can be evaded, L1 buffers expense is increased without, reduces high-rise ring
The DMA transfer method and system for multicarrier system answered number, twoport is avoided to operate.
Exemplary embodiments of the present invention relate to the DMA transfer methods and mechanism for multicarrier system.
According to an illustrative embodiment of the invention, a kind of DMA transfer method for multicarrier system is provided, is wrapped
It includes:Receive the every decoding data all the way being directed in multichannel carrier transmitted successively by dma controller;And in response to being directed to
Through transmitting the interrupt signal of all decoding datas, the received decoding data of processing.
Preferably, further include that dma controller receives decoding data from physical layer in the method.
Preferably, in the method, interrupt signal comes from physical layer.
Preferably, further include in the method:The information about decoding data is received for processing decoding data.
Preferably, in the method, information is received from the source of decoding data.
According to an illustrative embodiment of the invention, a kind of DMA transfer device for multicarrier system is additionally provided, is wrapped
It includes:For receiving the device for every decoding data all the way in multichannel carrier transmitted successively by dma controller;And it uses
In in response to for the interrupt signal for having transmitted all decoding datas, handling the device of received decoding data.
Preferably, in said device, dma controller receives decoding data from physical layer.
Preferably, in said device, interrupt signal comes from physical layer.
Preferably, further include in said device:For receiving the information about decoding data for processing solution yardage
According to device.
Preferably, in said device, information is received from the source of decoding data.
According to an illustrative embodiment of the invention, a kind of DMA transfer system for multicarrier system is additionally provided, is wrapped
It includes:Data transmission device is configured to transmit every decoding data all the way in multichannel carrier successively to dma controller;
Dma controller is configured to transmit decoding data successively to data processing equipment;And data processing equipment, it is configured to ring
Ying Yu is directed to the interrupt signal for having transmitted all decoding datas, handles decoding data.
Preferably, in the system, data transmission device is also configured to data processing equipment Transmission signal.
Preferably, in the system, data transmission device is also configured to transmit about decoding to data processing equipment
The information of data is for processing decoding data.
Preferably, in the system, dma controller is also configured to transmit about decoding data to data processing equipment
Information for handle decoding data.
Embodiments of the present invention have the following advantages:
1. since high level is it is not necessary that in response to the interruption triggered by dma controller, it is multiple frequently to reduce high-rise processing
Miscellaneous degree.
2. actually the decoding data from multichannel carrier can be uniformly processed due to interrupting every time, improve
The data processing amount interrupted every time.
3. it is interrupted since high level needs cpu resource to handle, when interruption times are reduced, interrupt service subroutine
Expense can also reduce, to reduce high-rise MIPS (Million Instructions Per Second, processing million per second
Grade instruction number).
4. since L1 buffers only need to store the bufferings of an ASIC in multiple ASIC buffers in the same time
The decoding data of device saves depositing for L1 buffers without storing the decoding data from multiple ASIC buffers simultaneously
It stores up space and cost can be reduced by reducing the memory capacity of L1 buffers.
5. due to the shared memory of high level of same time need to only be read out or write operation in a kind of operation, because
This high-rise shared memory only needs to support single port operation, to save manufacture and space cost.
Specific implementation mode
Below with reference to attached drawing, various exemplary embodiments of the present invention are described in detail.Flow chart and block diagram in attached drawing show
The architecture, function and operation in the cards of method and system according to various embodiments of the present invention is gone out.It should
Note that each box in flowchart or block diagram can represent a part for a module, program segment, or code, the module,
A part for program segment or code may include one or more logic functions for realizing defined in each embodiment
Executable instruction.It should also be noted that in some alternative implementations, the function of being marked in box can also be according to not
It is same as the sequence marked in attached drawing generation.For example, two boxes succeedingly indicated can essentially be basically executed in parallel,
Or they can also be executed in a reverse order sometimes, this depends on involved function.It should also be noted that stream
The combination of each box in journey figure and/or block diagram and the box in flowchart and or block diagram can use and execute regulation
The dedicated hardware based systems of functions or operations realize, or the group of specialized hardware and computer instruction can be used
It closes to realize.
It should be appreciated that providing these illustrative embodiments just for the sake of keeping those skilled in the art more preferable geographical
It solves and realizes the present invention in turn, be not intended to limit the scope of the invention in any way.
In multi-carrier systems, if according to above-mentioned traditional approach, exist for the multiple of each road-load wave in ASIC
ASIC buffers (ASIC BUF), when being decoded data transmission, ASIC will store each in each ASIC buffers
The decoding data of road-load wave is transferred to when decoding completion in the L1 buffers in L1.Due in multi-carrier systems, per all the way
Code block size it is close, therefore may also be very close to their decoding end time point.At this point, since L1 needs pass through
Decoding data is transferred to high-rise but only gathers around that there are one DMA channels by DMA channel, therefore L1 needs in order transmission solution yardage successively
According to.Because the deadline point (i.e. introduction time point) of decoding data is closely, L1 will be by DMA channel
It is likely to subsequent when the previously incoming decoding data stored in L1 buffers is to higher layer transmission and comes from another ASIC buffers
Decoding data can also be passed to L1.Since DMA channel is occupied at this time, which is also required to storage and arrives L1 buffers
In.Therefore, the capacity of L1 buffers is required to accommodate the decoding data stored in all ASIC buffers, slow so as to cause L1
The expense for rushing device is very big.
Further, since the multipath decoding data from multichannel carrier can very closely pass through dma controller in time
The shared memory being transferred in high level, and the decoding data from carrier wave all the way is often transferred, dma controller all can be to high level
Triggering is interrupted, and therefore, high level is likely to require the multiple interruptions of processing within the short time (for example, 5 milliseconds), and then repeatedly triggers number
According to process flow.For example, when multicarrier system includes two-way carrier wave, high level may need to handle in a short time in two
It is disconnected;When multicarrier system includes more multichannel carrier, high level may need to handle more multiple interrupt in the short time.Due to each interruption
When need to move larger data, and carrying out processing for multiple interruptions in the short time can make processing become very complicated, because
This this can bring prodigious processing pressure to the high level of multicarrier system, prodigious challenge is brought to its processing capacity.
In multi-carrier systems, UE has multipath decoding data and reports, if supporting the roads high order modulation Ze Mei reported data
Measure bigger.If still continuing to use traditional approach, first, L1 needs the decoding data of prodigious spatial cache preservation multichannel.Secondly,
Multiple Interrupt is probably sent to high level in shorter time interval, if in this period in the frequent responding DMAs of L1C/MAC
Disconnected, trigger data process flow can bring very big pressure to high level.Again, due to being transferred to high-rise be total to by dma controller
The introduction time for enjoying the decoding data of the multichannel carrier in memory is very close, it is therefore possible to high level to being stored in
It is subsequent to come from another way when the previously incoming decoding data from carrier wave all the way in shared memory is read
The decoding data of carrier wave just needs to be written in shared memory, this just needs shared memory to support twoport operation, you can with
It is carried out at the same time the operation of write-in or reading, so as to cause the increase of shared memory cost.DMA and L1C/MAC under this mode
A block storage may be operated simultaneously, need higher cost if selecting multiport memory, and if still selecting single port
Single port shared memory, which needs to increase, is carried out at the same time memory storage the protection for reading and writing operation.
It is respectively the DMA for multicarrier system according to an illustrative embodiment of the invention with reference to Fig. 2 and Fig. 3
The flow chart of the schematic diagram of Transmission system and DMA transfer method 300 for multicarrier system.
Below in conjunction with Fig. 2 and Fig. 3 to the DMA transfer for multicarrier system according to an illustrative embodiment of the invention
Method and system is described.
According to Fig.3, in step S101:The decoded multipath decoding data of process from UE are respectively stored in
It is respectively used to per in multiple ASIC buffers of decoding data all the way in ASIC.
Certain illustrative embodiments according to the present invention can be decoded the multichannel data in a frame as unit of frame
After be respectively stored in multiple ASIC buffers.
With continued reference to Fig. 3, in step s 102, ASIC will be stored in the decoding data in multiple ASIC buffers according to solution
Code completion sequence is transferred to successively in the L1 buffers in L1.
The capacity of certain illustrative embodiments according to the present invention, L1 buffers can be just slightly larger than or delay equal to ASIC
The capacity of device is rushed, therefore, ASIC is when transmission stores the decoding data in multiple ASIC buffers successively, only in L1 buffers
In the previously incoming decoding data outflow from some ASIC buffer after the completion of, just into L1 buffers, transmission comes from it
The decoding data of his ASIC buffers.
It should be appreciated that certain illustrative embodiments according to the present invention, the capacity of L1 buffers can be enabled sufficiently large, from
And allow to without when the previously incoming decoding data outflow from some ASIC buffer in L1 buffers is completed
Afterwards, the decoding data from other ASIC buffers is just transmitted into L1 buffers.
With continued reference to Fig. 3, in step s 103, L1 is by dma controller by the solution yardage from multiple ASIC buffers
According to being transferred to high level and be stored in the shared memory in high level.Wherein, L1 needs pair before transmission decoding data to high level
Dma controller is configured, and the content of configuration includes source address, destination address and size of data.
Certain illustrative embodiments according to the present invention, dma controller are often being transferred from an ASIC buffer
In decoding data after, to one interruption of high level triggering, but it is high-rise this interruption is not responded, but continue waiting for L1
The decoding data from other ASIC buffers is transmitted to it, and repeatedly incoming decoding data is uniformly stored in shared storage
In device.
Certain illustrative embodiments according to the present invention can also configure dma controller so that it is transferring
It does not interrupt to high level triggering from after the decoding data in any ASIC buffers, or is buffered from all ASIC transferring
It is just interrupted to high level triggering after decoding data in device.
With continued reference to Fig. 3, in step S104, high level is uniformly processed in response to interrupt signal and is stored in shared memory
In the decoding data from multichannel carrier.In this way, during high level only once responds after the transmission for receiving multiple decoding data
It is disconnected, such as only interrupted once in 5 milliseconds, interrupt the harmful effect that may be brought so as to avoid frequent response.
Certain illustrative embodiments according to the present invention, L1 by dma controller by multiple ASIC from ASIC
After the decoding data of the multichannel carrier of buffer is all transferred in high-rise shared memory, interrupt signal is triggered to high level.
Certain illustrative embodiments according to the present invention, dma controller by from L1 be passed to, from the multiple of ASIC
After the decoding data of the multichannel carrier of ASIC buffers is all transferred in high-rise shared memory, is triggered to high level and interrupt letter
Number.
It should be appreciated that just to high level after dma controller often transfers the decoding data in an ASIC buffer
It is high-rise only to indicating that the decoding data of last road-load wave in a frame is transferred in shared memory when triggering one is interrupted
Break signal is responded.
Certain illustrative embodiments according to the present invention are triggering interrupt signal from L1 or dma controller to high level
When, the information such as data format of the high-rise decoding data transmitted can be notified simultaneously, so that high level handles shared storage
Decoding data in device.
Certain illustrative embodiments according to the present invention are triggering interrupt signal from L1 or dma controller to high level
Afterwards, the high-rise information such as data format that oneself can detect transmitted decoding data, and it is total according to these information processings
Enjoy the decoding data in memory.
It will be appreciated that though present invention is mainly applied to multicarrier system, but the present invention is not precluded and can effectively answer
For single-carrier system.When applied to single-carrier system, equally triggered to high-rise interruption, so that L1 can be more by L1
Add directly control is high-rise when to handle decoding data.
The DMA for multicarrier system according to an illustrative embodiment of the invention is described above by reference to Fig. 3 and Fig. 2
Transmission method and system.It will be appreciated that though according to particular order (step S101, step S102, step S103, step S104)
The operation of this method is described, still, this, which does not require that or implies, to execute these operations according to the particular order, or
It is to have to carry out operation shown in whole to realize desired result.It is held on the contrary, the step of describing in flow chart can change
Row sequence.Additionally or alternatively, it is convenient to omit multiple steps are merged into step and executed by certain steps, and/or by one
A step is decomposed into execution of multiple steps.
Fig. 4 shows the schematic block diagram of the computer system suitable for being used for putting into practice embodiment of the present invention.Such as Fig. 4 institutes
Show, computer system may include:CPU (central processing unit) 401, RAM (random access memory) 402, ROM are (read-only to deposit
Reservoir) 403, system bus 404, hard disk controller 405, keyboard controller 406, serial interface controller 407, parallel interface control
Device 408, display controller 409, hard disk 410, keyboard 411, serial peripheral equipment 412, concurrent peripheral equipment 413 and display processed
414.In such devices, what is coupled with system bus 404 has CPU401, RAM402, ROM403, hard disk controller 405, keyboard
Controller 406, serialization controller 407, parallel controller 408 and display controller 409.Hard disk 410 and 405 coupling of hard disk controller
It closes, keyboard 411 is coupled with keyboard controller 406, and serial peripheral equipment 412 is coupled with serial interface controller 407, concurrent peripheral
Equipment 413 is coupled with parallel interface controller 408 and display 414 is coupled with display controller 409.
It should be appreciated that the structure diagram described in Fig. 4 is shown for illustrative purposes only, rather than to model of the present invention
The limitation enclosed.In some cases, it can increase or reduce certain equipment as the case may be.
Below with reference to Fig. 5, it illustrates the schematic frames suitable for the mobile terminal 500 for putting into practice embodiment of the present invention
Figure.In the example depicted in fig. 5, mobile terminal 500 is a mobile device with wireless communication ability.However, it is possible to manage
Solution, this is merely exemplary and not limiting.Other kinds of mobile terminal can also easily implementation using the present invention
Mode, such as portable digital-assistant (PDA), pager, mobile computer, mobile TV, game station, calculating on knee
Machine, camera, video recorder, GPS device and other kinds of voice and text communication system.Fixed mobile terminal equally may be used
Easily to use embodiments of the present invention.
Mobile terminal 500 includes one or antenna 512, is operationally led to transmitter 514 and receiver 516
Letter.Mobile terminal 500 further includes processor 512 or other processing elements, provide respectively the signal for going to transmitter 514 and
Receive the signal from receiver 516.Signal include according to the signaling information of the air-interface standard of appropriate cellular system, and
Further include the data that user speech, the data of reception and/or user generate.In this regard, mobile terminal 500 can utilize one
Or multiple air interface standard, communication protocols, modulation type and access style are operated.As demonstration, mobile terminal
500 can be grasped according to any agreement in multiple first generation, the second generation, the third generation and/or forth generation communication protocol etc.
Make.For example, mobile terminal 500 can be according to the second generation (G) wireless communication protocol IS-136 (TDMA), GSM and IS-95
(CDMA) it is operated, or is wirelessly communicated according to the third generation (G) of such as UMTS, CDMA2000, WCDMA and TD-SCDMA
Agreement is operated to be operated, or according to forth generation (4G) wireless communication protocol and/or similar agreement.
It is appreciated that processor 512 includes the circuit realized needed for the function of mobile terminal 500.For example, processor 512
May include digital signal processor device, microprocessor device, various analog-digital converters, digital analog converter and other support electricity
Road.The control of mobile terminal 500 and signal processing function distribute therebetween according to the respective ability of these equipment.Processor 512
Thus the function of convolutional encoding and intertexture is carried out before can also being included in modulation and transmission to message and data.Processor 312
Internal voice coder can also be also comprised, and may include internal data modem.In addition, processor 512 can
To include pair function that can be operated with one or more software programs stored in memory.For example, processor 512 can
Linker, such as traditional Web browser can be operated.Linker can then allow mobile terminal 300 for example by
Emit according to Wireless Application Protocol (WAP), hypertext transfer protocol (HTTP) etc. and receive web content and is (such as location-based
Content and/or other web page contents).
Mobile terminal 500 can also include user interface, such as may include earphone or loud speaker 524, ringer
522, microphone 526, display screen 528 and input interface 531, all these equipment are both coupled to processor 512.Mobile terminal
500 may include keypad 530.Keypad 530 may include traditional number key (0-9) and relative keys (#, *), and be used for
Operate other keys of mobile terminal 500.Alternatively, keypad 530 may include traditional QWERTY keypad arrangement.Keypad
530 can also include various soft keys associated with function.Mobile terminal 500 can also include camera model 536, for capturing
Statically and/or dynamically image.
Particularly, display screen 528 may include touch-screen and/or neighbouring formula screen, and user can be by directly grasping
Make screen and operates mobile terminal 500.At this point, display screen 528 functions simultaneously as both input equipment and output equipment.Such
In embodiment, input interface 531 may be configured to receive user for example, by common pen, special stylus and/or finger
The input provided on display screen 528, including give directions input and gesture input.Processor 512 is configurable to detect such defeated
Enter, and identifies the gesture of user.
In addition, mobile terminal 500 may include such as control stick interface equipment or other be used for input interface.It is mobile
Terminal 500 further includes battery 534, such as vibrating battery group, for powering for the various circuits needed for operation mobile terminal 500,
And mechanical oscillation are optionally provided as detectable output.
Mobile terminal 500 may further include Subscriber Identity Module (UIM) 538.UIM538 is typically to have built-in place
Manage the memory devices of device.UIM538 for example may include subscriber identity module (SIM), Universal Integrated Circuit Card (UICC), lead to
With subscriber identity module (USIM), removable Subscriber Identity Module (R-UIM) etc..UIM538 is commonly stored related to mobile subscriber
Cell.
Mobile terminal 500 can also have memory.For example, mobile terminal 500 may include volatile memory 540,
Such as include the volatile random access memory (RAM) of the cache area for data temporary storage.Mobile terminal 500
It can also include other nonvolatile memories 542, can be Embedded and/or moveable.Nonvolatile memory
542 can include additionally or alternatively such as EEPROM and flash memory.Memory can be used with memory mobile terminal 500
Multiple pieces of information and data in Arbitrary Term, to realize the function of mobile terminal 500.For example, memory 540 and 542 can
To be configured to store the computer program instructions for realizing the method 300 described above in association with Fig. 3.
It should be appreciated that the structure diagram described in Fig. 5 is shown for illustrative purposes only, rather than to model of the present invention
The limitation enclosed.In some cases, it can increase or reduce certain equipment as the case may be.
For conclusion, according to an illustrative embodiment of the invention, provide it is a kind of decoding data is reported to it is high-rise
Report method.Wherein, L1 takes data from ASIC successively, is moved by DMA.But high level is not to be responded after each DMA
It interrupts, but waits until that all downlink datas all move success in a frame, a specific interruption is triggered by L1, notifies high-rise present frame
Data are for interior all HS-DSCH (High-Speed Downlink Shared Channel, high-speed downlink shared channel)
Terminate through moving, and notifies the necessary informations such as high level data format.High level only responds this interruption, trigger data processing stream
Journey.
Wherein, L1 only stores one piece of DMA data every time, and when multipath reception does not need to increase memory overhead to cache each road
Data save the spaces L1.
Although detailed description of the preferred embodimentsthe present invention has been described by reference to several, should be appreciated that from foregoing description not
In the case of being detached from true spirit of the present invention, can each embodiment of the present invention be modified and be changed.In this specification
Description is only used for illustrative, and is not considered as restrictive.The present invention is directed to cover in appended claims
Included various modifications and equivalent arrangements in spirit and scope.Scope of the following claims is to be accorded the broadest interpretation, from
And include all such modifications and equivalent structure and function.