CN103378844A - Input/output interface device - Google Patents
Input/output interface device Download PDFInfo
- Publication number
- CN103378844A CN103378844A CN2012101915719A CN201210191571A CN103378844A CN 103378844 A CN103378844 A CN 103378844A CN 2012101915719 A CN2012101915719 A CN 2012101915719A CN 201210191571 A CN201210191571 A CN 201210191571A CN 103378844 A CN103378844 A CN 103378844A
- Authority
- CN
- China
- Prior art keywords
- input
- output
- voltage
- circuit
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000008054 signal transmission Effects 0.000 claims description 26
- 238000012937 correction Methods 0.000 claims description 6
- 230000000052 comparative effect Effects 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 abstract description 8
- 230000009471 action Effects 0.000 description 9
- 238000004088 simulation Methods 0.000 description 8
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000001915 proofreading effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Landscapes
- Analogue/Digital Conversion (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an input/output interface device, which comprises a digital input/output control circuit, a logic operation circuit, an analog core circuit, a switch and a voltage offset circuit. The digital input/output control circuit receives a digital output enable signal to transmit or receive a transmission signal through an input/output pad. The logic operation circuit is used for generating a digital output enable signal and an analog input output enable signal. The switch receives the control signal and is switched on or off according to the control signal. The voltage offset circuit receives and transfers the voltage of the analog input/output enable signal to generate a control signal.
Description
Technical field
The invention relates to a kind of input/output interface device, and particularly relevant for the input/output interface device of a kind of multiplexing of transmission analog signal and digital signal.
Background technology
In existing System on Chip/SoC (system on chip, SOC), its input and output pin that has can be divided into the digital IO pin of transmission of digital signals usually, and the analog input output pin of transmission of analogue signal.Signal transmission when wherein, the digital IO pin is commonly used to carry out the test of exploitation, chip of firmware (firmware) and/or chip misarrangement.The analog input output pin then can be used as the monitoring of the analog signal in the chip, or analog signal transmission that also can be when carrying out the chip misarrangement.
Please refer to Fig. 1, Fig. 1 is the pin configuration figure of existing System on Chip/SoC 100.Wherein, include digital core circuitry 110 and analog core circuit 120 in the System on Chip/SoC 100.And digital core circuitry 110 and analog core circuit 120 are coupled to respectively digital IO weld pad 111 and analog input output weld pad 112, and carry out respectively the action of the signal transmission of numeral and simulation by digital IO weld pad 111 and analog input output weld pad 112.These digital IO weld pads 111 and analog input output weld pad 112 is configured in around the System on Chip/SoC 100 usually, and a certain size the area of accounting for.In the more and more less situation of semiconductor processes size, the chip area that these digital IO weld pads 111 and analog input output weld pad 112 accounts for is can not be effectively reduced and so-called weld pad has occured limit (pad limit) (that is chip area is dominated by the weld pad number, irrelevant with the size of core circuit wherein) state, and the increase of the cost that causes.In addition, in order to save the packaging cost of System on Chip/SoC 100, the weld pad quantity of System on Chip/SoC 100 also is restricted, and therefore, how effectively to reduce the sum of weld pad, becomes those of ordinary skills' important topic.
Summary of the invention
The invention provides a kind of input/output interface device, can carry out by identical input and output weld pad the transmission action of digital signal or analog signal.
The present invention proposes a kind of input/output interface device, comprises digital IO control circuit, logical operation circuit, analog core circuit, switch and voltage offset circuits.The input and output weld pad of digital IO control circuit coupling chip receives digital output enable signal to transmit or to receive signal transmission by the input and output weld pad.Logical operation circuit couples the digital IO control circuit, in order to produce digital output enable signal and analog input output enable signal.Switch series is connected between input and output weld pad and analog core circuit, switch receive and according to control signal with conducting or disconnection.Voltage offset circuits couples logical operation circuit, and the voltage that receives and shift analog input output enable signal produces control signal.
In one embodiment of this invention, above-mentioned voltage offset circuits is heightened the voltage of analog input output enable signal to produce control signal.
In one embodiment of this invention, when above-mentioned switch disconnected, the digital IO control circuit transmitted signal transmission by the input and output weld pad.
In one embodiment of this invention, above-mentioned digital IO control circuit also couples digital core circuitry and logical operation circuit, and digital core circuitry transmits or receive signal transmission by the digital IO control circuit.
In one embodiment of this invention, above-mentioned input/output interface device also comprises correction resistance, be serially connected between this input and output weld pad and reference voltage, and the analog core circuit comprises reference current generator, current supply and reference current correcting circuit.Reference current generator is adjusted the reference current that reference current generator produces according to control voltage.Current supply couples reference current generator, and produce at least one for induced current and correcting current according to reference current, wherein, in order at least analog core electronic circuit to the analog core circuit to be provided, and provide correcting current by proofreading and correct resistance for induced current.The reference current correcting circuit couples proofreaies and correct resistance and reference current generator, makes reference current generator adjustment control voltage according to relatively controlling voltage and proofreading and correct ohmically voltage.
Based on above-mentioned, the present invention combines the weld pad that digital core circuitry and analog core circuit carry out the signal transmission inside and outside the System on Chip/SoC, effectively reduces the weld pad sum of System on Chip/SoC.In an embodiment of the present invention, then also propose a kind of correcting circuit of analog core circuit, come by shared input and output weld pad the reference current of analog core circuit is proofreaied and correct the accuracy of analog core circuit in the elevator system chip.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate accompanying drawing to be described in detail below.
Description of drawings
Fig. 1 is the pin configuration figure of existing System on Chip/SoC 100;
Fig. 2 is the schematic diagram of the input/output interface device 200 of one embodiment of the invention;
Fig. 3 is another execution mode of the input/output interface device 200 of the embodiment of the invention;
Fig. 4 is an execution mode of logical operation circuit 220;
Fig. 5 is the partial circuit figure of an again execution mode of the input/output interface device 200 of the embodiment of the invention.
Description of reference numerals:
100: System on Chip/SoC;
110: digital core circuitry;
120: the analog core circuit;
111: the digital IO weld pad;
112: analog input output weld pad;
200: input/output interface device;
210: the digital IO control circuit;
220: logical operation circuit;
230: the analog core circuit;
240: voltage offset circuits;
270: the input and output weld pad;
290: the logic core circuit;
231: reference current generator;
232: current supply;
233: the reference current correcting circuit;
2321～232P: analog core electronic circuit;
2331: correcting logic circuit;
OEN: digital output enable signal;
SW1: switch;
SIN, SOU, AIO: signal transmission;
AEN: simulation output enable signal;
CTR: control signal;
VDD, VDDIO: supply voltage;
AND: with door;
INV: not gate;
OEN_d: numeral output control signal;
REXT: proofread and correct resistance;
VREF: reference voltage;
V1: control voltage;
V2: voltage;
I1: reference current;
2311: the band gap voltage generator;
OPAMP: operational amplifier;
M1～M4: transistor;
RT: reference resistance;
I3～In: for induced current;
IC: correcting current;
VF: fixed voltage;
CR: resistance is adjusted signal;
CMP: comparator.
Embodiment
Please refer to Fig. 2, Fig. 2 is the schematic diagram of the input/output interface device 200 of one embodiment of the invention.Input/output interface device 200 comprises digital IO control circuit 210, logical operation circuit 220, analog core circuit 230, voltage offset circuits 240 and interrupteur SW 1.The input and output weld pad 270 of digital IO control circuit 210 coupling chips and logic core circuit 290, digital IO control circuit 210 receives digital output enable signal OEN to transmit or to receive signal transmission by input and output weld pad 270.More carefully illustrate, when digital output enable signal OEN is enabled state (for example being logic level " 0 "), the signal transmission SOU that digital IO control circuit 210 can spread out of logic core circuit 290 is to input and output weld pad 270, and by this signal transmission SOU spread out of to chip exterior.Certainly, under this state, digital IO control circuit 210 also can reach chip exterior the signal transmission SIN of input and output weld pad 270, turns to reach logic core circuit 290.
Certainly, above-mentioned digital output enable signal OEN is that enabled state is that logic level " 0 " is an example only, and the designer can set up the logic level of the digital output enable signal OEN of enabled state on their own.
In the present embodiment, numeral output enable signal OEN is provided by logical operation circuit 220, and, when chip will be sent out the signal transmission SOU that logic core circuit 290 produces by input and output weld pad 270, logical operation circuit 220 can produce the digital output enable signal OEN of enabled state.Relative, when signal transmission AIO that chip will produce by input and output weld pad 270 transportation simulator core circuits 230, logical operation circuit 220 can produce the digital output enable signal OEN of disabled state.That is to say that when chip for example will carry out the test of exploitation, chip of firmware (firmware) and/or chip misarrangement, logical operation circuit 220 can produce the digital output enable signal OEN of state.
Voltage offset circuits 240 is coupled to logical operation circuit 220.The voltage that voltage offset circuits 240 received and shifted analog input output enable signal AEN produces control signal CTR.It should be noted that in the present embodiment, analog core circuit 230 and digital core circuitry 220 the supply voltage VDDIO and the VDD that receive respectively be not identical, wherein, the magnitude of voltage of supply voltage VDDIO for example is greater than supply voltage VDD.Voltage offset circuits 240 then is to carry out the action of variation for the simulation output enable signal AEN that is produced by logical operation circuit 220, be created in the control signal CTR of transition between supply voltage VDDIO and earthed voltage, at this, earthed voltage for example is 0 volt.
At this, simulation output enable signal AEN can be provided by logical operation circuit 220 equally.And when chip will carry out the transmission action of signal transmission AIO by input and output weld pad 270 and analog core circuit 230, logical operation circuit 220 can produce the simulation output enable signal AEN of enabled state.Relative, when signal transmission AIO that chip does not produce by input and output weld pad 270 transportation simulator core circuits 230, logical operation circuit 220 can produce the simulation output enable signal AEN of disabled state.That is to say that when will carrying out the monitoring of the analog signal in the chip, or during the analog signal transmission when carrying out the chip misarrangement, logical operation circuit 220 can produce the simulation output enable signal AEN of enabled state.
Interrupteur SW 1 is serially connected in coupling between the path of input and output weld pad 270 and analog core circuit 230.Interrupteur SW 1 is controlled by control signal CTR with conducting or disconnection.In the present embodiment, when simulation output enable signal AEN was set to enabled state, the corresponding control signal CTR that produces can make interrupteur SW 1 be switched on, and conducting input and output weld pad 270 and analog core circuit 230 couple the path.Thus, produced by analog core circuit 230 or can effectively be transmitted at input and output weld pad 270 and 230 in analog core circuit by the signal transmission AIO that input and output weld pad 270 reaches by the outside.It should be noted that at the same time logical operation circuit 220 can produce the digital output enable signal OEN of disabled state, and logic core circuit 290 transmission signal transmission SOU are cut off to the path of input and output weld pad 270.
Subsidiary one carries, because the voltage amplitude maximum of signal transmission AIO is can be between between supply voltage VDDIO and earthed voltage, therefore, for making signal transmission AIO be unlikely to distortion through interrupteur SW 1 time, the control signal CTR that interrupteur SW 1 receives can be the digital signal that is controlled in transition between supply voltage VDDIO and earthed voltage.
Below please refer to Fig. 3, Fig. 3 is another execution mode of the input/output interface device 200 of the embodiment of the invention.In the present embodiment, logical operation circuit 220 can be by the interior logic core circuit 290 that is contained in.And about the action details of present embodiment, then the embodiment with Fig. 2 is identical, below seldom gives unnecessary details for this reason.
Please refer to Fig. 4, Fig. 4 is an execution mode of logical operation circuit 220.Logical operation circuit 220 comprises and door AND and not gate INV.Receive numeral output control signal OEN_d with the first input end of door AND, produce digital output enable signal OEN with the output of door AND.The output of not gate INV is coupled to the second input with door AND, and the input of not gate INV receives analog input output enable signal AEN.Analog input output enable signal AEN is then provided by logic core circuit 290.
Please refer to Fig. 5, Fig. 5 is the partial circuit figure of an again execution mode of the input/output interface device 200 of the embodiment of the invention.In the present embodiment, input/output interface device 200 can be used to provide the corrective action of the reference current that the analog core circuit 230 that carries out chip internal produces.In the present embodiment, input/output interface device 200 also comprises proofreaies and correct resistance R EXT, wherein, proofreaies and correct resistance R EXT and is serially connected between input and output weld pad 270 and reference voltage VREF.And analog core circuit 230 comprises reference current generator 231, current supply 232 and reference current correcting circuit 233.Reference current generator 231 is adjusted the reference current I1 that reference current generator 231 produces according to control voltage V1.
In the present embodiment, reference current generator 231 comprises band gap voltage generator 2311, operational amplifier OPAMP, transistor M1 and reference resistance RT.Band gap voltage generator 2311 produces fixed voltage VF, and provides a input to operational amplifier OPAMP with fixed voltage VF.Another input of operational amplifier OPAMP is coupled to the second end of transistor M1, and the first end of transistor M1 receives supply voltage VDD, and the control end of transistor M1 is connected to the output of operational amplifier OPAMP.Reference resistance RT is serially connected between the second end and reference voltage VREF of transistor M1, and reference voltage VREF can be earthed voltage.Wherein, the reference current I1 that reference current generator 231 produces flows to its second end by the first end of transistor M1, and reference current I1 and the reference resistance RT that flows through are to produce control voltage V1.And reference resistance RT is a variable resistor, and the resistance value of reference resistance RT can relatively be controlled voltage V1 and proofreaies and correct the comparative result that the voltage on the resistance R T produces and adjust according to reference current correcting circuit 233 utilization.
Wherein, supply electric current I 3～In is used to provide respectively to the analog core electronic circuit 2321～232P in the analog core circuit 230.
In addition, the first end of transistor M4 is coupled to supply voltage VDD, and its control end couples mutually with the control end of transistor M1～M3, and the second end of transistor M4 then provides correcting current IC.When carrying out the corrective action of reference current I1, interrupteur SW 1 correspondence is switched on, therefore, the second end of transistor M4 can be connected to by interrupteur SW 1 and proofread and correct resistance R EXT, and makes correcting current IC flow through correction resistance R EXT so that the second end of transistor M4 produces voltage V2.
Reference current correcting circuit 233 comprises comparator C MP and correcting logic circuit 2331.The first input end of comparator C MP couples the second end of transistor M4, and the second input of comparator C MP couples the second input of operational amplifier OPAMP.Correcting logic circuit 2331 couples the output of comparator C MP, and has a resistance according to the comparative result that the output of comparator C MP produces and to adjust signal CR.Wherein, resistance is adjusted signal CR and is provided to reference resistance RT, to adjust the resistance value of reference resistance RT.
At this, about adjusting the resistance value adjustment aspect that signal CR carries out reference resistance RT by resistance, wherein, reference resistance RT can be connected in series by a plurality of sub-resistance, and each sub-resistance all disposes one with it and the switch that connects.Adjust conducting or the off-state that signal CR controls each switch by resistance, just can effectively adjust the resistance value of reference resistance RT.The adjustment mode of the resistance value of similar above-mentioned explanation should be technology well known to those of ordinary skill in the art, pardons few numerous stating at this.
In sum, the present invention is by the conducting of switch or the action of disconnection, the input and output weld pad that input/output interface device is connected can under different chip use states, make analog core circuit or digital core circuitry in the chip carry out the transmission action of signal transmission by the input and output weld pad that shares.Thus, the weld pad quantity on the chip can effectively be reduced, and except the quantity that can reduce packaging pin, also can reduce the area of chip, significantly the cost competitiveness of improving product.
It should be noted that at last: above each embodiment is not intended to limit only in order to technical scheme of the present invention to be described; Although with reference to aforementioned each embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps some or all of technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the scope of various embodiments of the present invention technical scheme.
Claims (13)
1. input/output interface device, in be loaded on a chip, it is characterized in that, comprising:
One digital IO control circuit couples an input and output weld pad of this chip, receives a digital output enable signal to transmit or to receive a signal transmission by this input and output weld pad;
One logical operation circuit couples this digital IO control circuit, in order to produce this numeral output enable signal and an analog input output enable signal;
One analog core circuit;
One switch is serially connected between this input and output weld pad and this analog core circuit, and this switch reception and foundation one control signal are with conducting or disconnection; And
One voltage offset circuits couples this logical operation circuit, and the voltage that receives and shift this analog input output enable signal produces this control signal.
2. input/output interface device according to claim 1 is characterized in that, the single spin-echo of this analog input output enable signal and this numeral output enable signal.
3. input/output interface device according to claim 1 is characterized in that, this voltage offset circuits is heightened the voltage of this analog input output enable signal to produce this control signal.
4. input/output interface device according to claim 1 is characterized in that, when this switch disconnected, this digital IO control circuit transmitted this signal transmission by this input and output weld pad.
5. input/output interface device according to claim 1 is characterized in that, during this switch conduction, this analog core circuit transmits or receive this signal transmission by this switch.
6. input/output interface device according to claim 1, it is characterized in that, this digital IO control circuit also couples a digital core circuitry and this logical operation circuit, and this digital core circuitry transmits or receive this signal transmission by this digital IO control circuit.
7. input/output interface device according to claim 6 is characterized in that, is contained in this logical operation circuit in this digital core circuitry.
8. input/output interface device according to claim 1 is characterized in that, this logical operation circuit comprises:
One with door, its first input end receives a numeral output control signal, its output produces this numeral output enable signal; And
One not gate, its output be coupled to this with the door the second input, the input of this not gate receives this analog input output enable signal.
9. input/output interface device according to claim 1 is characterized in that, this input/output interface device also comprises:
One proofreaies and correct resistance, is serially connected between this input and output weld pad and a reference voltage, and wherein this analog core circuit then comprises:
One reference current generator is adjusted the reference current that this reference current generator produces according to a control voltage;
One current supply, couple this reference current generator, and produce at least one for induced current and a correcting current according to this reference current, wherein this confession induced current is in order to providing at least one analog core electronic circuit to this analog core circuit, and provides this correcting current by this correction resistance; And
One reference current correcting circuit couples this correction resistance and this reference current generator, according to relatively this control voltage and the ohmically voltage of this correction make this reference current generator adjust this control voltage.
10. input/output interface device according to claim 9 is characterized in that, this reference current generator comprises:
One band gap voltage generator produces a fixed voltage;
One operational amplifier, its first input end receives this fixed voltage;
One the first transistor has first end, the second end and control end, and its first end receives a supply voltage, and its second end is coupled to the second input of this operational amplifier, and its control end couples the output of this operational amplifier;
One reference resistance is serially connected between second end and this reference voltage of this first transistor,
Wherein, this reference current flows to its second end by the first end of this first transistor, and this reference current and this reference resistance of flowing through are to produce this control voltage.
11. input/output interface device according to claim 10, it is characterized in that, this reference resistance is variable resistor, and the resistance value of this reference resistance according to this reference current correcting circuit relatively the comparative result of this control voltage and the ohmically voltage of this correction adjust.
12. input/output interface device according to claim 10 is characterized in that, this current supply comprises:
At least one transistor seconds has first end, the second end and control end, and its first end couples this supply voltage, and its second end produces this confession induced current, and its control end couples the control end of this first transistor; And
One the 3rd transistor has first end, the second end and control end, and its first end couples this supply voltage, and its second end produces this correcting current, and its control end couples the control end of this first transistor.
13. input/output interface device according to claim 12 is characterized in that, this reference current correcting circuit comprises:
One comparator, its first input end couple the 3rd transistorized the second end, and its second input couples the second input of this operational amplifier; And
One correcting logic circuit couples the output of this comparator, and produces a resistance according to the comparative result that the output of this comparator produces and adjust signal,
Wherein, this resistance is adjusted signal and is provided to this reference resistance, to adjust the resistance value of this reference resistance.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101114938A TWI461959B (en) | 2012-04-26 | 2012-04-26 | Output and input interface apparatus |
| TW101114938 | 2012-04-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103378844A true CN103378844A (en) | 2013-10-30 |
| CN103378844B CN103378844B (en) | 2016-03-30 |
Family
ID=49463467
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210191571.9A Active CN103378844B (en) | 2012-04-26 | 2012-06-12 | Input/output interface device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103378844B (en) |
| TW (1) | TWI461959B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105573393A (en) * | 2014-11-11 | 2016-05-11 | 扬智科技股份有限公司 | Integrated circuit, current correction method thereof, and electronic device |
| CN113311212A (en) * | 2020-02-26 | 2021-08-27 | 合泰半导体(中国)有限公司 | Voltage monitoring device |
| CN115257184A (en) * | 2019-02-06 | 2022-11-01 | 惠普发展公司，有限责任合伙企业 | Multiple circuits coupled to the interface |
| US12030312B2 (en) | 2023-08-11 | 2024-07-09 | Hewlett-Packard Development Company, L.P. | Print component with memory circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040141392A1 (en) * | 2003-01-13 | 2004-07-22 | Lee Yun-Woo | Input/output buffer having analog and digital input modes |
| CN101102102A (en) * | 2006-07-07 | 2008-01-09 | 恩益禧电子股份有限公司 | Input interface circuit adapted to both of analog and digital signals |
| CN201243355Y (en) * | 2008-08-15 | 2009-05-20 | 青岛海信电器股份有限公司 | Interface processing device and video device containing the same |
| CN201489512U (en) * | 2009-08-21 | 2010-05-26 | 西安迅腾科技有限责任公司 | Analog and switching value multiplex interface for data acquisition system |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19743002A1 (en) * | 1997-09-29 | 1999-04-08 | Siemens Ag | Switching arrangement for simultaneous processing for digital and analog signal |
| US7196644B1 (en) * | 2004-07-01 | 2007-03-27 | Seagate Technology Llc | Decoupling of analog input and digital output |
| US7242559B2 (en) * | 2004-07-22 | 2007-07-10 | Taiwan Semiconductor Co., Ltd. | High voltage tolerant I/O circuit |
| SG127783A1 (en) * | 2005-05-12 | 2006-12-29 | Taiwan Semiconductor Mfg | Thin-oxide devices for high voltage i/o drivers |
| TWI275246B (en) * | 2005-09-26 | 2007-03-01 | Univ Tsinghua | Transmitting circuit applied to input output interface |
-
2012
- 2012-04-26 TW TW101114938A patent/TWI461959B/en active
- 2012-06-12 CN CN201210191571.9A patent/CN103378844B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040141392A1 (en) * | 2003-01-13 | 2004-07-22 | Lee Yun-Woo | Input/output buffer having analog and digital input modes |
| CN101102102A (en) * | 2006-07-07 | 2008-01-09 | 恩益禧电子股份有限公司 | Input interface circuit adapted to both of analog and digital signals |
| CN201243355Y (en) * | 2008-08-15 | 2009-05-20 | 青岛海信电器股份有限公司 | Interface processing device and video device containing the same |
| CN201489512U (en) * | 2009-08-21 | 2010-05-26 | 西安迅腾科技有限责任公司 | Analog and switching value multiplex interface for data acquisition system |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105573393A (en) * | 2014-11-11 | 2016-05-11 | 扬智科技股份有限公司 | Integrated circuit, current correction method thereof, and electronic device |
| CN115257184A (en) * | 2019-02-06 | 2022-11-01 | 惠普发展公司，有限责任合伙企业 | Multiple circuits coupled to the interface |
| CN113311212A (en) * | 2020-02-26 | 2021-08-27 | 合泰半导体(中国)有限公司 | Voltage monitoring device |
| US12030312B2 (en) | 2023-08-11 | 2024-07-09 | Hewlett-Packard Development Company, L.P. | Print component with memory circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103378844B (en) | 2016-03-30 |
| TW201344499A (en) | 2013-11-01 |
| TWI461959B (en) | 2014-11-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9118317B2 (en) | Transmitter swing control circuit and method | |
| JP6140860B2 (en) | Single-end configurable multimode driver | |
| US8610458B2 (en) | Impedance control circuit and semiconductor device including the same | |
| KR100660907B1 (en) | Internal reference voltage generator for reducing standby current and semiconductor memory device including the same | |
| US7420387B2 (en) | Semiconductor device capable of controlling OCD and ODT circuits and control method used by the semiconductor device | |
| US8120381B2 (en) | Impedance adjusting device | |
| WO2013033622A1 (en) | On -chip regulator with variable load compensation | |
| US8487650B2 (en) | Methods and circuits for calibrating multi-modal termination schemes | |
| CN1835485B (en) | Low voltage differential signaling transceiver | |
| CN107040254B (en) | Switching control using switched capacitor circuits | |
| US7974304B2 (en) | Out of band signaling enhancement for high speed serial driver | |
| US7659747B2 (en) | Transmission device | |
| Kim et al. | A 5.2-Gb/s low-swing voltage-mode transmitter with an AC-/DC-coupled equalizer and a voltage offset generator | |
| WO2021113113A1 (en) | Calibrating resistance for data drivers | |
| US8144726B2 (en) | Structure for out of band signaling enhancement for high speed serial driver | |
| CN103378844A (en) | Input/output interface device | |
| US11152944B2 (en) | Termination calibration scheme using a current mirror | |
| US7525357B2 (en) | Circuit and method for adjusting a voltage drop | |
| US20150280712A1 (en) | Data output circuit of semiconductor apparatus | |
| US10326437B2 (en) | Circuit device and electronic apparatus | |
| US9280162B2 (en) | Method and apparatus for minimizing within-die variations in performance parameters of a processor | |
| CN112702050B (en) | Integrated circuit chip and electronic device | |
| Song et al. | 26.5 An 8-to-16Gb/s 0.65-to-1.05 pJ/b 2-tap impedance-modulated voltage-mode transmitter with fast power-state transitioning in 65nm CMOS | |
| JP2004241930A (en) | Output circuit | |
| Tang et al. | A 28 Gb/s 2-tap FFE source-series-terminated transmitter in 22 nm CMOS FDSOI |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20151023 Address after: Arizona, USA Applicant after: MICROCHIP TECHNOLOGY Inc. Address before: Cayman Islands Applicant before: British Cayman Islands Business Miley electronic Limited by Share Ltd. Effective date of registration: 20151023 Address after: Cayman Islands Applicant after: British Cayman Islands Business Miley electronic Limited by Share Ltd. Address before: Science Park, Hsinchu, Taiwan, China Road 8, building 4 Applicant before: INTEGRATED SYSTEM SOLUTION CORPORATION |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |