CN103367315A - Wafer Level Package Construction - Google Patents

Abstract

The invention discloses a wafer level packaging structure, which comprises a semiconductor component, a first dielectric layer, a redistribution circuit layer, a second dielectric layer and at least one metal lug, wherein the redistribution circuit layer is arranged on the first dielectric layer and comprises a wire part, a fan-shaped part and a gasket part, the metal lug comprises a contact surface and an end edge, the contact surface is connected with the gasket part, the end edge is positioned on one side of the contact surface and faces the fan-shaped part, and a buffer distance for dispersing current is arranged between the end edge and the fan-shaped part. The buffer distance is formed between the end edge and the fan-shaped part, so that the range of the current passing through the end edge can be enlarged, the current moving from the metal lug to the fan-shaped part is further dispersed, the influence of electronic migration on the metal lug is reduced, and the metal lug is prevented from cracking or breaking.

Description

Wafer Level Package Construction

technical field

The present invention relates to a wafer-level packaging structure, in particular to a wafer-level packaging structure capable of improving the conductive stability of metal bumps.

Background technique

In semiconductor packaging technology, such as flip chip (Flip Chip), it is mainly to form metal bumps (Solder Bump) on the chip, such as tin bumps, and directly electrically connect with the substrate (Substrate) through the tin bumps , compared with the wire bonding chip (Wire Bonding Chip), the circuit path of the semiconductor packaging technology of the flip chip is shorter, has better electrical quality, and does not take up space, which can make the overall structure lighter, thinner and shorter .

In addition, the active surface of a semiconductor component, such as a chip in a wafer (wafer) or a wafer level package (WLP), is further connected to the metal bump through a redistribution layer (RDL). block to form electrical conduction, the active surface of the semiconductor component may be covered with a passivation layer and a redistribution layer, the redistribution layer is composed of several dielectric layers and at least one redistribution circuit layer, the redistribution The circuit layer is disposed in the dielectric layers and electrically connected to the metal pads on the active surface of the semiconductor component, wherein the metal bump is disposed on the dielectric layer and partially connected to the redistribution circuit layer.

When the semiconductor component is energized, a part of the current will move from the wire part of the redistribution circuit layer to the metal bump, and then gather in the circuit of the redistribution circuit layer. However, due to the redistribution circuit The width of the layer gradually expands from the wire portion (less than 20 microns in width) to the pad portion (about 250 to 300 microns in width) into a drop shape, but the wire portion and the pad portion are used to contact the redistribution pad of the metal bump The distance between the regions is too short, causing the current to flow to the redistribution pad region before it can be dispersed from the wire part into the pad part. As a result, the current density of the portion of the edge of the metal bump connected to the redistribution pad region is too high, so that the portion of the edge of the metal bump connected to the redistribution pad region is more susceptible to electromigration. , causing the metal atoms at the edge of the metal bump to dissipate and lose along with the migration of electrons, thereby causing cracks or disconnections.

Therefore, it is necessary to provide a wafer level packaging structure to solve the problems existing in the prior art.

Contents of the invention

In view of this, the present invention provides a wafer level packaging structure to solve the problem of cracks or disconnection between the metal bumps in the redistribution layer and the redistribution circuit layer due to the migration of metal ions caused by excessive current concentration.

The main purpose of the present invention is to provide a WLP structure, which can reduce the chance of cracks or disconnection between the metal bump and the redistribution circuit layer during conduction.

A secondary object of the present invention is to provide a wafer level packaging structure, which can improve the stability of the conduction between the metal bump and the redistribution circuit layer.

In order to achieve the aforementioned object of the present invention, an embodiment of the present invention provides a wafer-level packaging structure, wherein the wafer-level packaging structure includes a semiconductor component, a protective layer, a first dielectric layer, and a redistribution circuit layer , a second dielectric layer and at least one metal bump. The semiconductor component has an active surface, the active surface is provided with at least one conductive pad, the protective layer covers the active surface and the conductive pad, and partially exposes the conductive pad, the The first dielectric layer covers the protective layer and partially exposes the conductive pads. The redistribution circuit layer is disposed on the first dielectric layer and includes a wire part, a fan-shaped part and a A gasket part, one end of the wire part is electrically connected to the conductive pad, the fan-shaped part is formed by extending from the other end of the wire part, the gasket part is connected to the fan-shaped part, and the second intermediary The electrical layer covers the first dielectric layer and the redistribution circuit layer, and partially exposes the pad portion to define a redistribution pad area, and the metal bump is disposed on the second dielectric layer and the redistribution circuit layer. On the redistribution pad area, the metal bump includes a contact surface and an end edge, the contact surface is connected to the redistribution pad area, and the end edge is located on one side of the contact surface and faces the There is a buffer distance between the end edge and the fan-shaped part for dispersing current.

Furthermore, another embodiment of the present invention provides another WLP structure, wherein the WLP structure includes a semiconductor device and a redistribution layer. The semiconductor component has an active surface, the redistribution layer covers the active surface, and has a redistribution circuit layer, and the redistribution circuit layer includes a wire part, a sector part and a pad part , the fan-shaped portion is extended from the wire portion, the pad portion is connected to the fan-shaped portion, wherein a redistribution pad area is defined on the pad portion, and the redistribution pad area is close to the There is a buffer distance between one side of the sector and the sector for dispersing current.

As mentioned above, due to the sufficient buffer distance formed between the end edge and the fan-shaped part, the range of current passing through the end edge can be enlarged, and the current moving from the wire part to the metal bump through the fan-shaped part can be dispersed, reducing the The extent to which the metal bumps are affected by the loss of metal atoms due to electron migration is to avoid cracks or disconnections between the metal bumps and the redistribution circuit layer.

Description of drawings

FIG. 1 is a cross-sectional view of a wafer-level packaging structure according to an embodiment of the present invention.

2 and 3 are schematic diagrams of the wafer-level packaging structure in FIG. 1 and diagrams of usage states.

4 and 5 are schematic diagrams and usage status diagrams of wafer-level packaging structures according to another embodiment of the present invention.

Detailed ways

The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments in which the present invention can be practiced. Furthermore, the directional terms mentioned in the present invention are, for example, up, down, top, bottom, front, back, left, right, inside, outside, side, surrounding, central, horizontal, transverse, vertical, longitudinal, axial, The radial direction, the uppermost layer or the lowermost layer, etc. are only directions referring to the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention.

Please refer to FIGS. 1 and 2, a wafer-level packaging structure 100 according to an embodiment of the present invention mainly includes a semiconductor component 2, a protective layer 3, a first dielectric layer 4, a redistribution circuit layer 5, and a second A dielectric layer 6 and at least one metal bump 7, wherein the semiconductor component 2 refers to a semiconductor chip (Chip) in the wafer-level packaging structure 100 or a semiconductor wafer (wafer) that has not been cut at the front end of the manufacturing process, The present invention will describe in detail the detailed structure, assembly relationship and operation principle of the above-mentioned components one by one below.

1, the semiconductor component 2 is to form an active surface 21 on a semiconductor substrate (such as a silicon substrate), and the active surface 21 is provided with at least one conductive pad 22, such as an aluminum pad (Al Pad), the protective layer 3 is, for example, silicon dioxide, which covers the active surface 21 and the conductive pad 22, and the protective layer 3 is formed with an opening (not marked) at the position corresponding to the conductive pad 22 , so that the conductive pad 22 can be partially exposed.

The first dielectric layer 4 is covered on the protective layer 3, for example, an organic polymer insulating material such as benzocyclobutene (BCB) or polyimide (Polyimide, PI) can be used, and the first dielectric layer Openings (not shown) are also formed on the dielectric layer 4 corresponding to the conductive pads 22 to partially expose the conductive pads 22 . The thickness of the first dielectric layer 4 may be greater than or equal to the thickness of the protective layer 3 .

1 and 2, the redistribution circuit layer 5 is disposed on the first dielectric layer 4, such as copper or titanium/copper (Ti/Cu) alloy, etc., and includes a lead portion 51, a The fan-shaped part 52 and a pad part 53, the wire part 51 is linear, one end of which is electrically connected to the conductive pad 22; Extended from the other end of the lead portion 51 ; the washer portion 53 is substantially U-shaped and connected to the fan-shaped portion 52 .

The second dielectric layer 6 is, for example, selected from an organic polymer insulating material such as benzocyclobutene or polyimide, which covers the first dielectric layer 4 and the redistribution circuit layer 5, and the second dielectric layer 6 An opening (not shown) is formed in the second dielectric layer 6 corresponding to the position of the pad portion 53 to partially expose a central circular area of the pad portion 53 to define a redistribution pad region 53 ′.

The first dielectric layer 4 , the redistribution circuit layer 5 and the second dielectric layer 6 together form a redistribution layer (RDL).

The metal bump 7, such as a tin bump, a gold bump or a copper pillar bump, is disposed on the second dielectric layer 6 and the redistribution pad region 53', and the metal bump 7 includes a contact surface 71 and an end edge 72, the contact surface 71 is connected to the redistribution pad region 53', the contact surface 71 and the redistribution pad region 53' are both circular, and the end The edge 72 is arc-shaped and is located on one side of the contact surface 71 and faces the fan-shaped portion 52. There is a buffer distance I between the end edge 72 and the fan-shaped portion 52 to disperse the current, that is, the heavy There is a buffer distance I between the side of the distribution pad area 53 ′ close to the fan-shaped portion 52 (the left side in FIG. 2 ) and the fan-shaped portion 52 for spreading current. The length of the buffer distance I is at least 1/8 of a maximum width of the contact surface 71 , such as 1/7, 1/6, 1/5, 1/4 or 1/3.

Moreover, the width of the redistribution pad region 53' (contact surface 71) is 240 to 260 microns; the width of the pad portion 53 (up and down in FIG. 2 ) is 280 to 300 microns; the wire portion 51 The width is 18 microns or less; the widths of both ends of the fan-shaped portion 52 (left and right ends in FIG. 2 ) are respectively equal to the width of the wire portion 51 and the width of the pad portion 53.

Please refer to FIG. 3 , according to the above-mentioned structure, since a buffer distance I (see FIG. 2 ) is formed between the end edge 72 and the fan-shaped portion 52, the range of the current passing through the end edge 72 can be enlarged, and then the current can be dispersed. The electric current (see the arrow in FIG. 3 ) that the wire part 51 moves to the metal bump 7 through the fan-shaped part 52 prevents the current from being concentrated and passes through the edge 72 in a dot shape, so as to reduce the impact on the metal bump 7. Electron migration causes metal atom loss to avoid cracks or disconnection between the metal bump 7 and the redistribution pad region 53 ′ of the redistribution circuit layer 5 .

Please refer to FIG. 4 , the wafer-level packaging structure of another embodiment of the present invention is similar to that of the first embodiment of the present invention, and generally uses the same component names and figure numbers, but the difference of this embodiment is that: the terminal The edge 72 is linear, and the linear length of the end edge 72 is at least 1/12 of a maximum width of the contact surface 71, such as 1/10, 1/8, 1/6, 1/5, 1/ 4, 1/3 or 1/2 etc.

Please refer to FIG. 5 , according to the above-mentioned structure, since a buffer distance I (see FIG. 4 ) is also formed between the end edge 72 and the fan-shaped portion 52 of the present embodiment, the wire portion 51 can also be dispersed through the The current that moves the metal bump 7 (see the arrow in FIG. 5 ), so it can also effectively avoid cracks or disconnections between the metal bump 7 and the redistribution pad region 53 ′ of the redistribution circuit layer 5 situation.

The present invention has been described by the above-mentioned related embodiments, however, the above-mentioned embodiments are only examples for implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the claims are included in the scope of the present invention.

Claims (10)

1. A wafer-level packaging structure, characterized in that: the wafer-level packaging structure comprises: A semiconductor component has an active surface, the active surface is provided with at least one conductive pad; a protective layer covering the active surface and the conductive pads, and partially exposing the conductive pads; a first dielectric layer covering the protective layer and partially exposing the conductive pad; A redistribution circuit layer is disposed on the first dielectric layer and includes: a lead part, one end of which is electrically connected to the conductive pad; a fan-shaped part extending from the other end of the lead part; and a spacer portion connected to the sector; a second dielectric layer covering the first dielectric layer and the redistribution circuit layer and partially exposing the pad portion to define a redistribution pad region; and At least one metal bump is disposed on the second dielectric layer and the redistribution pad area, and the metal bump includes: a contact surface connected to the redistribution pad area; and an end edge located on the redistribution pad area. One side of the contact surface faces the fan-shaped portion, and there is a buffer distance between the end edge and the fan-shaped portion to disperse current. 2. The wafer level packaging structure according to claim 1, wherein the spacer portion is U-shaped. 3. The wafer level packaging structure according to claim 1, wherein the edge is arc-shaped. 4. The WLP structure as claimed in claim 2, wherein the buffer distance is at least 1/8 of a maximum width of the contact surface. 5. The wafer level packaging structure according to claim 1, wherein the edge is straight. 6 . The WLP structure as claimed in claim 5 , wherein the linear length of the end edge is at least 1/12 of a maximum width of the contact surface. 7. The wafer level packaging structure as claimed in claim 1, wherein the width of the wire portion is 18 microns or less. 8. A wafer-level packaging structure, characterized in that: the wafer-level packaging structure comprises: a semiconductor component having an active surface; and A redistribution layer covers the active surface and has a redistribution circuit layer, and the redistribution circuit layer includes: a wire section; a fan-shaped portion extending from the lead portion; and A pad part, connected to the fan-shaped part, wherein a redistribution pad area is defined on the pad part, and a side of the redistribution pad area close to the fan-shaped part and the fan-shaped part has a The buffer distance used to spread the current. 9. The wafer level packaging structure according to claim 8, wherein the edge is arc-shaped. 10. The wafer level packaging structure according to claim 8, wherein the edge is straight.

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