CN103367315A - Wafer level packaging structure - Google Patents
Wafer level packaging structure Download PDFInfo
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- CN103367315A CN103367315A CN201310287219XA CN201310287219A CN103367315A CN 103367315 A CN103367315 A CN 103367315A CN 201310287219X A CN201310287219X A CN 201310287219XA CN 201310287219 A CN201310287219 A CN 201310287219A CN 103367315 A CN103367315 A CN 103367315A
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- wafer
- packaging structure
- scallop
- grade packaging
- ora terminalis
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a wafer level packaging structure, which comprises a semiconductor component, a first dielectric layer, a redistribution circuit layer, a second dielectric layer and at least one metal bump, wherein the redistribution circuit layer is arranged on the first dielectric layer, and comprises a wire part, a fan-shaped part and a gasket part; the metal bump comprises a contact surface and an end edge; the contact surface is connected with the gasket part; the end edge is positioned on one side of the contact surface, and faces the fan-shaped part; and a buffer distance for diffusing current is formed between the end edge and the fan-shaped part. The buffer distance is formed between the end edge and the fan-shaped part, so that the range of the end edge, where current passes, can be widened, the current, which moves towards the fan-shaped part, of the metal bump is diffused, and the influence of electron migration on the metal bump is reduced to avoid the condition that the metal bump is cracked or broken.
Description
Technical field
The invention relates to a kind of wafer-grade packaging structure, particularly relevant for a kind of wafer-grade packaging structure that improves the conductive stability of metal coupling.
Background technology
In semiconductor packaging, flip-chip (Flip Chip) for example, mainly be to form metal coupling (Solder Bump) at chip, such as tin projection, and direct and substrate (Substrate) electric connection by described tin projection, compared to routing cake core (Wire Bonding Chip), the line route of the semiconductor packaging of described flip-chip is shorter, have better electrical quality, and do not take up room, can make overall structure more compact.
In addition; semiconductor subassembly; such as wafer (wafer) or wafer-grade packaging structure (wafer lever package; WLP) chip in etc.; its active surface be further by one reroute the layer (redistribution a layer; RDL) conduct with described metal coupling formation; the active surface of described semiconductor subassembly can be coated with protective layer (Passivation) and a layer that reroutes; the described layer that reroutes is made of several dielectric layers and at least one heavy distributed circuit layer; described heavy distributed circuit layer is arranged in described several dielectric layers; and the metallic pad on the active surface of electric connection semiconductor subassembly, wherein said metal coupling is arranged on the dielectric layer and part connects described heavy distributed circuit layer.
When described semiconductor subassembly energising, a part of electric current can be moved toward described metal coupling by the wire portion of heavy distributed circuit layer, and then come together in the circuit of described heavy distributed circuit layer, but, because the width of described heavy distributed circuit layer is toward pad section (about 250 to 300 microns of width) direction flaring great achievement drops by wire portion (width is less than 20 microns), but wire portion and pad section are too short in order to the distance that heavily distributes between the pad zone of contacting metal projection, cause electric current to enter pad section by wire portion and also do not have enough time to disperse just to concentrate toward the pad zone diffluence that heavily distributes.The result, it is excessive that described metal coupling connects the current density of part ora terminalis of described heavy distribution pad zone, so that described metal coupling connects the impact that the part ora terminalis of described heavy distribution pad zone is easier to be subject to electron transfer, cause described metal coupling in metallic atom loss loss along with electron transfer at ora terminalis place, and then the situation that produces be full of cracks or disconnect.
So, be necessary to provide a kind of wafer-grade packaging structure, to solve the existing problem of prior art.
Summary of the invention
In view of this, the invention provides a kind of wafer-grade packaging structure, the problem that reroutes and cause metal ion transport to chap or disconnect because of the electric current concentrations between the metal coupling and heavy distributed circuit layer in the layer with solution.
Main purpose of the present invention is to provide a kind of wafer-grade packaging structure, and it can reduce the chance that produces be full of cracks or disconnect between metal coupling and the heavy distributed circuit layer when conduction.
Secondary objective of the present invention is to provide a kind of wafer-grade packaging structure, and it can improve the conductive stability between metal coupling and the heavy distributed circuit layer.
For reaching aforementioned purpose of the present invention; one embodiment of the invention provides a kind of wafer-grade packaging structure, and wherein said wafer-grade packaging structure comprises semiconductor assembly, a protective layer, one first dielectric layer, a heavy distributed circuit layer, one second dielectric layer and at least one metal coupling.Described semiconductor subassembly has an active surface; described active surface is provided with at least one conductive connection pads; described protective layer covers on described active surface and the conductive connection pads; and the exposed described conductive connection pads of part; described the first dielectric layer covers on the described protective layer; and the exposed described conductive connection pads of part; described heavy distributed circuit layer is arranged on described the first dielectric layer; and comprise a wire portion; one scallop and a pad section; described wire portion one end is electrically connected described conductive connection pads; described scallop forms from described wire portion other end extension; described pad section connects described scallop; described the second dielectric layer covers on described the first dielectric layer and the heavy distributed circuit layer; and the exposed described pad of part section; to define the pad zone that heavily distributes; described metal coupling is arranged on described the second dielectric layer and the pad zone that heavily distributes; described metal coupling comprises a contact-making surface and an ora terminalis; described contact-making surface is connected with described heavy distribution pad zone; described ora terminalis is positioned at described contact-making surface one side and in the face of described scallop, has a buffer distance in order to scattered current between described ora terminalis and the scallop.
Moreover another embodiment of the present invention provides another kind of wafer-grade packaging structure, and wherein said wafer-grade packaging structure comprises semiconductor assembly and a layer that reroutes.Described semiconductor subassembly has an active surface, the described layer that reroutes covers on the described active surface, and has a heavy distributed circuit layer, described heavy distributed circuit layer comprises a wire portion, a scallop and a pad section, described scallop forms from described wire portion extension, described pad section connects described scallop, definition has the pad zone that heavily distributes in the wherein said pad section, and described heavy distribution pad zone is near having a buffer distance in order to scattered current between a side of described scallop and the described scallop.
As mentioned above, owing to be formed with enough buffer distances between described ora terminalis and the scallop, can enlarge electric current through the scope of described ora terminalis, and then the electric current that disperses described wire portion to move toward metal coupling through scallop, reduce described metal coupling to be subject to electron transfer and the influence degree that metallic atom runs off occurs, to avoid producing between described metal coupling and the heavy distributed circuit layer situation of be full of cracks or disconnection.
Description of drawings
Fig. 1 is the cutaway view of one embodiment of the invention wafer-grade packaging structure.
Fig. 2, the 3rd, the signal of the wafer-grade packaging structure of Fig. 1 and use state diagram.
Fig. 4, the 5th, the signal of another embodiment of the present invention wafer-grade packaging structure and use state diagram.
Embodiment
Below the explanation of each embodiment be with reference to additional graphic, can be in order to the specific embodiment of implementing in order to illustration the present invention.Moreover, the direction term that the present invention mentions, such as upper and lower, top, the end, front, rear, left and right, inside and outside, side, on every side, central authorities, level, laterally, vertically, vertically, axially, radially, the superiors or orlop etc., only be the direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the present invention, but not in order to limit the present invention.
Please refer to shown in Fig. 1,2; the wafer-grade packaging structure 100 of one embodiment of the invention mainly comprises semiconductor assembly 2, a protective layer 3, one first dielectric layer 4, a heavy distributed circuit layer 5, one second dielectric layer 6 and at least one metal coupling 7; wherein said semiconductor subassembly 2 refers to still uncut semiconductor crystal wafer (wafer) of semiconductor chip (Chip) in the described wafer-grade packaging structure 100 or its manufacture process front end, and the present invention will be in the detail structure, assembled relation and the operation principles thereof that hereinafter describe one by one above-mentioned each element in detail.
Continuous with reference to shown in Figure 1; described semiconductor subassembly 2 is to form one active surperficial 21 at semiconductor substrate (such as silicon substrate); described active surperficial 21 are provided with at least one conductive connection pads 22; such as aluminium pad (Al Pad); described protective layer 3 for example is silicon dioxide; its cover described active surperficial 21 and conductive connection pads 22 on, the position of described protective layer 3 corresponding conductive connection pads 22 is formed with perforate (indicate), and can partly expose described conductive connection pads 22.
Described the first dielectric layer 4 covers on the described protective layer 3; for example can select benzocyclobutene (Bencocyclobutene; BCB) or polyimides (Polyimide; the organic polymer insulating material such as PI); and the position of described the first dielectric layer 4 corresponding conductive connection pads 22 is formed with perforate (not indicating) equally, and the exposed described conductive connection pads 22 of part.The thickness of wherein said the first dielectric layer 4 can greater than or be equal to the thickness of described protective layer 3.
Continuous with reference to shown in Fig. 1,2, described heavy distributed circuit layer 5 is arranged on described the first dielectric layer 4, such as copper or titanium/copper (Ti/Cu) alloy etc., and comprises a wire portion 51, a scallop 52 and a pad section 53, described wire portion 51 is linear, and the one end is electrically connected described conductive connection pads 22; That described scallop 52 generally is is fan-shaped, isosceles trapezoid or triangle, and described scallop 52 is extended from described wire portion 51 other ends and formed; 53 described scallop 52 that generally take the shape of the letter U and be connected in of described pad section.
Described the second dielectric layer 6, such as selecting the organic polymer insulating material such as benzocyclobutene or polyimides, it covers on described the first dielectric layer 4 and the heavy distributed circuit layer 5, and the position of the corresponding described pad of described the second dielectric layer 6 section 53 is formed with perforate (indicating), and the central, circular zone of the exposed described pad of part section 53, to define the pad zone 53 ' that heavily distributes.
Described the first dielectric layer 4, heavy distributed circuit layer 5 and the second dielectric layer 6 be common to consist of the layer (redistribution layer, a RDL) that reroutes.
Described metal coupling 7, such as tin projection, gold projection or copper post projection, be arranged on described the second dielectric layer 6 and the pad zone 53 ' that heavily distributes, described metal coupling 7 comprises a contact-making surface 71 and an ora terminalis 72, described contact-making surface 71 is connected with described heavy distribution pad zone 53 ', described contact-making surface 71 and described heavy distribution pad zone 53 ' are all circle at this, wherein said ora terminalis 72 is arc and is positioned at described contact-making surface 71 1 sides and faces described scallop 52, have a buffer distance I in order to scattered current between described ora terminalis 72 and the scallop 52, namely have a buffer distance I in order to scattered current between a side of described heavy distribution pad zone 53 ' close described scallop 52 (Fig. 2 left side) and the described scallop 52.The length of described buffer distance I be at least described contact-making surface 71 a Breadth Maximum 1/8, such as 1/7,1/6,1/5,1/4 or 1/3 etc.
Moreover the width of described heavy distribution pad zone 53 ' (contact-making surface 71) is 240 to 260 microns; The width (Fig. 2 above-below direction) of described pad section 53 is 280 to 300 microns; The width of described wire portion 51 be 18 microns or below; The width at the two ends of described scallop 52 (the left and right two ends of Fig. 2) respectively equals the width of described wire portion 51 and the width of described pad section 53.
Please refer to shown in Figure 3, according to above-mentioned structure, owing to be formed with buffer distance I (seeing Fig. 2) between described ora terminalis 72 and the scallop 52, can enlarge electric current through the scope of described ora terminalis 72, and then the electric current (seeing Fig. 3 arrow) that disperses described wire portion 51 to move toward described metal coupling 7 through described scallop 52, preventing that electric current from all concentrating is passed through by described ora terminalis 72 point-like, the influence degree that metallic atom runs off occurs to reduce described metal coupling 7 to be subject to electron transfer, with the situation that produces be full of cracks or disconnect between the heavily distribution pad zone 53 ' of avoiding described metal coupling 7 and described heavy distributed circuit layer 5.
Please refer to shown in Figure 4, the wafer-grade packaging structure of another embodiment of the present invention is similar in appearance to first embodiment of the invention, and roughly continue to use similar elements title and figure number, but the difference characteristic of present embodiment is: described ora terminalis 72 is linear, and the straight length of described ora terminalis 72 be at least described contact-making surface 71 a Breadth Maximum 1/12, such as 1/10,1/8,1/6,1/5,1/4,1/3 or 1/2 etc.
Please refer to shown in Figure 5, according to above-mentioned structure, owing to also be formed with buffer distance I (seeing Fig. 4) between the ora terminalis 72 of present embodiment and the scallop 52, can disperse equally described wire portion 51 through the described electric current (seeing Fig. 5 arrow) that moves toward metal coupling 7, therefore can effectively avoid equally the situation that produces be full of cracks or disconnect between the heavily distribution pad zone 53 ' of described metal coupling 7 and described heavy distributed circuit layer 5.
The present invention is described by above-mentioned related embodiment, yet above-described embodiment is only for implementing example of the present invention.Must be pointed out that published embodiment does not limit the scope of the invention.On the contrary, being contained in the spirit of claims and modification and impartial setting of scope is included in the scope of the present invention.
Claims (10)
1. wafer-grade packaging structure, it is characterized in that: described wafer-grade packaging structure comprises:
The semiconductor assembly has an active surface, and described active surface is provided with at least one conductive connection pads;
One protective layer covers on described active surface and the conductive connection pads, and the exposed described conductive connection pads of part;
One first dielectric layer covers on the described protective layer, and the exposed described conductive connection pads of part;
One heavy distributed circuit layer is arranged on described the first dielectric layer, and comprises: a wire portion, and the one end is electrically connected described conductive connection pads; One scallop forms from described wire portion other end extension; And a pad section, connect described scallop;
One second dielectric layer covers on described the first dielectric layer and the heavy distributed circuit layer, and the exposed described pad of part section, to define the pad zone that heavily distributes; And
At least one metal coupling is arranged on described the second dielectric layer and the pad zone that heavily distributes, and described metal coupling comprises: a contact-making surface is connected with described heavy distribution pad zone; And an ora terminalis, be positioned at described contact-making surface one side and in the face of described scallop, have a buffer distance in order to scattered current between described ora terminalis and the scallop.
2. wafer-grade packaging structure as claimed in claim 1 is characterized in that: described pad section is U-shaped.
3. wafer-grade packaging structure as claimed in claim 1, it is characterized in that: described ora terminalis is arc.
4. wafer-grade packaging structure as claimed in claim 2 is characterized in that: described buffer distance be at least described contact-making surface a Breadth Maximum 1/8.
5. wafer-grade packaging structure as claimed in claim 1, it is characterized in that: described ora terminalis is linear.
6. wafer-grade packaging structure as claimed in claim 5 is characterized in that: the straight length of described ora terminalis be at least described contact-making surface a Breadth Maximum 1/12.
7. wafer-grade packaging structure as claimed in claim 1 is characterized in that: the width of described wire portion be 18 microns or below.
8. wafer-grade packaging structure, it is characterized in that: described wafer-grade packaging structure comprises:
The semiconductor assembly has an active surface; And
One layer that reroutes covers on the described active surface, and has a heavy distributed circuit layer, and described heavy distributed circuit layer comprises:
One wire portion;
One scallop forms from described wire portion extension; And
One pad section connects described scallop, and definition has the pad zone that heavily distributes in the wherein said pad section, and described heavy distribution pad zone is near having a buffer distance in order to scattered current between a side of described scallop and the described scallop.
9. wafer-grade packaging structure as claimed in claim 8, it is characterized in that: described ora terminalis is arc.
10. wafer-grade packaging structure as claimed in claim 8, it is characterized in that: described ora terminalis is linear.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310287219XA CN103367315A (en) | 2013-07-08 | 2013-07-08 | Wafer level packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310287219XA CN103367315A (en) | 2013-07-08 | 2013-07-08 | Wafer level packaging structure |
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| Publication Number | Publication Date |
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| CN103367315A true CN103367315A (en) | 2013-10-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310287219XA Pending CN103367315A (en) | 2013-07-08 | 2013-07-08 | Wafer level packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114400214A (en) * | 2022-01-07 | 2022-04-26 | 广东气派科技有限公司 | Method for improving crack of Flip chip wafer circuit layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004001837A2 (en) * | 2002-06-25 | 2003-12-31 | Unitive International Limited | Methods of forming electronic structures including conductive shunt layers and related structures |
| US20060076679A1 (en) * | 2002-06-25 | 2006-04-13 | Batchelor William E | Non-circular via holes for bumping pads and related structures |
| CN102810506A (en) * | 2011-06-03 | 2012-12-05 | 台湾积体电路制造股份有限公司 | Electrical connection for chip scale packaging |
-
2013
- 2013-07-08 CN CN201310287219XA patent/CN103367315A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004001837A2 (en) * | 2002-06-25 | 2003-12-31 | Unitive International Limited | Methods of forming electronic structures including conductive shunt layers and related structures |
| US20060076679A1 (en) * | 2002-06-25 | 2006-04-13 | Batchelor William E | Non-circular via holes for bumping pads and related structures |
| CN102810506A (en) * | 2011-06-03 | 2012-12-05 | 台湾积体电路制造股份有限公司 | Electrical connection for chip scale packaging |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114400214A (en) * | 2022-01-07 | 2022-04-26 | 广东气派科技有限公司 | Method for improving crack of Flip chip wafer circuit layer |
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Application publication date: 20131023 |