CN103364704B - A kind of Forecasting Methodology of polysilicon chip open circuit voltage - Google Patents

A kind of Forecasting Methodology of polysilicon chip open circuit voltage Download PDF

Info

Publication number
CN103364704B
CN103364704B CN201310263287.2A CN201310263287A CN103364704B CN 103364704 B CN103364704 B CN 103364704B CN 201310263287 A CN201310263287 A CN 201310263287A CN 103364704 B CN103364704 B CN 103364704B
Authority
CN
China
Prior art keywords
polysilicon chip
open circuit
circuit voltage
image
batch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310263287.2A
Other languages
Chinese (zh)
Other versions
CN103364704A (en
Inventor
付少永
熊震
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Trina Solar Co Ltd
Original Assignee
Changzhou Trina Solar Energy Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changzhou Trina Solar Energy Co Ltd filed Critical Changzhou Trina Solar Energy Co Ltd
Priority to CN201310263287.2A priority Critical patent/CN103364704B/en
Publication of CN103364704A publication Critical patent/CN103364704A/en
Application granted granted Critical
Publication of CN103364704B publication Critical patent/CN103364704B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

The invention discloses a kind of Forecasting Methodology of polysilicon chip open circuit voltage.Present invention utilizes CCD imaging technique and luminescence generated by light (PL) imaging technique, from polysilicon chip ccd image, extract the photogenerated current I of expection l, from PL figure, extract reverse saturation current I 0, and predict the open circuit voltage V of polysilicon chip on this basis oc.The invention also discloses predicts the outcome based on open circuit voltage sorts the technology of polysilicon chip.

Description

A kind of Forecasting Methodology of polysilicon chip open circuit voltage
Technical field
The present invention relates to the battery performance prediction field of polysilicon chip, particularly relate to a kind of polysilicon chip open circuit voltage (V oc) Forecasting Methodology.
Background technology
In polysilicon solar cell field, battery production business and silicon manufacturer all need a kind of method of judgement Si wafer quality of fast and reliable.Wherein, the open circuit voltage V of polysilicon chip oca kind of important parameter reflecting photovoltaic generation performance, therefore, can based on V ocpredict the outcome judge Si wafer quality.
Luminescence generated by light imaging (PL Imaging) technology is a kind of fast optical detection method.By process PL image, more existing algorithms at present, predict that the battery performance of polysilicon chip is (comprising prediction open circuit voltage V oc).But these methods are all confined to the information of luminescence generated by light imaging technique itself, have departing from of can not ignore between different batches experimental result.
Summary of the invention
The present invention is intended to the deficiency overcoming routine techniques means, proposes one polysilicon chip open circuit voltage V more accurately ocforecasting Methodology.
In general, for achieving the above object, present invention utilizes CCD imaging technique and luminescence generated by light (PL) imaging technique, from polysilicon chip ccd image, extract the photogenerated current I of expection l, from PL figure, extract reverse saturation current I 0, and predict the open circuit voltage V of polysilicon chip on this basis oc.
According to a kind of polysilicon chip open circuit voltage Forecasting Methodology of the present invention, comprising: the luminescence generated by light PL image and the ccd image that a) gather polysilicon chip; B) the PL image that gathers is processed therefrom to extract permanent defects information; C) calculate based on treated PL image wherein β ito represent in treated PL image the brightness value of a bit; D) calculate (k2-α) based on gathered ccd image, wherein α is the average brightness value of ccd image; And e) will (k2-α) substitutes into open circuit voltage V ocpredictor formula 1:
V oc = kT q ln ( k 1 k 2 - α Σ 1 m 1 k 3 + β i + 1 )
Wherein k1, k2, k3 are constant, and kT/q is thermal voltage.
According to an aspect of the present invention, described constant k3 by value for making be proportional to total reverse saturation current I of described polysilicon chip 0.
According to an aspect of the present invention, described constant k3=95.2.
According to an aspect of the present invention, described constant k2 is by the photogenerated current I of value for making (k2-α) be proportional to described polysilicon chip l.
According to an aspect of the present invention, the least square method based on the batch silicon wafer of known actual open circuit voltage demarcates described constant k1 and k2.
According to an aspect of the present invention, described constant k2=2130, k3=95.2.
According to an aspect of the present invention, described step b) in, maximum filtering is carried out to gathered PL image, and subtracts each other with original image and filtering image.
According to a kind of polysilicon chip open circuit voltage prognoses system of the present invention, comprising: luminescence generated by light imaging device; CCD optical imaging apparatus; And computing equipment, for realizing open circuit voltage Forecasting Methodology of the present invention.
According to test and the method for sorting of a kind of polysilicon chip of the present invention, comprising: by the open circuit voltage V of Forecasting Methodology prediction batch polysilicon chip of the present invention oc; And based on predicted open circuit voltage V ocbatch polysilicon chip is tested and sorted.
According to test and the sorting system of a kind of polysilicon chip of the present invention, comprising: aforesaid open circuit voltage prognoses system, for predicting the open circuit voltage V of batch polysilicon chip oc; And sorting mechanism, based on predicted open circuit voltage V ocbatch polysilicon chip is sorted.
Accompanying drawing explanation
Comprising accompanying drawing is further understand the present invention for providing, and they are included and form a application's part, and accompanying drawing shows embodiments of the invention, and plays the effect explaining the principle of the invention together with this specification.In accompanying drawing:
Fig. 1 is the polysilicon chip open circuit voltage V according to the embodiment of the present invention octhe flow chart of Forecasting Methodology.
Fig. 2 a is polysilicon chip luminescence generated by light (PL) image collected according to the embodiment of the present invention.
Fig. 2 b is the polysilicon chip ccd image collected according to the embodiment of the present invention.
Fig. 3 is according to the image after the processing PL image of the embodiment of the present invention.
Fig. 4 is the prediction V obtained according to experimental example of the present invention ocwith actual V occomparison diagram.
Embodiment
An exemplary polysilicon chip open circuit voltage Forecasting Methodology is described as follows, it should be noted that, for ease of understanding, following examples give a lot of implementation detail and technical parameter, but these ins and outs and technical parameter are only the object of example, are not construed as limiting the invention.Meanwhile, should be understood that also not all ins and outs and technical parameter are all that enforcement the present invention is necessary.
Fig. 1 illustrates the method for prediction polysilicon chip open circuit voltage according to an embodiment of the invention, comprises following basic step:
1) IMAQ (step 101 in Fig. 1) of polysilicon chip.Comprise and photoluminescence image collection is carried out to polysilicon chip, obtain the PL image such as shown in Fig. 2 a, and ccd image collection is carried out to polysilicon, obtain such as ccd image shown in Fig. 2 b.The resolution of PL image is 16 dark or more Gao Weijia.
2) PL image is processed (step 102 in Fig. 1).This step mainly comprises the information extraction to permanent defects in PL image.The Defect shown in PL image some can remove in cell manufacturing process (as the diffusion of ingot casting process sidewall of crucible causes, the black surround on right side in Fig. 2 a), other then can not (part as cluster-shaped and wire in Fig. 2 a).In addition, in PL image pixel brightness reflection be the size of its position excess carrier concentration Δ n.And when little injection, Δ n is proportional to the minority carrier life time of this point.In order to estimate the impact of PL image permanent defects, can be handled as follows PL image: such as 40 × 40 maximum filtering are carried out to image, and subtracts each other with it with original image, obtain image as shown in Figure 3.In Fig. 3, the brightness value of every bit (is set to β i) meaning be the difference of maximum in corresponding points brightness and its neighborhood in Fig. 2 a.Brightness is lower, then minority carrier life time is lower.The method of this maximum Neighborhood Filtering can be forgone the information of removable defect in PL figure effectively.
3) reverse saturation current I is estimated 0(step 103 in Fig. 1)
Reverse saturation current I is estimated based on treated PL image 0.In prediction algorithm of the present invention, total reverse saturation current I of whole silicon chip 0computing formula be
I 0 = Σ 1 m I 0 i ,
Wherein I 0ifor the reverse saturation current of pixel position each in treated PL image, its computing formula is again
I 0 i = Aq D e n i 2 τ ei N A ,
In above formula: A represents sectional area; Q representation element electric charge; n iit is the intrinsic carrier concentration of material; N ait is the p side acceptor concentration of pn knot; D eit is less sub-diffusion coefficient; τ eiit is minority carrier life time.Except τ eiother parameters outer are all constant, therefore I 0with be directly proportional, k3 is undetermined constant.
Therefore, can calculate as with I 0the estimated value be directly proportional.
4) photogenerated current I is estimated l(step 104 in Fig. 1)
Photogenerated current I is estimated based on silicon chip ccd image reflective information l.Suppose that ccd image mean flow rate is α, then its reflectivity becomes a positive correlation with α.Prediction algorithm of the present invention hypothesis cell reflective rate and silicon chip reflectivity are also a positive correlation, then cell reflective rate also becomes a positive correlation with α, and with photogenerated current I lbecome a negative correlation.It can thus be appreciated that I lbe directly proportional to (k2-α), k2 is another undetermined constant.
Therefore, can calculate (k2-α) as with I lthe estimated value be directly proportional.
5) V is calculated oc(step 105 in Fig. 1)
Will (k2-α) substitutes into V ocpredictor formula calculates.Empirical equation after substitution is:
V oc = kT q ln ( k 1 k 2 - α Σ 1 m 1 k 3 + β i + 1 ) (formula 1)
Wherein kT/q is thermal voltage, and parameter k3 is compared by the filtered PL figure of minority carrier lifetime scintigram after polysilicon chip passivation and maximum and obtains, and such as value is 95.2.More particularly, for the silicon chip after abundant passivation, on life test scintigram certain point life value should after filtering corresponding to it on PL figure corresponding points become once relation, k3 can by the intercept decision of this once relation.K1, k2 actual V of known corresponding battery ocbatch silicon wafer least square method demarcate, such as k1=9.82 × 10 9, k2=2130.
The numbering of said method step be only description just, and do not mean that each step must order successively be implemented according to this.Such as, step 3) and step 4) in fact can carry out simultaneously.
Corresponding polysilicon chip open circuit voltage prognoses system is contained in the present invention simultaneously.According to one embodiment of present invention, polysilicon chip open circuit voltage detection system comprises luminescence generated by light imager and CCD optical imaging instrument, also comprise calculation element, for receiving the silicon chip image that luminescence generated by light imager and CCD optical imaging instrument obtain, and implement open circuit voltage prediction algorithm of the present invention.Described calculation element can be any device realizing special algorithm logic, and it can comprise the general purpose computer of software program for execution, also can comprise the hardware of custom-made, such as FPGA, ASIC, DSP etc.
The present invention also should contain the method and corresponding system that the result based on the prediction of polysilicon chip open circuit voltage sorts batch polysilicon chip.
Experimental example:
An experimental example according to the present invention is as follows:
Get constant k1=9.82 × 10 9, k2=2130, k3=95.2;
Silicon chip is put into test macro, obtains silicon chip photoluminescence image and ccd image respectively;
Process PL image is calculated process ccd image is calculated (k2-α); And
The above results is substituted into formula 1, calculate V ocpredicted value.
According to above-mentioned experimental example, open circuit voltage test has been carried out to many group batch silicon wafers, and and actual be prepared into battery after the V that records occompare, as shown in Figure 4, abscissa is actual V oc, ordinate is prediction V oc, it is near the straight line of 1 that data point is distributed in slope substantially, surperficial actual V ocwith prediction V ocbetween have good degree of conformity.Meanwhile, in experimental example, the test of silicon chip and processing speed are all less than 1s, are highly suitable for online Si wafer quality and judge and sorting.
Technique effect
The present invention utilizes the physical meaning of two kinds of quick silicon wafer test methods, considers the information of silicon chip ccd image and PL image simultaneously, establishes the forecast model of its open circuit voltage.Be proven, open circuit voltage Forecasting Methodology of the present invention can provide the open circuit voltage being coincident with actual value well to predict the outcome, and test and processing speed satisfactory.

Claims (8)

1. a polysilicon chip open circuit voltage Forecasting Methodology, comprising:
A) luminescence generated by light PL image and the ccd image of polysilicon chip is gathered;
B) the PL image that gathers is processed therefrom to extract permanent defects information;
C) calculate based on treated PL image wherein β ito represent in treated PL image the brightness value of a bit;
D) calculate (k2-α) based on gathered ccd image, wherein α is the average brightness value of ccd image; And
E) will (k2-α) substitutes into open circuit voltage V ocpredictor formula 1:
V oc = kT q ln ( k 1 k 2 - α Σ 1 m 1 k 3 + β i + 1 )
Wherein k1, k2, k3 are constant, and kT/q is thermal voltage,
Described constant k3 by value for making be proportional to total reverse saturation current I of described polysilicon chip 0,
Described constant k2 is by the photogenerated current I of value for making (k2-α) be proportional to described polysilicon chip l.
2. the method for claim 1, is characterized in that, described constant k3=95.2.
3. the method for claim 1, is characterized in that, the least square method based on the batch silicon wafer of known actual open circuit voltage demarcates described constant k1 and k2.
4. the method for claim 1, is characterized in that, described constant k2=2130, k3=95.2.
5. the method for claim 1, is characterized in that, described step b) in, maximum filtering is carried out to gathered PL image, and subtracts each other with original image and filtering image.
6. a polysilicon chip open circuit voltage prognoses system, comprising:
Luminescence generated by light imaging device;
CCD optical imaging apparatus; And
Computing equipment, for realizing the method according to any one of claim 1-5.
7. the test of polysilicon chip and a method for sorting, comprising:
By the open circuit voltage V of the method prediction batch polysilicon chip any one of claim 1-5 oc; And
Based on predicted open circuit voltage V ocbatch polysilicon chip is tested and sorted.
8. the test of polysilicon chip and a sorting system, comprising:
Open circuit voltage prognoses system as claimed in claim 6, for predicting the open circuit voltage V of batch polysilicon chip oc; And
Sorting mechanism, based on predicted open circuit voltage V ocbatch polysilicon chip is sorted.
CN201310263287.2A 2013-06-26 2013-06-26 A kind of Forecasting Methodology of polysilicon chip open circuit voltage Active CN103364704B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310263287.2A CN103364704B (en) 2013-06-26 2013-06-26 A kind of Forecasting Methodology of polysilicon chip open circuit voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310263287.2A CN103364704B (en) 2013-06-26 2013-06-26 A kind of Forecasting Methodology of polysilicon chip open circuit voltage

Publications (2)

Publication Number Publication Date
CN103364704A CN103364704A (en) 2013-10-23
CN103364704B true CN103364704B (en) 2015-10-28

Family

ID=49366495

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310263287.2A Active CN103364704B (en) 2013-06-26 2013-06-26 A kind of Forecasting Methodology of polysilicon chip open circuit voltage

Country Status (1)

Country Link
CN (1) CN103364704B (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101581671A (en) * 2009-06-12 2009-11-18 3i系统公司 Solar cell silicon chip detecting system
CN102017191A (en) * 2008-03-31 2011-04-13 Bt成像股份有限公司 Wafer imaging and processing method and apparatus
CN102144284A (en) * 2008-08-19 2011-08-03 Bt成像股份有限公司 Method and apparatus for defect detection
CN102565659A (en) * 2011-12-31 2012-07-11 常州天合光能有限公司 Solar grade ingoting polycrystalline silicon chip characterization method
CN102680444A (en) * 2012-05-11 2012-09-19 常州天合光能有限公司 Method for testing crystal orientations of polycrystalline silicon wafer
CN102974551A (en) * 2012-11-26 2013-03-20 华南理工大学 Machine vision-based method for detecting and sorting polycrystalline silicon solar energy
CN103091616A (en) * 2013-01-29 2013-05-08 南昌航空大学 New analytic method for extracting solar battery parameters
CN103105574A (en) * 2013-01-29 2013-05-15 南昌航空大学 Analytic method for extracting solar battery parameter

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI262504B (en) * 2003-04-15 2006-09-21 Ibm Dynamic semiconductor memory device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102017191A (en) * 2008-03-31 2011-04-13 Bt成像股份有限公司 Wafer imaging and processing method and apparatus
CN102144284A (en) * 2008-08-19 2011-08-03 Bt成像股份有限公司 Method and apparatus for defect detection
CN101581671A (en) * 2009-06-12 2009-11-18 3i系统公司 Solar cell silicon chip detecting system
CN102565659A (en) * 2011-12-31 2012-07-11 常州天合光能有限公司 Solar grade ingoting polycrystalline silicon chip characterization method
CN102680444A (en) * 2012-05-11 2012-09-19 常州天合光能有限公司 Method for testing crystal orientations of polycrystalline silicon wafer
CN102974551A (en) * 2012-11-26 2013-03-20 华南理工大学 Machine vision-based method for detecting and sorting polycrystalline silicon solar energy
CN103091616A (en) * 2013-01-29 2013-05-08 南昌航空大学 New analytic method for extracting solar battery parameters
CN103105574A (en) * 2013-01-29 2013-05-15 南昌航空大学 Analytic method for extracting solar battery parameter

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
晶硅太阳电池电致发光研究及缺陷电池的Matlab数字图像识别;肖娇;《中国优秀硕士学位论文全文数据库工程科技II辑》;20110615(第7期);全文 *

Also Published As

Publication number Publication date
CN103364704A (en) 2013-10-23

Similar Documents

Publication Publication Date Title
TWI609177B (en) Wafer imaging and processing method and apparatus
JP5413785B2 (en) Solar cell evaluation method, evaluation apparatus, maintenance method, maintenance system, and solar cell module manufacturing method
Altermatt et al. High-performance p-type multicrystalline silicon (mc-Si): Its characterization and projected performance in PERC solar cells
TW200931554A (en) Photovoltaic cell manufacturing
CN112991264B (en) Method for detecting crack defect of monocrystalline silicon photovoltaic cell
TW201330136A (en) Qualification of silicon wafers for photo-voltaic cells by optical imaging
Mitchell et al. PERC solar cell performance predictions from multicrystalline silicon ingot metrology data
Trupke et al. Progress with luminescence imaging for the characterisation of silicon wafers and solar cells
CN109540900B (en) Photovoltaic module subfissure judgment method
Xu et al. Detection methods for micro-cracked defects of photovoltaic modules based on machine vision
Hameiri et al. Evaluation of recombination processes using the local ideality factor of carrier lifetime measurements
Prabhakaran et al. Deep Learning-Based Model for Defect Detection and Localization on Photovoltaic Panels.
Chawla et al. A Mamdani fuzzy logic system to enhance solar cell micro-cracks image processing
Kristensen et al. A high-accuracy calibration method for temperature dependent photoluminescence imaging
Sio et al. 3-D modeling of multicrystalline silicon materials and solar cells
CN103364704B (en) A kind of Forecasting Methodology of polysilicon chip open circuit voltage
Hess et al. Crystal defects and their impact on ribbon growth on substrate (RGS) silicon solar cells
CN101915546B (en) Solar chip anti-reflection coating detection method and detection device thereof
Fu et al. Cell performance prediction based on the wafer quality
CN201740515U (en) Detecting device of antireflection layer of solar chip
Höffler et al. Statistical Evaluation of a Luminescence-based Method for imaging the series resistance of solar cells
CN102927918A (en) Detection method and device of anti-reflection layer of solar chip
Mankad et al. Inline bulk-lifetime prediction on as-cut multicrystalline silicon wafers
Kristensen Temperature coefficients and crystal defects in multicrystalline silicon solar cells
Abbott et al. Application of photoluminescence to high-efficiency silicon solar cell fabrication

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: 213031 Tianhe Road, Tianhe PV Industrial Park, Changzhou, Jiangsu Province, No. 2

Patentee after: TRINA SOLAR Co.,Ltd.

Address before: 213031 Tianhe Road, Tianhe PV Industrial Park, Changzhou, Jiangsu Province, No. 2

Patentee before: trina solar Ltd.

Address after: 213031 Tianhe Road, Tianhe PV Industrial Park, Changzhou, Jiangsu Province, No. 2

Patentee after: trina solar Ltd.

Address before: 213031 Tianhe Road, Tianhe PV Industrial Park, Changzhou, Jiangsu Province, No. 2

Patentee before: CHANGZHOU TRINA SOLAR ENERGY Co.,Ltd.