CN103346862A - On-chip network data transmission device and method with cascade protection function - Google Patents
On-chip network data transmission device and method with cascade protection function Download PDFInfo
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- CN103346862A CN103346862A CN201310272366XA CN201310272366A CN103346862A CN 103346862 A CN103346862 A CN 103346862A CN 201310272366X A CN201310272366X A CN 201310272366XA CN 201310272366 A CN201310272366 A CN 201310272366A CN 103346862 A CN103346862 A CN 103346862A
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Abstract
The invention discloses an on-chip network data transmission device and method with a cascade protection function and belongs to the technical field of multi-core chips. The device comprises a data coding unit, a head protection unit and a data decoding unit, wherein the data coding unit is used for achieving fault-tolerant coding of all data of a data package; the head protection unit is used for achieving skip-to-skip protection for a head chip; the data decoding unit is used for achieving decoding of the data package, requesting end-to-end retransmission when the number of errors exceeds the error correcting capability of adopted codes, and thus achieving end-to-end protection for the data package. Meanwhile, the invention discloses the on-chip network data transmission method with the cascade protection function. Reliable protection is conducted at the two stages of the data package and the chip, namely, the end-to-end protection is conducted on the data package and the skip-to-skip protection is conducted on the head chip, and the method can be achieved through the device. The device and method not only ensure on-chip network reliability, but also achieve data transmission which is low in power consumption and short in delay time.
Description
Technical field
The present invention relates to network-on-chip data transmission device and the method for multi core chip technical field, particularly a kind of cascade protection.
Background technology
(Network-on-Chip NoC) is extensively thought and is promised to be the communications infrastructure in the extensive multi core chip (multi-core chip) most network-on-chip.
Because the restriction of network-on-chip router buffer memory, the bag that transmits in network-on-chip (packet) is divided into littler unit----sheet (flit) to be transmitted.These sheets are divided into a sheet (head flit) and data slice (data flit) again.The routing iinformation that comprises this packet in the sheet, namely the route of whole packet is to be determined by a sheet, data slice moves to destination node immediately following a sheet.
Yet all kinds of software and hardware mistakes (be soft error, crosstalk etc. as single event upset) may cause the bust this of network-on-chip.For example, the mistake in the sheet may cause packet can't arrive correct destination node.Therefore, reliability becomes one of key technology of network-on-chip design.
Usually way mainly is divided into two classes: a kind of is the solution that relies on end-to-end (end-to-end) to retransmit, and rises but work as error rate, and retransmitting the delay expense of bringing will increase greatly, have a strong impact on the transmission performance of network-on-chip.Another kind is that all data are carried out strict hop to hop (hop-by-hop) protection, but this method will cause the rapid rising that the router cache expense is big and transmit power consumption.
Summary of the invention
(1) technical problem that will solve
Technical problem to be solved by this invention is at the prior art deficiency, to provide a kind of network-on-chip data transmission device and method of cascade protection, assurance network-on-chip transmission reliability, reduction transmission power consumption and delay simultaneously.
(2) technical scheme
For solving the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of network-on-chip data transmission device of cascade protection, comprise network interface and a plurality of router, described network interface comprises transmitting terminal network interface and receiving terminal network interface, be provided with in the described transmitting terminal network interface for the data coding unit that packet is carried out fault-tolerant encoding and the re-transmission buffer memory of the whole packet of storage in order to end-to-end re-transmission, described data coding unit output is connected with described re-transmission buffer memory input; Described router comprises cross bar switch and is used for a sheet of packet is carried out the head protection unit of hop to hop protection, the output of described head protection unit is connected with the cross bar switch input, and the output of described cross bar switch connects the input of next hop router or receiving terminal network interface; Be provided with in the described receiving terminal network interface for to the decoded packet data behind the coding and wrong number exceed institute adopts encode ask the data decode unit of end-to-end re-transmission during the fault-tolerant wrong number of energy.
Device of the present invention is protected respectively packet (packet) and sheet (flit) two-stage.For data packet level, realize that described transmitting terminal network interface is to end-to-end (end-to-end) protection of described receiving terminal network interface; For the sheet rank, realize that at a sheet (head flit) each jumps hop to hop (hop-by-hop) protection of described router or described network interface.
The packet that described transmitting terminal network interface sends is delivered to described receiving terminal networking interface behind router, be provided with in the described transmitting terminal network interface for the data coding unit that packet is carried out fault-tolerant encoding and the re-transmission buffer memory of the whole packet of storage in order to end-to-end re-transmission; Described router comprises cross bar switch and be used for head protection unit to a sheet of the packet behind the coding carries out crosstalking in the protection, tolerance transmission line of hop to hop and the memory soft error leads to errors in a sheet, the output of described head protection unit is connected with the cross bar switch input, and the output of described cross bar switch connects the input of next hop router or receiving terminal network interface; Be provided with in the described receiving terminal network interface for to the decoded packet data behind the coding and wrong number exceed institute adopts encode ask the data decode unit of end-to-end re-transmission during the fault-tolerant wrong number of energy.
Described data coding unit is encoded to data, and is a packet adding sheet.Sending packet in the router, it is saved to is retransmitting buffer memory and prepare against end-to-end re-transmission.
Described head protection unit comprises sampling module, first in first out buffer memory and most vote module three times.Described three sampling modules comprise three registers, two MUX, No. three sampling controllers, described three registers all are connected with first MUX, first MUX is connected with second MUX, the clock signal of the first register receiving chip, second register is by the clock signal of the first little retardation element receiving chip, and the 3rd register is by the clock signal of the described first little retardation element and the second little retardation element receiving chip; Described little retardation element is in series by two not gates (inverter).The output of described No. three sampling controllers is connected with described first MUX, second MUX and controls its gating way.The packet of a last hop node is divided into three the tunnel, and first via data slice is imported second MUX into, and the second road sheet is sent in described first, second, third register, and described No. three sampling controllers are sent in all sheet type code positions of Third Road.Described second MUX is connected with described first in first out buffer memory.Described most vote module comprises three registers, ballot ruling comparator, the 3rd MUX, most polling controller.The 4th register inserts ballot ruling comparator, and the 5th register inserts between described the 4th register and the ballot ruling comparator, and the 6th register inserts between described the 5th register and the ballot ruling comparator.Described first in first out buffer memory data packets transmitted is divided into three the tunnel: the first via is that data slice is directly imported the 3rd MUX into, and the second road sheet is sent into described the 4th register, and described most polling controller is sent in the type code position of all sheets of Third Road.The input clock signal of described the 4th register, the 5th register, the 6th register, most polling controllers is the clock signal of the chip that adopts.Described most polling controller is connected with described the 3rd MUX and controls its gating way; The enable signal of the output of described the 3rd MUX and described most polling controller outputs inserts cross bar switch; A wherein said last hop node is transmitting terminal network interface or router.
Described data decode unit is data decoder, realizes decoding and error correction to packet.
Utilize described transmitting device to the cascade protection method of network-on-chip transfer of data to be:
1) after the transmitting terminal network interface receives the packet that the transmitting terminal core need send, packet is carried out fault-tolerant encoding, and the packet cutting after will encoding is a plurality of data slice;
2) add a sheet that comprises whole packet routing iinformation for the packet behind the coding;
3) the transmitting terminal network interface sends the packet that adds the higher authorities' sheet to the next-hop node request, and after transmission that packet is temporary, in order to end-to-end re-transmission;
4) after this node router receives a hop node (router or transmitting terminal network interface) transmission request, judge whether the data slice of request transmission is a sheet, if enter 5); If not, then the data slice of request transmission directly is transferred to next-hop node through second MUX, first in first out buffer memory, the 3rd MUX, if next-hop node is the receiving terminal network interface, then jumps to 8);
5) three continuous clock cycles the sheet in three registers of three sampling modules of this node router is sent into the first in first out buffer memory respectively;
6) this node router reads in above-mentioned three stature sheets backup respectively three registers of most vote module three continuous clock cycle;
7) the majority ballot is carried out in the sheet step-by-step in three registers of most vote module, the sheet after the ruling enters cross bar switch and further exchanges to next-hop node, thereby realizes the hop to hop protection of a sheet;
8) after the receiving terminal network interface receives a hop router data packets for transmission, this packet is decoded, if decoding detected error number then sends the correct data bag after the error correction to the receiving terminal core within the fault-tolerant ability scope of employing fault-tolerant encoding; If decoding detected error number has exceeded the fault-tolerant ability of used fault-tolerant encoding, then ask the transmitting terminal network interface to retransmit this packet, thereby realize the end-to-end protection of packet.
In the described step 1), adopt cyclic redundancy code or hamming code that packet is carried out fault-tolerant encoding.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, utilizes the device and method that the data Bumper is carried out hop to hop (hop-by-hop) protection provided by the invention; can tolerate the mistake that the data packet head sheet occurs effectively in transmission course; guarantee the destination end that routes to that packet can be correct, thereby guaranteed the reliability data transmission of network-on-chip.
2, utilize the packet to packet provided by the invention to carry out protective device and the method for end-to-end (end-to-end), greatly reduce delay and power consumption expense that the every jumping protection of network-on-chip brings.
3, utilize the apparatus and method to the cascade protection of the different bag of transmission packet sheet provided by the invention; under the prerequisite that guarantees reliability; minimizing is to the frequent operation of non-sheet, thereby significantly reduces transmission delay and power consumption expense, is applicable to the communications infrastructure of following multi core chip.
Description of drawings
Fig. 1 is one embodiment of the invention apparatus structure schematic diagram, wherein: the protection of → expression hop to hop head sheet;
Represent end-to-end packet protection and retransmit;
Fig. 2 is head protection cellular construction schematic diagram of the present invention;
Fig. 3 is in the head protection used in the present invention unit, a kind of logic circuit structure of No. three sampling controllers;
Fig. 4 is in the head protection used in the present invention unit, the method flow diagram of No. three sampling controllers;
Fig. 5 is in the head protection used in the present invention unit, a kind of logic circuit structure of most polling controllers;
Fig. 6 is in the head protection used in the present invention unit, the method flow diagram of most polling controllers;
Fig. 7 is the flow chart of network-on-chip cascade protection method of the present invention.
Embodiment
As shown in Figure 1, one embodiment of the invention is that example describes with the network topology structure of Mesh2x2.The function that this device is realized is: hop to hop (hop-by-hop) protection of a sheet (head flit) and packet end-to-end (end-to-end) protection.This device comprises data coding unit, head protection unit and data decode unit.Wherein, data coding unit and data decode unit lay respectively in the network interface of the network interface of transmitting terminal and receiving terminal, be used for realizing packet is carried out fault-tolerant encoding and decoding, and when wrong number exceeds the error correcting capability of fault-tolerant encoding, carry out end-to-end retransmission data packet may.Retransmission data packet may is stored in the re-transmission buffer memory of transmitting terminal network interface.The head protection unit is arranged in the router of network-on-chip, is used for the protection that realization is transmitted between each router and router the data Bumper.The head protection unit is arranged in before the cross bar switch of router, and its output connects to the end specified next router entrance or the receiving terminal network interface of routing iinformation in the sheet by cross bar switch.
Fig. 2 is head protection cellular construction figure.The head protection unit comprises sampling module, first in first out buffer memory and most vote module three times, realizes the protection to the data Bumper:
Described three sampling modules comprise three register (R1, R2, R3), two MUX (MUX1, MUX2), No. three sampling controllers, described three register R1, R2, R3 is connected with the first MUX MUX1, the first MUX MUX1 is connected with the second MUX MUX2, the first register R1 directly adopts clock signal chip clk, the second register R2 adopts described clock signal chip clk through the first little retardation element (δ among Fig. 2) clock signal afterwards, and the 3rd register R3 adopts described clock signal chip clk through the clock signal after the first little retardation element and the second little retardation element.Described little retardation element is in series by two not gates (being inverter).Described No. three sampling controllers are connected with the described first MUX MUX1, the second MUX MUX2, control the gating way of the described first MUX MUX1, the second MUX MUX2; The packet of a last hop node is divided into three the tunnel, and first via data slice is imported second MUX into, and the second road sheet is sent in described first, second, third register, and all sheet type code positions of Third Road are sent in described No. three sampling controllers.Described second MUX is connected with described first in first out buffer memory.No. three sampling controller control data slice are through these three sampling modules of the second MUX MUX2 bypass.
Described first in first out buffer memory is made up of one group of register, realizes the first in first out storage and management of all bag sheets (flit), and produces the request of transmission to most vote module.
Described most vote module comprises three registers (R4, R5, R6), ballot ruling comparator, the 3rd MUX MUX3, most polling controller.The 4th register R4 inserts ballot ruling comparator, and the 5th register R5 inserts between described the 4th register R4 and the ballot ruling comparator, and the 6th register R6 inserts between described the 5th register R5 and the ballot ruling comparator; Described first in first out buffer memory data packets transmitted is divided into three the tunnel: first via data slice is directly imported the 3rd MUX MUX3 into, and the second road sheet is sent into described the 4th register R4, and described most polling controller is sent in all sheet type code positions of Third Road.Described the 4th register R4, the 5th register R5, the 6th register R6 insert the clock signal of chip.Three registers (R4, R5, R6) are read in three backups of a sheet in the first in first out buffer memory respectively.Described most polling controller is connected with described the 3rd MUX MUX3, controls the gating way of described the 3rd MUX MUX3; The enable signal enable of the output of described the 3rd MUX and described most polling controller outputs inserts cross bar switch; To the ruling of voting of the content in these three registers, ballot ruling result is sent to cross bar switch by MUX MUX3.These MUX and ballot ruling are controlled by most polling controllers.
Described No. three sampling controllers are one group of logical circuits, and Fig. 3 is its a kind of implementation structure.Wherein flit type code position is for using " 1 ", " 0 " expression sheet and data slice respectively, flit type code position and high level (logical one) through first with the door AND1 after control the second MUX MUX2 gating, clock pulse count part through second with door AND2 and the 3rd with door AND3 after, and first control jointly with the output of door AND1 and to select the first MUX MUX1.Clock pulse count begins counting when the flit type code is " 1 ", maximum count is binary system " 11 ", when being first clock pulse a sheet read in first, second, third register R1, R2, R3, in three clock cycle subsequently, when clock pulse count is output as binary system " 01 ", " 10 ", " 11 ", control the first MUX MUX1 gating " 0 " " 1 " " 2 " road respectively, namely export the sheet of first, second, third register R1, R2, R3 respectively.
The method flow that described No. three sampling controllers are realized as shown in Figure 4.When the connection control line that detects a last hop node (router or transmitting terminal network interface) has the request of transmission, judge according to flit type code position whether current flit is a flit, if not " 0 " road of the gating second MUX MUX2 then, flit directly is sent to the first in first out buffer memory with these data.If current flit is a flit, then control " 1 " road of the gating second MUX MUX2, and in three continuous clock cycles (clk+1, clk+2, clk+3) subsequently the content in three registers (R1, R2, R3) is sent into first in first out (FIFO) buffer memory respectively.
Described most polling controller is one group of logical circuit, and Fig. 5 is its a kind of implementation structure.Wherein the flit type code is for using " 1 ", " 0 " expression sheet and data slice respectively, flit type code and high level (logical one) through the 4th with door AND4 after control the gating of the 3rd MUX MUX3; When being " 1 ", just triggers the flit type code counting of clock pulse count, clock pulse count is output as " 11 " namely during the 3rd clock pulse through the 5th with a door AND5, enable signal enble is that high level is logical one, and the 3rd MUX MUX3 selects " 1 " road namely to export the result of ballot ruling comparator.
The method flow of the realization of described most polling controllers as shown in Figure 6.When flit type code position was non-sheet, " 0 " road of most polling controller gating MUX MUX3 directly was sent to cross bar switch with data flit.If when flit type code position was flit, most polling controllers allowed the backup of three stature sheets read in three registers (R4, R5, R6) respectively three continuous clock cycle.Step-by-step is carried out majority and is voted through ballot ruling comparator then, obtains the value after the final ruling.For example, suppose that the value among R4, R5, the R6 is respectively 10101010,11101010,10101000, the result of ballot ruling then is 10101010, namely has one among R5, the R6 respectively and has made mistakes.At last, " 1 " road of gating the 3rd MUX MUX3 allows the sheet after the ruling enter cross bar switch, further exchanges to next-hop node (router or receiving terminal network interface).
Fig. 3 and Fig. 5 are respectively No. three sampling controllers and a kind of implementation structure of most polling controller, according to the implementation method flow process of Fig. 4 and Fig. 6, No. three sampling controllers and most polling controller also can adopt the logical circuit of other versions to realize corresponding function.
Fig. 7 is method flow diagram of the present invention.This method has used hop to hop protection and end-to-end protection strategy to carry out the protection of different levels to needing data packets for transmission.Specifically may further comprise the steps:
Step 1: after the transmitting terminal network interface received the packet (packet) of transmitting terminal core (core) needs transmission, (1) carried out fault-tolerant encoding to this packet, encode optional cyclic redundancy code or hamming code etc.; (2) with the packet cutting be a plurality of data slice (data flit); (3) for packet adds the higher authorities' sheet (head flit), a sheet comprises the key messages such as route of whole packet; (4) send to the router solicitation that connects, and after transmission that data are temporary in order to end-to-end re-transmission.
Step 2: after router receives a hop router or transmitting terminal network interface transmission request; (1) be that a flit(judges the flit type according to the type code position among each flit as if what ask transmission); then carry out triplication redundancy protection at router, the guard method of adopting comprises: the majority ballot of crosstalking three samplings leading to errors, soft error possible in the first in first out buffer memory is carried out jointly at transmission line.Thereby realize the hop to hop protection of a sheet; (2) be data flit as if what ask transmission, then between bypass, walk around above-mentioned protection process in the router.
Step 3: after the receiving terminal network interface receives a hop router data packets for transmission, this packet is decoded, (1) if decoding detected error number within the error correcting capability scope of adopt coding, then sends the correct data after the error correction to the receiving terminal core; (2) if decoding detected error number has exceeded the error correcting capability of the coding that adopts, then ask transmitting terminal to retransmit this packet.Thereby realize the end-to-end protection of packet.
Table 1 is performance and the expense result of network-on-chip provided by the invention.The Mesh8x8 network topology is adopted in experiment, and wrong probability appears in every Bit data in network transmission process be 0.1%.
The performance of table 1 the inventive method and other method and the comparison of expense
As can be seen from Table 1, the average power consumption of the inventive method is only near half of hop to hop method, and average retardation has only end-to-end method half.Therefore, when guaranteeing same reliability, the power consumption of the inventive method and delay all reach the optimization effect.
Claims (4)
1. the network-on-chip data transmission device of a cascade protection, comprise network interface and router, described network interface comprises transmitting terminal network interface and receiving terminal network interface, it is characterized in that, be provided with in the described transmitting terminal network interface for the data coding unit that packet is carried out fault-tolerant encoding and the re-transmission buffer memory of the whole packet of storage in order to end-to-end re-transmission, described data coding unit output is connected with described re-transmission buffer memory input; Described router comprises cross bar switch and is used for a sheet of packet is carried out the head protection unit of hop to hop protection, the output of described head protection unit is connected with the cross bar switch input, and the output of described cross bar switch connects the input of next hop router or receiving terminal network interface; Be provided with in the described receiving terminal network interface for to the decoded packet data behind the coding and wrong number exceed institute adopts encode ask the data decode unit of end-to-end re-transmission during the fault-tolerant wrong number of energy.
2. the network-on-chip data transmission device of cascade protection according to claim 1 is characterized in that, described head protection unit comprises sampling module, first in first out buffer memory and most vote module three times:
Described three sampling modules comprise three registers, two MUX, No. three sampling controllers; Described three registers all are connected with first MUX, the clock signal of first register is clock signal chip, described clock signal chip inserts second register by the first little retardation element, described clock signal chip inserts the 3rd register by the first little retardation element, the second little retardation element successively, and described little retardation element is composed in series by two not gates; The type code position that is input as described clock signal chip, bag sheet of described No. three sampling controllers, the output of described No. three sampling controllers is connected with first MUX, second MUX; The packet of a last hop node is divided into three the tunnel, and first via data slice is imported second MUX into, and the second road sheet is sent in described first, second, third register, and the type code position of all bag sheets of Third Road is inserted in described No. three sampling controllers; The output of described second MUX is connected with described first in first out buffer memory; A wherein said last hop node is transmitting terminal network interface or router;
Described most vote module comprises three registers, vote ruling comparator, the 3rd MUX, a most polling controller; The packet that described first in first out buffer memory transmits is divided into three the tunnel: first via data slice is directly imported described the 3rd MUX into, and the second road sheet is sent into the 4th register, and described most polling controller is inserted in the type code position of all data slice of Third Road; The 5th register inserts between described the 4th register and the ballot ruling comparator, the 6th register inserts between described the 5th register and the ballot ruling comparator, the input clock signal of described the 4th register, the 5th register, the 6th register, most polling controllers is described clock signal chip, and the output of described the 4th register, the 5th register, the 6th register all links to each other with ballot ruling comparator; Described most polling controller is connected with described the 3rd MUX, and the enable signal of the output of described the 3rd MUX and described most polling controller outputs inserts cross bar switch.
3. utilize the network-on-chip data transmission device of claim 1 or 2 described cascade protections to the guard method of network-on-chip transfer of data, it is characterized in that this method is:
1) after the transmitting terminal network interface receives the packet that the transmitting terminal core need send, packet is carried out fault-tolerant encoding, and the packet cutting after will encoding is a plurality of data slice;
2) add a sheet that comprises whole packet routing iinformation for the packet behind the coding;
3) the transmitting terminal network interface sends the packet that adds the higher authorities' sheet to the next-hop node request, and after transmission finishes that packet is temporary, in order to end-to-end re-transmission;
4) after this node router receives hop node transmission request, judge whether the sheet of request transmission is a sheet, if enter 5); If not, then the data slice of request transmission directly is transferred to next-hop node through second MUX, first in first out buffer memory, the 3rd MUX, if next-hop node is the receiving terminal network interface, then jumps to 8);
5) three continuous clock cycles the sheet in three registers of three sampling modules of this node router is sent into the first in first out buffer memory respectively;
6) the most polling controllers of this node router will be stored in three registers that three parts of sheets in the first in first out buffer memory read in most vote module respectively three continuous clock cycle;
7) ballot ruling comparator carries out the majority ballot to the sheet step-by-step in three registers of most vote module, and the sheet after the ruling enters cross bar switch and further exchanges to next-hop node, thereby realizes the hop to hop protection of a sheet;
8) after the receiving terminal network interface receives a hop router data packets for transmission, this packet is decoded, if decoding detected error number then sends the correct data bag after the error correction to the receiving terminal core within the fault-tolerant ability scope of employing fault-tolerant encoding; If decoding detected error number has exceeded the fault-tolerant ability of used fault-tolerant encoding, then ask the transmitting terminal network interface to retransmit this packet, thereby realize the end-to-end protection of packet.
4. the cascade protection method of network-on-chip transfer of data according to claim 3 is characterized in that, in the described step 1), adopts cyclic redundancy code or hamming code that packet is carried out fault-tolerant encoding.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103984674A (en) * | 2014-05-15 | 2014-08-13 | 厦门大学 | Central controller used for wireless on-chip network communication and control method thereof |
| CN104092615A (en) * | 2014-06-10 | 2014-10-08 | 西安电子科技大学 | Network on chip with network coding function, network topology of the network on chip, and route algorithm of the network topology |
| CN105589768A (en) * | 2015-12-09 | 2016-05-18 | 中国航空工业集团公司西安航空计算技术研究所 | Self-healing fault-tolerant computer system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050243722A1 (en) * | 2004-04-30 | 2005-11-03 | Zhen Liu | Method and apparatus for group communication with end-to-end reliability |
| CN102497649A (en) * | 2011-12-09 | 2012-06-13 | 西安电子科技大学 | Satellite network route establishing method based on reliability assurance |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050243722A1 (en) * | 2004-04-30 | 2005-11-03 | Zhen Liu | Method and apparatus for group communication with end-to-end reliability |
| CN102497649A (en) * | 2011-12-09 | 2012-06-13 | 西安电子科技大学 | Satellite network route establishing method based on reliability assurance |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103984674A (en) * | 2014-05-15 | 2014-08-13 | 厦门大学 | Central controller used for wireless on-chip network communication and control method thereof |
| CN103984674B (en) * | 2014-05-15 | 2017-01-11 | 厦门大学 | Central controller used for wireless on-chip network communication and control method thereof |
| CN104092615A (en) * | 2014-06-10 | 2014-10-08 | 西安电子科技大学 | Network on chip with network coding function, network topology of the network on chip, and route algorithm of the network topology |
| CN105589768A (en) * | 2015-12-09 | 2016-05-18 | 中国航空工业集团公司西安航空计算技术研究所 | Self-healing fault-tolerant computer system |
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