CN103346853B - Master clock based on IEEE1588v2 protocol and generating method thereof - Google Patents
Master clock based on IEEE1588v2 protocol and generating method thereof Download PDFInfo
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- CN103346853B CN103346853B CN201310292010.2A CN201310292010A CN103346853B CN 103346853 B CN103346853 B CN 103346853B CN 201310292010 A CN201310292010 A CN 201310292010A CN 103346853 B CN103346853 B CN 103346853B
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Abstract
The invention provides a master clock based on an IEEE1588v2 protocol. The master clock is composed of a software module and a hardware module, wherein the software module comprises a processor, and the hardware module comprises a message classifying module, a message combining module, a message receiving and sending module and a message configuration table memorizer. A software and hardware combining mode is adopted in the master clock, the advantage of hardware in the aspect of time accuracy and the advantage of software in the aspect of protocol processing are brought into full play, therefore, the load capacity of the IEEE1588v2 master clock is improved, a slave clock can be dynamically inserted or deleted or changed, and operation is convenient to conduct. In addition, the hardware can rapidly respond to the dynamic change and accurately control time through an internal high-speed clock, therefore, message sending intervals can be accurately controlled, and message time scale accuracy can be improved.
Description
Technical field
The present invention relates to master clock field, be specifically related to a kind of master clock device based on IEEE1588v2 agreement and master clock production method.
Background technology
At present, traditional IEEE1588v2 master clock all adopts software simulating, hardware be only responsible for beats timestamp, when load is more from clock, occupy a large amount of processor time and the load capacity of master clock be subject to processing device performance restriction be difficult to raising.
The load capacity how improving master clock becomes one of key technical problem that design IEEE1588v2 master clock will solve.
Summary of the invention
In view of this, the invention provides a kind of master clock based on IEEE1588v2 agreement and production method thereof, the mode combined by software and hardware, improve the load capacity of IEEE1588v2 master clock.
The invention provides a kind of master clock device based on IEEE1588v2 agreement, be made up of software module and hardware module, described software module comprises processor, and described hardware module comprises message classification module, message merges module, packet sending and receiving module and message allocation list memory, wherein
The message received for receiving message, and is classified by described message classification module, and according to type of message, message is sent to processor or packet sending and receiving module;
The message that described processor is used for according to receiving upgrades message allocation list memory, and merges module transmission message to message;
Described packet sending and receiving module is for receiving message and being sent to by response message message to merge module, and message allocation list memory is scanned, according to scanning result, Sync message and Follow_up message are sent to message to merge module, or only Sync message is sent to merging module;
Described message allocation list memory is for storing the message allocation list comprising first area and second area;
Described message merges module and is used for the message of reception to carry out merging and sending.
Preferably, described processor is also for carrying out enable to first area or second area and noticing enable result.
Preferably, described packet sending and receiving module only scans the region be enabled, and notices the region of scanning.
Preferably, described processor only upgrades the region be not under scanning mode.
Preferably, described message allocation list comprises multiple dispensing unit, and each dispensing unit stores a relevant information from clock.
Preferably, described packet sending and receiving module also for according to high-frequency clock generation time sheet, and starts at each timeslice head and scans region, completes single pass in a timeslice.
Preferably, described type of message comprises A type, Type B and C type, and wherein, described A type message is non-IEEE1588v2 message; Described Type B message is the Announce message of IEEE1588v2, Management message and Signaling message; Described C type message is the IEEE1588v2 message except Announce message, Management message and Signaling message; Wherein,
Category-A and category-B message are sent to processor by described message classification module; C class message is sent to packet sending and receiving module.
The present invention additionally provides the method for a kind of generation based on the master clock of IEEE1588v2 agreement simultaneously, and described method comprises the steps:
Step one a: region of the enable message allocation list of processor, the announcement that works of going forward side by side;
Step 2: come interim at timeslice head, the region be enabled in packet sending and receiving module scans message allocation list, the announcement that works of going forward side by side;
Step 3: according to scanning result, packet sending and receiving module maybe sends to message to merge module by sending to from the Sync message of clock by sending to from the Sync message of clock and Follow_up message;
Step 4: message merges module to carry out framing by the message received and sends to corresponding from clock.
Preferably, showing of receiving that message classification module sends from the message of the number of clock or attribute change time, processor upgrades the region be not under scanning mode in message allocation list.
Preferably, described message allocation list comprises multiple dispensing unit, and each dispensing unit stores a relevant information from clock.
Preferably, described processor is enable first area and second area alternately, dynamically deletes/inserts or change from clock.
As shown from the above technical solution, a kind of master clock based on IEEE1588v2 agreement of the present invention and production method thereof, by adopting the mode of software and hardware combining, the advantage of hardware in time precision and the advantage of software in protocol processes can be given full play to, thus improve the load capacity of IEEE1588v2 master clock; And can dynamic insertion/deletion or change from clock, easy to operate; In addition, because hardware can respond this dynamic change fast, thus accurately can control message transmission interval, improve message markers accuracy.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skills, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation of a kind of master clock device based on IEEE1588v2 agreement that Fig. 1 provides for one embodiment of the invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, clear, complete description is carried out to the technical scheme in the embodiment of the present invention, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making creative work, all belongs to the scope of protection of the invention.
A kind of master clock device based on IEEE1588v2 agreement that one embodiment of the invention provides, be made up of software module and hardware module, described software module comprises processor 1, described hardware module comprises message classification module 2, message merges module 3, packet sending and receiving module 4 and message allocation list memory 5, wherein
The message received for receiving message, and is classified by described message classification module 2, and according to type of message, message is sent to processor 1 or packet sending and receiving module 4;
Described processor 1 for upgrading the message allocation list in message allocation list memory 5 according to the message received, and sends message to message merging module 3;
Described packet sending and receiving module 4 is for receiving message and being sent to by response message message to merge module 3, and message allocation list memory 5 is scanned, according to scanning result, Sync message and Follow_up message are sent to message to merge module 3, or only sent to by Sync message message to merge module 3;
Described message allocation list memory 5 is for storing the message allocation list comprising first area and second area;
Wherein, described message allocation list is configured dynamically by software, can realize the information interaction between software and hardware.Message allocation list is made up of multiple tactic dispensing unit, and each dispensing unit comprises the relevant information from clock that needs master clock time service.Table one gives the definition of dispensing unit:
Table one: the definition of dispensing unit
The implication of each field of dispensing unit is as follows:
(1) CONTROL: describe this group configuration unit controls information, comprises dispensing unit enable switch, sends type of message, message transmission frequency etc., 2 bytes;
(2) DES_MAC: the target MAC (Media Access Control) address of message, 6 bytes;
(3) DES_IP: the object IP address of message, IPv4 agreement gets low 4 bytes, and IPv6 agreement gets whole 16 bytes;
(4) DES_UDP_PORT: the UDP destination interface of message, 2 bytes.
Message allocation list synchronization can load 0 ~ N number of from clock, load from the number N of clock only by the restriction of software processing capability and hardware resource;
In message allocation list, the number of effective dispensing unit and information by dynamic update of software, forever can not taken from clock by some;
Because software and hardware can conduct interviews to message allocation list, in order to avoid access conflict, message allocation list comprises two panels independent, equal-sized region mutually, i.e. first area and second area, by the management of software, software and hardware alternate access two regions, any moment software and hardware all can not access same region simultaneously.
After device starts, hardware ceaselessly scans message allocation list, checks each dispensing unit one by one, has message to need to start transmission flow immediately when sending when being checked through dispensing unit.
Described message merges module 3 for being carried out merging and sending by the message of reception.
Preferably, described processor 1 is also for carrying out enable to first area or second area and noticing enable result.
Preferably, described packet sending and receiving module 4 only scans the region be enabled, and notices the region of scanning.
Preferably, described processor 1 only upgrades the region be not under scanning mode.
Preferably, described message allocation list comprises multiple dispensing unit, and each dispensing unit stores a relevant information from clock.
Preferably, described packet sending and receiving module 4 also for according to high-frequency clock generation time sheet, and starts at each timeslice head and scans region, completes single pass in a timeslice.The least unit of timeslice is the minimum interval that IEEE1588v2 message sends.The scanning moment of message allocation list is strictly defined---only start scanning at the head of timeslice, thus the transmission interval of message has very high precision and the uniformity; When having detected that message sends, start framing module immediately, directly the message of the legal form of composition sends.All completed by hardware because message constructs and beats timestamp, so the transmitting efficiency of message is high, message time stamp precision is high.
Preferably, described type of message comprises A type, Type B and C type, and wherein, described A type message is non-IEEE1588v2 message; Described Type B message is the Announce message of IEEE1588v2, Management message and Signaling message; Described C type message is the IEEE1588v2 message except Announce message, Management message and Signaling message; Wherein,
Category-A and category-B message are sent to processor by described message classification module; C class message is sent to packet sending and receiving module.
The present invention additionally provides the method for a kind of generation based on the master clock of IEEE1588v2 agreement simultaneously, and described method comprises the steps:
Step one a: region of the enable message allocation list of processor, the announcement that works of going forward side by side;
Step 2: come interim at timeslice head, the region be enabled in packet sending and receiving module scans message allocation list, the announcement that works of going forward side by side;
Step 3: according to scanning result, packet sending and receiving module maybe sends to message to merge module by sending to from the Sync message of clock by sending to from the Sync message of clock and Follow_up message;
Step 4: message merges module to carry out framing by the message received and sends to corresponding from clock.
Preferably, showing of receiving that message classification module sends from the message of the number of clock or attribute change time, processor upgrades the region be not under scanning mode in message allocation list.
Preferably, described message allocation list comprises multiple dispensing unit, and each dispensing unit stores a relevant information from clock.
As shown from the above technical solution, a kind of master clock based on IEEE1588v2 agreement of the present invention and production method thereof, by adopting the mode of software and hardware combining, the advantage of hardware in time precision and the advantage of software in protocol processes can be given full play to, thus improve the load capacity of IEEE1588v2 master clock; And can dynamic insertion/deletion or change from clock, easy to operate; In addition, this dynamic change can be responded fast due to hardware and inner high speed clock can be adopted accurately to control the time, thus accurately can control message transmission interval, improve message markers accuracy.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or equivalent replacement is carried out to wherein portion of techniques feature, and these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (1)
1., based on a master clock device for IEEE1588v2 agreement, be made up of software module and hardware module, it is characterized in that, described software module comprises processor, described hardware module comprises message classification module, message merges module, packet sending and receiving module and message allocation list memory, wherein
The message received for receiving message, and is classified by described message classification module, and according to type of message, message is sent to processor or packet sending and receiving module;
The message that described processor is used for according to receiving upgrades message allocation list memory, and merges module transmission message to message; Described processor is also for carrying out enable to first area or second area and noticing enable result;
Described packet sending and receiving module is for receiving message and being sent to by response message message to merge module, and message allocation list memory is scanned, according to scanning result, Sync message and Follow_up message are sent to message to merge module, or only Sync message is sent to merging module;
Described message allocation list memory is for storing the message allocation list comprising first area and second area;
Described message merges module and is used for the message of reception to carry out merging and sending.
2. master clock device according to claim 1, is characterized in that, described packet sending and receiving module only scans the region be enabled, and notices the region of scanning.
3. master clock device according to claim 2, is characterized in that, described processor only upgrades the region be not under scanning mode.
4. master clock device according to claim 3, is characterized in that, described message allocation list comprises multiple dispensing unit, and each dispensing unit stores a relevant information from clock.
5. master clock device according to claim 4, is characterized in that, described packet sending and receiving module also for according to high-frequency clock generation time sheet, and starts at each timeslice head and scans region, completes single pass in a timeslice.
6. master clock device according to claim 5, is characterized in that, described type of message comprises A type, Type B and C type, and wherein, described A type message is non-IEEE1588v2 message; Described Type B message is the Announce message of IEEE1588v2, Management message and Signaling message; Described C type message is the IEEE1588v2 message except Announce message, Management message and Signaling message; Wherein,
Category-A and category-B message are sent to processor by described message classification module; C class message is sent to packet sending and receiving module.
7. produce the method based on the master clock of IEEE1588v2 agreement, it is characterized in that, described method comprises the steps:
Step one a: region of the enable message allocation list of processor, the announcement that works of going forward side by side;
Step 2: come interim at timeslice head, the region be enabled in packet sending and receiving module scans message allocation list, the announcement that works of going forward side by side;
Step 3: according to scanning result, packet sending and receiving module maybe sends to message to merge module by sending to from the Sync message of clock by sending to from the Sync message of clock and Follow_up message;
Step 4: message merges module to carry out framing by the message received and sends to corresponding from clock.
8. generation according to claim 7 is based on the method for the master clock of IEEE1588v2 agreement, it is characterized in that, showing of receiving that message classification module sends from the message of the number of clock or attribute change time, processor upgrades the region be not under scanning mode in message allocation list.
9. generation according to claim 7 is based on the method for the master clock of IEEE1588v2 agreement, it is characterized in that, described message allocation list comprises multiple dispensing unit, and each dispensing unit stores a relevant information from clock.
10. generation according to claim 7 is based on the method for the master clock of IEEE1588v2 agreement, it is characterized in that, described processor is enable first area and second area alternately, dynamically deletes/inserts or change from clock.
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| CN101577600A (en) * | 2008-05-09 | 2009-11-11 | 华为技术有限公司 | Time synchronization method, system and optical network equipment for passive optical network system |
| CN101834685A (en) * | 2010-04-16 | 2010-09-15 | 华为技术有限公司 | 1588 message extracting and processing method and equipment |
| CN103138887A (en) * | 2011-12-05 | 2013-06-05 | 中兴通讯股份有限公司 | Processing method of 1588 event messages and processing method of 1588 event messages |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101577600A (en) * | 2008-05-09 | 2009-11-11 | 华为技术有限公司 | Time synchronization method, system and optical network equipment for passive optical network system |
| CN101834685A (en) * | 2010-04-16 | 2010-09-15 | 华为技术有限公司 | 1588 message extracting and processing method and equipment |
| CN103138887A (en) * | 2011-12-05 | 2013-06-05 | 中兴通讯股份有限公司 | Processing method of 1588 event messages and processing method of 1588 event messages |
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Inventor after: Wang Haigang Inventor after: Xie Min Inventor after: Wen Junliang Inventor after: Yuan Chengwei Inventor after: Deng Zheng Inventor after: Meng Yang Inventor after: Gao Baohong Inventor after: Wang Tao Inventor before: Yuan Chengwei Inventor before: Deng Zheng Inventor before: Meng Yang Inventor before: Gao Baohong Inventor before: Wang Tao |
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Effective date of registration: 20170216 Address after: Mount Huangshan road in Baohe District of Hefei city of Anhui Province, No. 9 230000 Patentee after: State Grid Anhui Electric Power Company Patentee after: Wuhan Zhongyuan Huadian Science & Technology Co., Ltd. Address before: The Chinese science and Technology Park of East Lake Development Zone six road 430223 Hubei city of Wuhan province No. 6 Patentee before: Wuhan Zhongyuan Huadian Science & Technology Co., Ltd. |