CN103326968B - The implementation method of soft-decision metrics is generated in Turbo-STBC system - Google Patents

Abstract

The invention provides a kind of implementation method generating LLR soft-decision metrics in the Turbo-STBC system of 2 transmitting antenna 2 reception antennas formations.The method realizes by designing LLR maker module on FPGA, in Turbo-STBC cascade system, LLR maker is by the baseband signal of receiving terminal by inputting LLR internalarithmetic after STBC decoders decode, and the LLR soft-decision metrics of generation carries out Turbo decoding as the input of follow-up Turbo soft decision decoder.When carrying out the design of internal arithmetic module, fully adopting concurrent operation thought, improve throughput of system.Adopt hardware multiplexing technology in the design of wherein STBC decoder, while guarantee arithmetic unit functional realiey, save the consumption of arithmetic unit to hardware resource.The design of LLR arithmetic unit have employed simple algorithm, compared with traditional algorithm, reduces the hard-wired complexity of arithmetic unit.

Description

The implementation method of soft-decision metrics is generated in Turbo-STBC system

Technical field

The present invention relates to wireless communication field, and relate more specifically to a kind of Turbo-STBC (SpaceTimeBlockCode, Space-Time Block Coding) generate the implementation method of LLR (LoglikelihoodRatio, log-likelihood ratio) soft-decision metrics in system.

Background technology

Turbo code is as a kind of channel coding schemes of programmable single-chip system shannon limit, be widely used in wireless communication system with the performance of its excellence, convolution code and random interleaver organically combine by Turbo code, achieve random coded, decoder carrys out near-maximum-likelihood decoding by adopting soft-output coding iterative decoding, can obtain higher decoded gain.

STBC is a kind of MIMO (MultipleInputMultipleOutput, multiple-input and multiple-output) the conventional transmitting diversity coded system of multiaerial system, coding and decoding mode is simple, and during with the outer code concatenated had compared with unitary Item gain, the performance of cascade system will improve a lot.In Turbo-STBC cascade system, data after modulation are carried out STBC coding again and send by transmitting terminal after Turbo encoder encodes, receiving terminal adopts cascade decoding that two kinds can be made to encode and organically combines, and makes system obtain channel coding gain and transmitting diversity gain simultaneously.

But, conventional STBC decoding algorithm is that one exports decoding firmly, what STBC decoder exported is the Bit data recovered after judgement, Turbo soft-output coding iterative decoding can not be used for, therefore, in Turbo-STBC cascade system, the algorithm of the LLR soft-decision metrics that the modulation symbol how to be recovered by STBC receiver transforms required for Turbo decoder just seems particularly crucial.Tradition LLR generating algorithm generally based on the Euclidean distance between receiving symbol and standard constellation point, and needs carry out traversal computing to all constellation point and compare, and algorithm is complicated, and operand is large, is unfavorable for hardware implementing.

Summary of the invention

The invention provides a kind of implementation method generating LLR soft-decision metrics in the Turbo-STBC cascade system of 2 transmitting antenna 2 reception antennas formations.The method is based on FPGA (FieldProgrammableGateArray, field programmable gate array) Platform Designing realization, comprise STBC decoder module and LLR soft-decision metrics generation module, realize STBC decoding and LLR computing respectively, and adopt simple algorithm when carrying out the design of LLR generation module, solve the problem that traditional LLR hardware algorithm implementation complexity is high.

Realize concrete technological means of the present invention to have:

1, the implementation method of soft-decision metrics is generated in a kind of Turbo-STBC Space-Time Block Code, it is characterized in that: the method realizes by designing receiving terminal LLR log-likelihood ratio maker module on FPGA hardware platform, wherein receiving terminal LLR maker module is by channel estimating input buffer, base band data input buffer, noise variance input buffer, STBC decoder, LLR arithmetic unit, output state is formed;

1.1. channel estimating input buffer, base band data input buffer, noise variance input buffer, respectively by its inside input control device, the channel parameter of input LLR maker module, receiving terminal baseband signal and noise variance signal are carried out buffer memory, and input respective inside FIFO (FirstInFirstOut, first-in first-out) buffer unit;

1.2.STBC decoder module is used for the realization of STBC combination algorithm, and this module reads in channel parameter and receiving terminal baseband signal from channel estimating input buffer, base band data input buffer, and carries out STBC associative operation by internal arithmetic circuit;

1.3.LLR operator block is used for the realization of LLR soft-decision metrics generating algorithm, noise variance signal in the output signal of STBC decoder and noise variance input buffer is carried out LLR computing by this module, operation result is sent into output state and exports as final result.

2. in aforementioned 1.2, STBC decoder is inner by arithmetic element multiplex controller and reusable real part computing module, reusable imaginary-part operation module composition, two reusable computing modules can carry out the switching of operational pattern according to the change of the control signal low and high level of arithmetic element multiplex controller input, when carrying out STBC associative operation to adjacent baseband signal, realize the time division multiplexing of computing circuit.

3. in aforementioned 1.3, LLR arithmetic unit adopts LLR shortcut calculation, this algorithm simplifies traditional algorithm further for QPSK (QuadraturePhaseShiftKeying, quarternary phase-shift keying (QPSK)) modulation system, and in shortcut calculation, the LLR value of each modulation bit is expressed as:

$LLR\left(b_0\right)=-Im\left(s_i\right)\·\frac{2}{{\mathrm{\σ}}^2}$

$LLR\left(b_1\right)=-\mathrm{Re}\left(s_i\right)\·\frac{2}{{\mathrm{\σ}}^2}$

B in formula ₀, b ₁for modulation bit, s _ifor receiving terminal baseband signal, Im for getting real part computing, Re for getting imaginary-part operation, σ ²for channel noise variance.

4. in aforementioned 1.3, LLR arithmetic unit is inner to be made up of input data buffer storage unit and divider, computing modulation bit b while of adopting two parallel links ₀, b ₁corresponding LLR value; Input data buffer storage unit adopts ping-pong operation mode to input divider by after input data buffer storage, in ping-pong operation, input selection controller is by while data Input Data Buffer, carry out negate to corresponding data and add 1 in data buffer, what achieve data asks complement arithmetic.

5. in aforementioned 2, reusable computing module inside adopts concurrent operation structure, be divided into 4 grades of arithmetic units, wherein reusable real part computing module the 1st grade of arithmetic unit is made up of 8 multipliers, 2nd grade of arithmetic unit is made up of 4 controlled adder-subtracters of pattern, 3rd level arithmetic unit is made up of 2 adders, and the 4th grade of arithmetic unit is made up of 1 adder.The front 3 grades of arithmetic units of reusable imaginary-part operation module are identical with real part computing module, and the 4th grade of arithmetic unit is made up of 1 subtracter.

Accompanying drawing explanation

Fig. 1 is LLR maker hardware module block diagram

Fig. 2 is base band data input buffer hardware structure diagram

Fig. 3 is STBC decoder hardware structure chart

Fig. 4 arithmetic element multiplex controller internal state machine state transition diagram

Fig. 5 is the QPSK modulation constellation of gray encoding

Fig. 6 LLR arithmetic unit hardware structure diagram

Embodiment

Below in conjunction with Figure of description, embodiments of the invention are described further:

In the Turbo-STBC cascade system that 2 transmitting antenna 2 reception antennas are formed, data input STBC coding module after Turbo coding and modulation, and STBC coding module is by two continuous modulation symbol s ₀, s ₁carry out orthogonal coding process to generate sending metrix:

$S=\left[\begin{array}{cc}{s}_0& -{s_1}^{*}\\ s_1& {s_0}^{*}\end{array}\right]---\left(1\right)$

In formula (1), " * " represents conjugation.

The channel parameter matrix that channel estimating obtains is defined as:

$H=\left[\begin{array}{cc}{h}_1& h_2\\ h_{21}& h_{22}\end{array}\right]---\left(2\right)$

The baseband receiving signals matrix that receiving terminal is corresponding is:

$R=\left[\begin{array}{cc}{r}_{11}& r_{12}\\ r_{21}& r_{22}\end{array}\right]---\left(3\right)$

Receiving end signal is converted into LLR soft-decision metrics after entering receiving terminal LLR maker module, and final Turbo decoder of sending into carries out decoding.

Figure 1 shows that LLR maker hardware module block diagram, mainly comprise 4 outside ports and 6 internal modules, the data in the inputoutput data of each outside port and each internal module all represent with complement form.Wherein, outside port mainly comprises 3 data-in ports and 1 LLR output port, 3 input ports comprise: channel estimating input port, be mainly used in the input of channel parameter, this port comprises two-way complex signal, the first row of difference input channel parameter matrix and the second row, and every road complex signal is made up of I, Q data, wherein data I represents complex signal real part, and data Q represents complex signal imaginary part; Baseband signal input port, is mainly used in the input of receiving terminal baseband signal, and this port comprises two-way complex data, and input the first row and second row of Baseband Receiver matrix respectively, every circuit-switched data is made up of I, Q two-way; Noise variance input port, is mainly used to input noise variance data, and its input data format is single channel real data.LLR output port, for exporting LLR value corresponding to each modulation bit, carries out decoding to be supplied to Turbo decoder.Internal module mainly comprises channel estimating input buffer 101, base band data input buffer 102, noise variance input buffer 103, STBC decoder 104, LLR arithmetic unit 105, output state 106.During work, the baseband signal of input port input and channel parameter enter STBC decoder through respective independently input buffer and carry out STBC associative operation, to remove channel, also tentatively raw modulation symbols is recovered to the non-linear effects sending symbol, enter the LLR soft-decision metrics value that LLR computing module calculates each modulation bit afterwards again, the LLR value of last gained is sent into Turbo decoder by output state and is carried out decoding.

Fig. 2 gives the hardware structure diagram of base band data input buffer, input control device is first by the input of handshake and upper level module settling signal, shown in receiving matrix in (3), input buffer the 1st clock cycle by baseband signal r corresponding for two reception antennas ₁₁, r ₂₁buffer memory, the 2nd clock cycle by baseband signal r ₁₂, r ₂₂buffer memory, and group Received signal strength of two in adjacent time is carried out serioparallel exchange, the parallel data r after conversion ₁₁, r ₁₂, r ₂₁, r ₂₂send into FIFO buffer, to ensure that STBC decoder can complete reading in of whole element in receiving matrix R to the read operation of the data in FIFO.

The structure of channel estimating input buffer and noise variance input buffer and function and base band data input buffer similar, mainly complete the channel transfer matrices of input and the buffer memory of channel noise variance and serioparallel exchange function.

In the present invention, STBC decoder have employed classical STBC combination algorithm, and its expression formula is:

${\tilde{s}}_0=\underset{j=1}{\overset{2}{\Σ}}\[{\left(h_{1,j}\right)}^{*}\·r_{1,j}+h_{2,j}.{\left(r_{2,j}\right)}^{*}\]---\left(4\right)$

${\tilde{s}}_1=\underset{j=1}{\overset{2}{\Σ}}\[{\left(h_{2,j}\right)}^{*}\·r_{1,j}-h_{1,j}.{\left(r_{2,j}\right)}^{*}\]---\left(5\right)$

H and r in formula (4) and (5) represents the element in channel transfer matrices and baseband receiving signals matrix respectively, represent STBC decoder output signal.

When FPGA realizes, the real arithmetic of formula (4), (5) is divided into real part computing and imaginary-part operation, formula (4) is carried out real part and imaginary part expansion, shown in (6), (7), formula (5) is carried out real part and imaginary part expansion, shown in (8), (9):

$\begin{array}{c}\mathrm{Re}\left({\tilde{s}}_0\right)=\mathrm{Re}\left(h_{11}\right)\·\mathrm{Re}\left(r_{11}\right)+\mathrm{Re}\left(h_{21}\right)\·\mathrm{Re}\left(r_{21}\right)\mathrm{Re}\left(h_{12}\right)\·\mathrm{Re}\left(r_{12}\right)+\mathrm{Re}\left(h_{22}\right)\·\mathrm{Re}\left(r_{22}\right)\\ +\mathrm{Im}\left(h_{11}\right)\·\mathrm{Im}\left(r_{11}\right)+\mathrm{Im}\left(h_{21}\right)\·\mathrm{Im}\left(r_{21}\right)+\mathrm{Im}\left(h_{12}\right)\·\mathrm{Im}\left(r_{12}\right)+\mathrm{Im}\left(h_{22}\right)\·\mathrm{Im}\left(r_{22}\right)\end{array}---\left(6\right)$

$\begin{array}{c}\mathrm{Im}\left({\tilde{s}}_0\right)=\mathrm{Re}\left(h_{11}\right)\·\mathrm{Im}\left(r_{11}\right)-\mathrm{Re}\left(h_{21}\right)\·\mathrm{Im}\left(r_{21}\right)+\mathrm{Re}\left(h_{12}\right)\·\mathrm{Im}\left(r_{12}\right)-\mathrm{Re}\left(h_{22}\right)\·\mathrm{Im}\left(r_{22}\right)\\ +\left(\mathrm{Im}\right(h_{11})\·\mathrm{Re}\left(r_{11}\right)-\mathrm{Im}\left(h_{21}\right)\·\mathrm{Re}\left(r_{21}\right)+\mathrm{Im}\left(h_{12}\right)\·\mathrm{Re}\left(r_{12}\right)-\mathrm{Im}\left(h_{22}\right)\·\mathrm{Re}\left(r_{22}\right))\end{array}---\left(7\right)$

$\begin{array}{c}\mathrm{Re}\left({\tilde{s}}_1\right)=\mathrm{Re}\left(h_{21}\right)\·\mathrm{Re}\left(r_{11}\right)-\mathrm{Re}\left(h_{11}\right)\·\mathrm{Re}\left(r_{21}\right)\mathrm{Re}\left(h_{22}\right)\·\mathrm{Re}\left(r_{12}\right)-\mathrm{Re}\left(h_{12}\right)\·\mathrm{Re}\left(r_{22}\right)\\ +\mathrm{Im}\left(h_{21}\right)\·\mathrm{Im}\left(r_{11}\right)-\mathrm{Im}\left(h_{11}\right)\·\mathrm{Im}\left(r_{21}\right)+\mathrm{Im}\left(h_{22}\right)\·\mathrm{Im}\left(r_{12}\right)-\mathrm{Im}\left(h_{12}\right)\·\mathrm{Im}\left(r_{22}\right)\end{array}---\left(8\right)$

$\begin{array}{c}\mathrm{Im}\left({\tilde{s}}_1\right)=\mathrm{Re}\left(h_{21}\right)\·\mathrm{Im}\left(r_{11}\right)+\mathrm{Re}\left(h_{11}\right)\·\mathrm{Im}\left(r_{21}\right)+\mathrm{Re}\left(h_{22}\right)\·\mathrm{Im}\left(r_{12}\right)+\mathrm{Re}\left(h_{12}\right)\·\mathrm{Im}\left(r_{22}\right)\\ +\left(\mathrm{Im}\right(h_{21})\·\mathrm{Re}\left(r_{11}\right)+\mathrm{Im}\left(h_{11}\right)\·\mathrm{Re}\left(r_{21}\right)+\mathrm{Im}\left(h_{22}\right)\·\mathrm{Re}\left(r_{12}\right)-\mathrm{Im}\left(h_{12}\right)\·\mathrm{Re}\left(r_{22}\right))\end{array}---\left(9\right)$

By contrast (6) and formula (8), formula (7) and formula (9), known with real part, imaginary-part operation expression formula similar, only have any different, therefore in the design carrying out STBC decoder, adopt hardware multiplexing thought on part plus and minus calculation, and it is right to be completed by same module with computing.

The hardware configuration of STBC decoder as shown in Figure 3, in formula (6), (8) with the computing of real part, is completed by reusable real part computing module 302, in formula (7), formula (9) with the computing of imaginary part, is completed by reusable imaginary-part operation module 303.By changing the mode of operation of internal arithmetic device under the real part operational pattern control signal 308 that above-mentioned two modules export at arithmetic element multiplex controller 301, the control of imaginary-part operation mode control signal 309, calculate respectively within two continuous print clock cycle in a time multiplexed manner

Arithmetic element multiplex controller has 3 kinds of operating states, controlled by the state machine of its inside, the state migration procedure of state machine is as shown in Figure 4: state 1 is initial state, this stage arithmetic element multiplex controller reads base band data and channel parameter from base band data input buffer, channel estimating input buffer, complete data to read in rear arithmetic element multiplex controller and get the hang of 2, otherwise rest on state 1, until complete desired data buffer memory; In state 2, arithmetic element multiplex controller is according in formula (6) and formula (7) operation expression, by the corresponded manner shown in Fig. 3, according to the order of sequence by Re (h ₁₁), Re (r ₁₁), Re (h ₂₁), Re (r ₂₁), Re (h ₁₂), Re (r ₁₂), Re (h ₂₂), Re (r ₂₂), Im (h ₁₁), Im (r ₁₁), Im (h ₂₁), Im (r ₂₁), Im (h ₁₂), Im (r ₁₂), Im (h ₂₂), Im (r ₂₂) export each input port of reusable real part computing module 302 to, by Re (h ₁₁), Im (r ₁₁), Re (h ₂₁), Im (r ₂₁), Re (h ₁₂), Im (r ₁₂), Re (h ₂₂), Im (r ₂₂), Im (h ₁₁), Re (r ₁₁), Im (h ₂₁), Re (r ₂₁), Im (h ₁₂), Re (r ₁₂), Im (h ₂₂), Re (r ₂₂) export each input port of reusable imaginary-part operation module 303 to, simultaneously with low level output real part operational pattern control signal 308, with high level output imaginary-part operation mode control signal 309, control two arithmetic elements and be operated in computing pattern under, after completing aforesaid operations, state machine gets the hang of 3, otherwise arithmetic element multiplexer rests on state 2 until complete all operations; In state 3, controller is according in formula (8) and formula (9) operation expression, by the corresponded manner shown in Fig. 3, according to the order of sequence by Re (h ₂₁), Re (r ₁₁), Re (h ₁₁), Re (r ₂₁), Re (h ₂₂), Re (r ₁₂), Re (h ₁₂), Re (r ₂₂), Im (h ₂₁), Im (r ₁₁), Im (h ₁₁), Im (r ₂₁), Im (h ₂₂), Im (r ₁₂), Im (h ₁₂), Im (r ₂₂) export reusable real part computing mould 302 pieces of each input ports to, by Re (h ₂₁), Im (r ₁₁), Re (h ₁₁), Im (r ₂₁), Re (r ₂₁), Im (h ₂₂), Re (h ₁₂), Im (r ₂₂), Im (h ₂₁), Re (r ₁₁), Im (h ₁₁), Re (r ₂₁), Im (h ₂₂), Re (r ₁₂), Im (h ₁₂), Re (r ₂₂) export each input port of reusable imaginary-part operation module 303 to, and with high level output real part operational pattern control signal 308, low level output imaginary-part operation mode control signal 309, to control reusable real part computing module 302 and reusable imaginary-part operation module 303 is operated in computing pattern under, after completing aforesaid operations, arithmetic element multiplex controller completes a periodic duty, and state machine reenters state 1, prepare to carry out the computing of lower group of data, otherwise arithmetic element multiplexer rests on state 3, until complete all operations.

In Fig. 3, reusable real part computing module 302 inside adopts concurrent operation structure and pipeline processing mode, is made up of: the 1st grade of arithmetic unit 304 is 8 multipliers, completes 4 grades of arithmetic units multiply operation needed for real part computing.2nd grade of arithmetic unit 305 is 4 controlled adder-subtracters of pattern, the low and high level that this adder-subtracter inputs by real part operational pattern control signal 308 controls its mode of operation, when control signal is low level, arithmetic unit performs add operation, and when control signal is high level, arithmetic unit performs subtraction.Reusable real part operational pattern control signal 308 will be input to controlled adder-subtracter again after a delay unit, to ensure the output data syn-chronization of this control signal and the 1st grade of multiplier.3rd level arithmetic unit 306 is become by 3 adder stage joint groups with the 4th grade of arithmetic unit 307, is responsible for the Output rusults of arithmetic unit before to carry out sum operation.Reusable imaginary-part operation module 303 is substantially identical with reusable real part computing module 302 structure, and being distinguished as reusable imaginary-part operation module the 4th grade of arithmetic unit is subtracter.

The output of STBC decoder enter LLR arithmetic unit subsequently and carry out LLR computing, because traditional LLR generating algorithm computational complexity is high, be unfavorable for FPGA hardware implementing, therefore the present invention have employed a kind of simple algorithm in the design to LLR arithmetic unit, the LLR of each modulation bit of QPSK modulation system shown in Fig. 5 is defined as such as formula shown in (10), (11) by this algorithm, under QPSK modulation system, corresponding two the modulation bit b of each modulation symbol ₀, b ₁, therefore, each modulation symbol can calculate two LLR soft-decision metrics.

$LLR\left(b_0\right)=-2Im\left(Z_i\right)\·\frac{|H_s{|}^2}{{\mathrm{\σ}}^2}---\left(10\right)$

$LLR\left(b_1\right)=-2\mathrm{Re}\left(Z_i\right)\·\frac{|H_s{|}^2}{{\mathrm{\σ}}^2}---\left(11\right)$

Z in formula (10), (11) _ifor the symbol after equilibrium, | H _s| ²for channel gain amplitude square and, σ ²for channel noise variance.The output of STBC decoder and Z _ibetween relation can be expressed as, then (10), (11) formula can be reduced to:

$LLR\left(b_0\right)=-Im\left(s_i\right)\·\frac{2}{{\mathrm{\σ}}^2}---\left(12\right)$

$LLR\left(b_1\right)=-\mathrm{Re}\left(s_i\right)\·\frac{2}{{\mathrm{\σ}}^2}---\left(13\right)$

The LLR arithmetic unit hardware structure diagram gone out according to formula (12), LLR algorithm design of describing in (13) is as shown in figure (6), and in order to improve the throughput of module, this module adopts two parallel links to calculate b respectively ₁, b ₀corresponding LLR soft-decision metrics, each link have employed ping-pong operation when carrying out input data buffer storage.Input selection controller in Fig. 6 in input-buffer unit, 4 data buffers, 2 output selection controls constitute two groups of ping-pong operation unit walked abreast, while carrying out ping-pong operation, corresponding data is carried out negate by input selection controller, and add-one operation is carried out by adder in data buffer, try to achieve complement code, operation result is buffer memory in adder.Two continuous datas that during work, STBC decoder is exported by the handshake with upper level intermodule by input selection controller and corresponding noise variance data σ in noise variance input buffer _i ², σ _i+1 ²temporary.The 1st clock cycle after completing data temporary storage, input data will negate and σ _i ²stored in data buffer 1, will negate and σ _i ²stored in data buffer 3; Will at the 2nd clock cycle data input selection controller negate and σ _i+1 ²stored in data buffer 2, will negate and σ _i+1 ²stored in data buffer 4, meanwhile, outlet selector 1 reads from data buffer 1 complement code and σ _i ², and inputting real part divider respectively as dividend and divisor, outlet selector 2 is sense data from data buffer 3 complement code and σ _i ², input imaginary part divider as dividend and divisor; The 3rd clock cycle, input selection controller is by temporary new one group of data again stored in data buffer 1 and data buffer 3, and meanwhile, outlet selector 1 reads from data buffer 2 complement code and σ _i+1 ², input real part divider, outlet selector 2 reads from data buffer 4 complement code and σ _i+1 ², input imaginary part divider.In subsequent clock, what module circulated in the above described manner will input data buffer storage, row operation of going forward side by side.

In LLR computing module, the output of divider 1 and divider 2 is b ₁, b ₀corresponding LLR soft-decision metrics value, this decision metric value is admitted in output state in parallel, and LLR soft-decision metrics is exported, to complete subsequent operation by the handshake between next stage module by output state.

The present invention supports QPSK and BPSK (BinaryPhaseShiftKeying, two-phase phase shift keying) two kinds of modulation systems, when system modulation mode is BPSK, do not need to make any adjustment to hardware configuration of the present invention, only the output of divider 1 in LLR computing module need be exported as final LLR soft-decision metrics value.

The above is the embodiment of the present invention under a kind of system parameters, and be not used for being limited the present invention, the present invention is applicable under different system parameterss.

Claims (5)

1. a Turbo-STBC (SpaceTimeBlockCode, Space-Time Block Coding) generate the implementation method of soft-decision metrics in system, it is characterized in that: the method by designing receiving terminal LLR (LoglikelihoodRatio on FPGA hardware platform, log-likelihood ratio) maker module realizes, wherein receiving terminal LLR maker module is by channel estimating input buffer, base band data input buffer, noise variance input buffer, STBC decoder, LLR arithmetic unit, output state is formed;

1.1. channel estimating input buffer, base band data input buffer, noise variance input buffer, respectively by its inside input control device, the channel parameter of input LLR maker module, receiving terminal baseband signal and noise variance signal are carried out buffer memory, and input respective inside FIFO buffer unit;

1.2.STBC decoder module is used for the realization of STBC combination algorithm, and this module reads in channel parameter and receiving terminal baseband signal from channel estimating input buffer, base band data input buffer, and carries out STBC associative operation by internal arithmetic circuit;

1.3LLR operator block is used for the realization of LLR soft-decision metrics generating algorithm, noise variance signal in the output signal of STBC decoder and noise variance input buffer is carried out LLR computing by this module, operation result is sent into output state and exports as final result.

2. according to the implementation method generating soft-decision metrics in a kind of Turbo-STBC system described in claim 1, it is characterized in that: in described 1.2, STBC decoder is inner by arithmetic element multiplex controller and reusable real part computing module, reusable imaginary-part operation module composition, two reusable computing modules can carry out the switching of operational pattern according to the change of the control signal low and high level of arithmetic element multiplex controller input, when carrying out STBC associative operation to adjacent baseband signal, realize the time division multiplexing of computing circuit.

3. according to the implementation method generating soft-decision metrics in a kind of Turbo-STBC system described in claim 1, it is characterized in that: in described 1.3, LLR arithmetic unit adopts LLR shortcut calculation, this algorithm simplifies traditional algorithm further for QPSK quarternary phase-shift keying (QPSK) modulation system, and in shortcut calculation, the LLR value of each modulation bit is expressed as:

$LLR\left(b_0\right)=-Im\left(s_i\right)\·\frac{2}{{\mathrm{\σ}}^2}$

$LLR\left(b_1\right)=-\mathrm{Re}\left(s_i\right)\·\frac{2}{{\mathrm{\σ}}^2}$

B in formula ₀, b ₁for modulation bit, s _ifor receiving terminal baseband signal, Im for getting real part computing, Re for getting imaginary-part operation, σ ²for channel noise variance.

4. according to the implementation method generating soft-decision metrics in a kind of Turbo-STBC system described in claim 1, it is characterized in that: in described 1.3, LLR arithmetic unit is inner to be made up of input data buffer storage unit and divider, adopts two parallel links computing simultaneously modulation bit b ₀, b ₁corresponding LLR value; Input data buffer storage unit adopts ping-pong operation mode to input divider by after input data buffer storage, in ping-pong operation, input selection controller is by while data Input Data Buffer, carry out negate to corresponding data and add 1 in data buffer, what achieve data asks complement arithmetic.

5. according to the implementation method generating soft-decision metrics in a kind of Turbo-STBC system described in claim 2, it is characterized in that: reusable real part computing module inside adopts concurrent operation structure, be divided into 4 grades of arithmetic units, 1st grade of arithmetic unit is made up of 8 multipliers, 2nd grade of arithmetic unit is made up of 4 controlled adder-subtracters of pattern, 3rd level arithmetic unit is made up of 2 adders, and the 4th grade of arithmetic unit is made up of 1 adder; The front 3 grades of arithmetic units of reusable imaginary-part operation module are identical with real part computing module, and the 4th grade of arithmetic unit is made up of 1 subtracter.