CN103311283A - Power semiconductor chip gate resistor - Google Patents
Power semiconductor chip gate resistor Download PDFInfo
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- CN103311283A CN103311283A CN201310259231XA CN201310259231A CN103311283A CN 103311283 A CN103311283 A CN 103311283A CN 201310259231X A CN201310259231X A CN 201310259231XA CN 201310259231 A CN201310259231 A CN 201310259231A CN 103311283 A CN103311283 A CN 103311283A
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Abstract
Provided is a power semiconductor chip gate resistor. A gate resistor is arranged in a chip gate resistor region, the gate resistor region is arranged between a main gate region and a gate ring. The main gate region and the gate ring are arranged in a chip cellular region. The gate ring surrounds the main gate region. The gate resistor at least comprises two sub-resistors. One end of each sub-resistor is connected with the main gate region, and the other end of each sub-resistor is connected with the gate ring. Due to the fact that the gate resistor is formed by connecting at least two sub-resistors in parallel, when one sub-resistor is damaged, other sub-resistors can still work normally, and signals are transmitted between the main gate region and the gate ring. The gate resistor avoids the risk of chip damage caused by resistor damage due to series-connection of a single resistor in the prior art.
Description
Technical field
The present invention relates to field of semiconductor devices, relate in particular to a kind of power semiconductor chip gate resistance.
Background technology
Application in a lot of power electronic device usually is connected in parallel to realize the target power grade with many power semiconductor chips (as IGBT, MOSFET etc.).For the switching speed of controlling power semiconductor chip to improve the equal properties of flow between the chip, a kind of method in a gate resistance of chip internal series connection has been proposed, the gate regions of this method power semiconductor chip is set to central gate and gate bar two parts, and gate resistance is connected between the two.Because the error of resistance is generally bigger, for the identical central gate signal of different chip chambers, the signal on gate bar is then widely different, causes the inhomogeneous and not current-sharing of switching speed of chip chamber easily.Even when the resistance of series connection is damaged, no longer include signal on the gate bar, have a strong impact on the operate as normal of chip, even cause entire chip to be damaged.
Summary of the invention
In view of this, the invention provides a kind of power semiconductor chip gate resistance, this gate resistance structure can improve the current-sharing performance of power chip, reduces single resistance simultaneously and damages the risk that entire chip is just damaged.
In order to solve the problems of the technologies described above, the invention provides a kind of power semiconductor chip gate resistance, described gate resistance is positioned at the gate resistance district of chip, described gate resistance district is positioned between main grid polar region and the grid circle, described main grid polar region and described grid circle are positioned at the chip cellular region, and described grid circle surrounds described main grid polar region, and described gate resistance comprises two sub-resistances at least, one end of each described sub-resistance connects described main grid polar region, and the other end connects described grid circle.
Further, described sub-resistance is evenly distributed in the described gate resistance district.
Further, described sub-resistance is strip structure.
Further, the two ends of described sub-resistance long side direction connects described main grid polar region and described grid circle respectively, and the width of the broadside of described sub-resistance is constant on the direction of extending to described grid circle along described main grid polar region.
Further, the two ends of described sub-resistance long side direction connects described main grid polar region and described grid circle respectively, and the width of the broadside of described sub-resistance increases on the direction of extending to described grid circle along described main grid polar region gradually.
Further, described sub-resistance be shaped as circle or polygon, an end of described sub-resistance is connected with described main grid polar region by first metal connecting line, the other end passes through second metal connecting line and is connected with described grid circle.
Further, described sub-resistance is non-closed hoop structure, the inboard of described sub-resistance is connected with described main grid polar region by first metal connecting line, the outside of described sub-resistance is connected with described grid circle by second metal connecting line, wherein, described first metal connecting line and described second metal connecting line distribute alternately.
Further, each described sub-resistance comprises the first sub-resistance and the second sub-resistance in parallel at least.
Further, the described first sub-resistance and the described second sub-resistance are the overlapping distribution of interlayer.
The present invention also provides another kind of power semiconductor chip gate resistance, described gate resistance is positioned at the gate resistance district of chip, described gate resistance district is positioned between main grid polar region and the grid circle, described main grid polar region and described grid circle are positioned at the chip cellular region, and described grid circle surrounds described main grid polar region, described gate resistance comprises at least one first resistive segments and at least one second resistive segments that is non-closed hoop structure, and described first resistive segments and described second resistive segments are the interlayer complementary distribution, described first resistive segments the inboard be connected with described main grid polar region by some first metal connecting lines, the outside of described second resistive segments is passed through some second metal connecting lines and is connected with described grid circle.
The present invention also provides another power semiconductor chip gate resistance, described gate resistance is positioned at the gate resistance district of chip, described gate resistance district is positioned between main grid polar region and the grid circle, described main grid polar region and described grid circle are positioned at the chip cellular region, and described grid circle surrounds described main grid polar region, described gate resistance comprises first resistance that is the closed hoop structure that surrounds described main grid polar region, the inboard of described first resistance is connected with described main grid polar region by some first metal connecting lines, and the outside of described first resistance is connected with described grid circle by some second metal connecting lines.
Further, described first metal connecting line and described second metal connecting line distribute alternately.
Further, described gate resistance also comprises inboard that at least one is positioned at described first sub-resistance or second resistance that is the closed hoop structure in the outside, the inboard that is positioned at the sub-resistance of the most close described main grid polar region is connected with described main grid polar region by some first metal connecting lines, the outside that is positioned at the sub-resistance of the most close described grid circle is connected with described grid circle by some second metal connecting lines, connects by some articles of the 3rd metal connecting lines between the adjacent described sub-resistance.
Further, described first metal connecting line, described second metal connecting line and described the 3rd metal connecting line evenly distribute alternately.
The power semiconductor chip gate resistance of the present invention all-in resistance that at least two sub-resistances compose in parallel of serving as reasons, this gate resistance is connected between main grid polar region and the grid circle.By the switch control characteristic of this gate resistance control chip and the uniformity of electric current.This gate resistance has following beneficial effect: because this gate resistance is by at least two sub-resistance parallel connections, when one of them sub-resistance is damaged, other sub-resistances still can operate as normal, transmits signal between main grid polar region and grid circle.Therefore, this gate resistance avoided of the prior art because single resistance string associated come because resistance damages, chip just faces the risk of damage.In addition, the resistance value of gate resistance of the present invention is the total resistance value after each sub-resistance parallel connection, even there is error in the resistance of single sub-resistance, the different gate bar in the chip also are identical with the resistance between the main grid polar region.Thereby the uniformity of switching speed of chip internal cellular in parallel and the uniformity of electric current have been improved.
Description of drawings
In order to be expressly understood the technical scheme of prior art or the embodiment of the invention, to do to introduce simply to the accompanying drawing of required use in prior art or the embodiment of the invention description below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the gate regions structural representation of the embodiment of the invention;
Fig. 2 to Fig. 9 is the gate resistance structural representation of the embodiment of the invention.
Embodiment
Describe the present invention below with reference to embodiment shown in the drawings.But these execution modes do not limit the present invention, and the conversion on the structure that those of ordinary skill in the art makes according to these execution modes, method or the function all is included in protection scope of the present invention.
As shown in Figure 1, the gate regions structure of the power semiconductor chip that provides of the embodiment of the invention comprises in grid circle 02 and the gate resistance district 03 between main grid polar region 01 and grid circle 02 near the main grid polar region 01 in the chip cellular region 10, encirclement main grid polar region 01.Be provided with gate resistance in gate resistance district 03, an end of this gate resistance connects main grid polar region 01, and the other end connects grid circle 02.The total resistance value scope of gate resistance is between 2～5 ohm.
The gate regions shape of the embodiment of the invention can be different shapes such as circle, bar shaped or regular polygon, and similarly, the main grid polar region 01 in this gate regions, grid circle 02 also can be shapes such as circle, bar shaped or polygon.Be that example describes in the following description with the circle.Be appreciated that present embodiment does not limit gate regions for circular, can be other shapes.In order to make being evenly distributed of gate resistance, the shape of preferred main grid polar region 01 is identical with the shape of grid circle 02, and further preferred both center overlaps.
Be connected on above-mentioned shortcoming between central gate and the gate bar in order to overcome single gate resistance in the prior art, present embodiment is provided with the sub-resistance of a plurality of parallel connections in the gate resistance district.Total resistance value after these sub-resistance parallel connections is the resistance of gate resistance.For parallel connection or the series parallel structure of realizing the sub-resistance in the gate resistance district, and each sub-resistance is evenly distributed on the gate resistance district, the invention provides the gate resistance structure of different structure, and concrete structure is referring to following examples.
Referring to Fig. 2, be provided with 4 sub-resistances 24 that are strip structure in the gate resistance district 03 in gate regions, the two ends of the long side direction of this each sub-resistance 24 connects main grid polar region 01 and grid circle 02 respectively.Thereby realized between main grid polar region 01 and grid circle 02 purpose of a plurality of sub-resistances 24 in parallel.Should be conducive to reduce because the resistance of the gate resistance that the single resistive band of series connection comes changes significantly by a plurality of sub-resistance 24 gate resistances that form in parallel, reduce simultaneously because gate resistance damage entire chip just can't operate as normal even the risk that is damaged.
In addition, because an end of the different gate bar in the chip is connected with the grid circle, gate bar and grid circle are made by the metallic conduction material, and the gate resistance between different gate bar and the main grid polar region is exactly the gate resistance between grid circle and the main grid polar region.The resistance value of the gate resistance of present embodiment is the total resistance value after each sub-resistance parallel connection, even there is error in the resistance of single sub-resistance, make that different gate bar also are identical with resistance between the main grid polar region, can guarantee that the current-sharing stability of characteristics of the uniformity of switching speed of chip internal cellular in parallel and chip chamber is reliable.
In addition, present embodiment is integrated in chip internal with gate resistance, in the prior art on liner plate or substrate the scheme of series resistance, present embodiment has been removed the resistance on liner plate or the substrate, reduce the packaging technology difficulty, improved packaging technology efficient, simplified the design of liner plate or substrate, reduce liner plate or substrate volume, improved the reliability of device.
In order to make each sub-resistance be evenly distributed in the gate regions, the preferred sub-resistance 24 of present embodiment is evenly distributed in the gate resistance district 03, specifically, this sub-resistance 24 distribution in the gate resistance district can be symmetrically distributed about the one-tenth center, center of main grid polar region 01, and perhaps the angle between the adjacent sub-resistance 24 equates.In addition, as shown in Figure 2, this width of broadside that is the sub-resistance of strip structure is invariable in the direction of extending to grid circle 02 along main grid polar region 01.In order to improve the distribution consistency degree of resistance in gate regions, as shown in Figure 3, the width of this sub-resistance 34 can increase gradually in the direction of extending to grid circle 02 along main grid polar region 01.
Understand easily, the number of the sub-resistance of present embodiment is not defined as described above 4, as long as the number of this sub-resistance is in the purpose that can satisfy the resistance parallel connection more than 2.For example, the number of this sub-resistance can be 2,3,6,10 etc.And being readily appreciated that the number of sub-resistance in parallel is more many, the error between the single sub-resistance is more little to the contribution of all-in resistance, makes that the electric current uniformity of chip chamber is better.Simultaneously, sub-resistance is more many, and the risk of damage of damaging the entire chip bring owing to resistance is more little.
As another embodiment of the present invention, the shape of this sub-resistance can also be circle or polygon.In order to realize the even distribution of gate resistance in gate regions, these sub-resistances preferably are evenly distributed in the gate resistance district.As shown in Figure 4, being shaped as circular sub-resistance 44 is evenly distributed in the gate resistance district 03.And an end of each sub-resistance 44 is connected with main grid polar region 01 by first metal connecting line 51, and the other end is connected with grid circle 02 by second metal connecting line 52.Each sub-resistance 44 is realized being connected with grid circle 02 with main grid polar region 01 respectively with second metal connecting line 52 by first metal connecting line 51, thereby has realized the parallel connection of a plurality of sub-resistances between main grid polar region 01 and grid circle 02.
As another embodiment of the present invention, as shown in Figure 5, the shape of this sub-resistance 54 can be non-closed hoop structure, when described circulus is circular configuration, this sub-resistance 54 be shaped as the arc structure with certain width, preferred each radius that is the sub-resistance 54 of arc structure of present embodiment equates, the arc length of circular arc equates that each sub-resistance 54 is evenly distributed in the gate resistance district 03.Each sub-resistance 54 is connected with main grid polar region 01 by first metal connecting line 51 near a side (inboard) of main grid polar region 01, side (outside) near grid circle 02 is connected with grid circle 02 by second metal connecting line 52, realizes being connected in parallel of gate resistance 03 and main grid polar region 01 and grid circle 02.
The sub-resistance that is non-closed hoop structure shown in Figure 5 54 is single resistance, the sub-resistance that this sub-resistance 54 can also be formed by a plurality of sub-resistance.As shown in Figure 6, this sub-resistance 54 can also comprise the first sub-resistance 541 and the second sub-resistance 542, and this first sub-resistance 541 and the second sub-resistance 542 are connected in parallel.The inboard that is positioned at the first sub-resistance 541 of close main grid polar region 01 is connected with main grid polar region 01 by first metal connecting line, and the outside that is positioned at the second sub-resistance 542 of close grid circle 02 is connected with grid circle 02 by second metal connecting line.Easy to connect between technologic easy realization and the sub-resistance, the first sub-resistance 541 and the second sub-resistance 542 are the overlapping distribution of interlayer, in other words, the position of two terminations of the position of two of the first sub-resistance 541 terminations and the second sub-resistance 542 be positioned at main grid polar region 01 to grid circle 02 extend in the radial direction same.In other words, second circumference at first circumference at the first sub-resistance, 541 places and the second sub-resistance, 542 places is concentric circles, and the first sub-resistance 541 and the second sub-resistance 542 are positioned at the same sector region of disc.
As another embodiment of the present invention, as shown in Figure 7, gate resistance comprises at least one first resistive segments 741 and at least one second resistive segments 742 that is non-closed hoop structure, first resistive segments 741 and the second sub-resistive segments 742 are the arc section of different radii, and first resistive segments 741 and second distribution of resistive segments 742 in the gate resistance district are the interlayer complementary distribution.Namely second circumference at first circumference at first resistive segments, 741 ' place and second resistive segments, 742 ' place is concentric circles, and the termination of the termination of first resistive segments 741 and second resistive segments 742 is positioned in the radial direction same from beginning to end, and by metal connecting line first resistive segments 741 and second resistive segments 742 are communicated with, the gate resistance that two resistive segments are formed constituted one close-shaped.For realize with main grid polar region 01 and grid circle 02 between be connected, the inboard of first resistive segments 741 is connected with main grid polar region 01 by some first metal connecting lines 51, and the outside of second resistive segments 742 is connected with grid circle 02 by some second metal connecting lines 52.
As another embodiment of the present invention, as shown in Figure 8, this gate resistance is a ring resistance that is the closed hoop structure 84 that surrounds main grid polar region 01, the inboard of this ring resistance 84 is connected with main grid polar region 01 by some (two) first metal connecting line 51 at least, preferred first metal connecting line 51 is evenly distributed in the gate resistance district, the outside of this ring resistance 84 is connected with grid circle by some (two) second metal connecting line 52 at least, and preferred second metal connecting line 52 is evenly distributed in the gate resistance district.Further preferred, the quantity of first metal connecting line is identical with the quantity of second metal connecting line 52.And first metal connects 51 lines and second metal connecting line 52 evenly distributes alternately.
Above-mentioned gate resistance shown in Figure 8 only comprises a ring resistance 84 that is the closed hoop structure.For more resistance is set in the gate resistance district, and resistance is evenly distributed in the gate resistance district, as shown in Figure 9, this gate resistance can also be a plurality of ring resistances that are the closed hoop structure.For convenience of description, these a plurality of ring resistances are called after first ring resistance 941, second ring resistance 942 successively from inside to outside ..., N ring resistance 94n.First ring resistance 941 that is positioned at the most close main grid polar region 01 is connected with main grid polar region 01 by some first metal connecting lines 51, the N ring resistance 94n that is positioned at the most close grid circle 02 is connected with the grid circle by some second metal connecting lines 52, and connect by some articles of the 3rd metal connecting lines 53 between the adjacent ring resistance, further preferred, be distributed in the gate resistance district between first metal connecting line, 51, the second metal connecting lines 52 and the 3rd metal connecting line 53 homogeneous phases.
Be to be understood that, though this specification is described according to execution mode, but be not that each execution mode only comprises an independently technical scheme, this narrating mode of specification only is for clarity sake, those skilled in the art should make specification as a whole, technical scheme in each execution mode also can form other execution mode that it will be appreciated by those skilled in the art that through appropriate combination.
Above listed a series of detailed description only is specifying at feasibility execution mode of the present invention.They are not in order to limiting protection scope of the present invention, and equivalent execution mode or change that all the present invention's of disengaging designs are done all should be included within protection scope of the present invention.
Claims (14)
1. power semiconductor chip gate resistance, it is characterized in that, described gate resistance is positioned at the gate resistance district of chip, described gate resistance district is positioned between main grid polar region and the grid circle, described main grid polar region and described grid circle are positioned at the chip cellular region, and described grid circle surrounds described main grid polar region, and described gate resistance comprises two sub-resistances at least, one end of each described sub-resistance connects described main grid polar region, and the other end connects described grid circle.
2. gate resistance according to claim 1 is characterized in that, described sub-resistance is evenly distributed in the described gate resistance district.
3. gate resistance according to claim 1 and 2 is characterized in that, described sub-resistance is strip structure.
4. gate resistance according to claim 3, it is characterized in that, the two ends of described sub-resistance long side direction connects described main grid polar region and described grid circle respectively, and the width of the broadside of described sub-resistance is constant on the direction of extending to described grid circle along described main grid polar region.
5. gate resistance according to claim 3, it is characterized in that, the two ends of described sub-resistance long side direction connects described main grid polar region and described grid circle respectively, and the width of the broadside of described sub-resistance increases on the direction of extending to described grid circle along described main grid polar region gradually.
6. gate resistance according to claim 1 and 2, it is characterized in that, described sub-resistance be shaped as circle or polygon, an end of described sub-resistance is connected with described main grid polar region by first metal connecting line, the other end passes through second metal connecting line and is connected with described grid circle.
7. gate resistance according to claim 1 and 2, it is characterized in that, described sub-resistance is non-closed hoop structure, the inboard of described sub-resistance is connected with described main grid polar region by first metal connecting line, the outside of described sub-resistance is connected with described grid circle by second metal connecting line, wherein, described first metal connecting line and described second metal connecting line distribute alternately.
8. gate resistance according to claim 7 is characterized in that, each described sub-resistance comprises the first sub-resistance and the second sub-resistance in parallel at least.
9. gate resistance according to claim 8 is characterized in that, the described first sub-resistance and the described second sub-resistance are the overlapping distribution of interlayer.
10. power semiconductor chip gate resistance, it is characterized in that, described gate resistance is positioned at the gate resistance district of chip, described gate resistance district is positioned between main grid polar region and the grid circle, described main grid polar region and described grid circle are positioned at the chip cellular region, and described grid circle surrounds described main grid polar region, described gate resistance comprises at least one first resistive segments and at least one second resistive segments that is non-closed hoop structure, and described first resistive segments and described second resistive segments are the interlayer complementary distribution, described first resistive segments the inboard be connected with described main grid polar region by some first metal connecting lines, the outside of described second resistive segments is passed through some second metal connecting lines and is connected with described grid circle.
11. power semiconductor chip gate resistance, it is characterized in that, described gate resistance is positioned at the gate resistance district of chip, described gate resistance district is positioned between main grid polar region and the grid circle, described main grid polar region and described grid circle are positioned at the chip cellular region, and described grid circle surrounds described main grid polar region, described gate resistance comprises first resistance that is the closed hoop structure that surrounds described main grid polar region, the inboard of described first resistance is connected with described main grid polar region by some first metal connecting lines, and the outside of described first resistance is connected with described grid circle by some second metal connecting lines.
12. gate resistance according to claim 11 is characterized in that, described first metal connecting line and described second metal connecting line distribute alternately.
13. according to claim 11 or 12 described gate resistances, it is characterized in that, described gate resistance also comprises inboard that at least one is positioned at described first sub-resistance or second resistance that is the closed hoop structure in the outside, the inboard that is positioned at the sub-resistance of the most close described main grid polar region is connected with described main grid polar region by some first metal connecting lines, the outside that is positioned at the sub-resistance of the most close described grid circle is connected with described grid circle by some second metal connecting lines, connects by some articles of the 3rd metal connecting lines between the adjacent described sub-resistance.
14. gate resistance according to claim 13 is characterized in that, described first metal connecting line, described second metal connecting line and described the 3rd metal connecting line evenly distribute alternately.
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| CN201310259231.XA CN103311283B (en) | 2013-06-26 | 2013-06-26 | A kind of power semiconductor chip gate resistor |
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| CN201310259231.XA CN103311283B (en) | 2013-06-26 | 2013-06-26 | A kind of power semiconductor chip gate resistor |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448967A (en) * | 2015-12-21 | 2016-03-30 | 国网智能电网研究院 | Novel gate structure and manufacture method thereof |
| CN105609481A (en) * | 2015-12-21 | 2016-05-25 | 国网智能电网研究院 | Novel package and manufacturing method thereof |
| CN104022093B (en) * | 2014-06-17 | 2016-09-28 | 江苏中科君芯科技有限公司 | A kind of integrated variable gate resistance grid structure |
| CN110444592A (en) * | 2019-09-12 | 2019-11-12 | 无锡德力芯半导体科技有限公司 | A kind of gate structure and IGBT device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4764802A (en) * | 1986-03-19 | 1988-08-16 | Kabushiki Kaisha Toshiba | Semiconductor devices |
| US5661315A (en) * | 1995-12-28 | 1997-08-26 | Asea Brown Boveri Ag | Controllable power semiconductor component |
| CN202178566U (en) * | 2011-08-22 | 2012-03-28 | 无锡艾柯威科技有限公司 | Series capacitor protective circuit |
| CN102842610A (en) * | 2011-06-22 | 2012-12-26 | 中国科学院微电子研究所 | Igbt chip and manufacturing method thereof |
-
2013
- 2013-06-26 CN CN201310259231.XA patent/CN103311283B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4764802A (en) * | 1986-03-19 | 1988-08-16 | Kabushiki Kaisha Toshiba | Semiconductor devices |
| EP0237932B1 (en) * | 1986-03-19 | 1993-09-22 | Kabushiki Kaisha Toshiba | Wiring layout for bipolar and unipolar insulated gate transistors |
| US5661315A (en) * | 1995-12-28 | 1997-08-26 | Asea Brown Boveri Ag | Controllable power semiconductor component |
| CN102842610A (en) * | 2011-06-22 | 2012-12-26 | 中国科学院微电子研究所 | Igbt chip and manufacturing method thereof |
| CN202178566U (en) * | 2011-08-22 | 2012-03-28 | 无锡艾柯威科技有限公司 | Series capacitor protective circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104022093B (en) * | 2014-06-17 | 2016-09-28 | 江苏中科君芯科技有限公司 | A kind of integrated variable gate resistance grid structure |
| CN105448967A (en) * | 2015-12-21 | 2016-03-30 | 国网智能电网研究院 | Novel gate structure and manufacture method thereof |
| CN105609481A (en) * | 2015-12-21 | 2016-05-25 | 国网智能电网研究院 | Novel package and manufacturing method thereof |
| CN105609481B (en) * | 2015-12-21 | 2024-04-12 | 国网智能电网研究院 | Novel package and manufacturing method thereof |
| CN110444592A (en) * | 2019-09-12 | 2019-11-12 | 无锡德力芯半导体科技有限公司 | A kind of gate structure and IGBT device |
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| CN103311283B (en) | 2016-02-03 |
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Address after: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee after: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee before: ZHUZHOU CSR TIMES ELECTRIC Co.,Ltd. |
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Effective date of registration: 20200930 Address after: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province Patentee after: Zhuzhou CRRC times Semiconductor Co.,Ltd. Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee before: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. |