CN103308520B - Evaluation method for polycrystal battery technical level and slice source - Google Patents

Abstract

The invention proposes a battery technology and an evaluation method for polycrystalline silicon chip source. The method uses electroluminescence or photoluminescence to extract defect information in silicon wafers, thereby obtaining quantitative parameters that can be used to characterize the quality of silicon wafers. Further, the present invention is based on the quantitative parameters, combined with the open-circuit voltage V _oc test of the battery, and separates the impact of the battery technology level and the polysilicon wafer source on V _oc .

Description

A method for evaluating the process level and source of polycrystalline cells

technical field

The invention belongs to the field of polycrystalline solar cells, in particular to an evaluation method for the technological level of polycrystalline solar cells and the quality of chip sources.

Background technique

In the field of polycrystalline silicon solar cells, the quality of polycrystalline silicon wafers and cell technology have an impact on cell performance. Therefore, how to separately evaluate the influence of polysilicon wafer source quality and battery process from battery performance (such as V _oc ), so as to simultaneously monitor wafer source and battery process level, is a problem that the industry has been working on solving.

Contents of the invention

The invention proposes a battery technology and an evaluation method for polycrystalline silicon chip sources. The method uses electroluminescence or photoluminescence to extract defect information in silicon wafers, thereby obtaining quantitative parameters that can be used to characterize the quality of silicon wafers. Further, the present invention is based on the quantitative parameters, combined with the open-circuit voltage V _oc test of the battery, and separates the impact of the battery technology level and the polysilicon wafer source on V _oc .

According to the first aspect of the present invention, a method for extracting quantitative parameters for characterizing the quality of a silicon wafer of a polycrystalline cell is proposed, comprising: acquiring an electroluminescence EL image or a photoluminescence PL image of a polycrystalline cell; processing the EL or a PL image to obtain a minority carrier lifetime image; calculate the minority carrier lifetime parameter LT of the polycrystalline battery based on the minority carrier lifetime image; and use the minority carrier lifetime parameter LT as a quantitative parameter of silicon wafer quality.

In the above method, the minority carrier lifetime image is obtained by processing the EL image or PL image in the following manner: performing maximum filtering on the EL image or PL image; subtracting the filtered image from the original image; The image is optionally linearly transformed, and the raster lines are removed with a mask.

In the above method, the form of the maximum value filtering is: β _i,j =M _i,j -max(R _i,j ), where M _i,j represents the brightness of the pixel point (i,j) to be investigated currently , max(R _i,j ) represents the maximum value in the neighborhood of the pixel to be investigated currently, and Β _i,j represents the difference between the two.

In the above method, the brightness of each pixel on the minority carrier lifetime image corresponds to the minority carrier lifetime of the pixel position on the silicon wafer; the brightness of each pixel on the minority carrier lifetime image corresponds to the permanent defect information of the pixel position on the silicon wafer.

In the above method, the average minority carrier lifetime is calculated based on the minority carrier lifetime image to obtain the minority carrier lifetime parameter LT.

According to the second aspect of the present invention, an online polysilicon wafer source quality monitoring method for solar cells is proposed. According to the method of the first aspect, the minority carrier lifetime parameter LT is obtained online; and the minority carrier lifetime parameter LT is used as an indicator of silicon wafer quality. Quantify parameters and compare the quality differences between film sources.

According to the third aspect of the present invention, a method for evaluating the influence of polycrystalline silicon chip source quality on the open circuit voltage of polycrystalline cells is proposed, including: selecting batches of standard polycrystalline silicon chips, and producing batches of standard polycrystalline cells under standard processes; For each of the standard polycrystalline cells in the batch, use the method in the first aspect to obtain the corresponding minority carrier lifetime parameter LT as a quantitative parameter of silicon wafer quality; for each of the standard polycrystalline cells in the batch, measure its Corresponding open-circuit voltage V _oc ; and based on the minority carrier lifetime parameter LT and open-circuit voltage V _oc of the batch of standard polycrystalline cells, a primary analytical formula is fitted: V _oc =k·LT+b, where b is a constant, and the coefficient k characterizes the impact of the quality of the silicon chip source on V _oc .

In the above method, after a plurality of silicon rods are sliced, they are equally selected to select the batch of standard polysilicon wafers.

According to the fourth aspect of the present invention, a method for evaluating the influence of the manufacturing process of solar cells on the open circuit voltage of polycrystalline cells is proposed, including: according to the method of the third aspect, obtaining the relational expression V of V _oc and LT under the standard sheet technology _oc = k·LT+b; test the open circuit voltage V _oc1 of each batch of polycrystalline cells manufactured by the process to be evaluated; according to the method of the first aspect, test the minority carrier lifetime parameter LT1 of each of the batch polycrystalline cells ; Calculate the average value of LT1, and substitute the average value into the relational formula V _oc =k·LT+b to obtain the average open-circuit voltage V _oc0 under the standard chip process; and the difference α between V _oc1 and V _oc0 Characterize the difference in open circuit voltage V _oc between the process to be evaluated and the standard chip process.

According to a fifth aspect of the present invention, an online process monitoring method for solar cells is proposed, comprising: obtaining the difference α online according to the method of the fourth aspect; and determining the process to be evaluated compared to the standard sheet process based on the difference α stability. .

Description of drawings

The accompanying drawings are included to provide further understanding of the present invention, and they are incorporated and constitute a part of this application. The accompanying drawings illustrate embodiments of the present invention and together with the specification serve to explain the principle of the present invention. In the attached picture:

Figure 1a shows an electroluminescence (EL) image of a polycrystalline cell according to an embodiment of the present invention.

Fig. 1b shows a minority carrier lifetime diagram obtained after processing the image in Fig. 1a according to an embodiment of the present invention.

Figure 2 shows the relationship between the open circuit voltage and the minority carrier lifetime of a standard sheet.

Detailed ways

The present invention is described in detail below with reference to the accompanying drawings, including the technical principle on which the present invention is based, and typical implementations.

The invention proposed by this application may include the following aspects:

1. Image acquisition

According to the invention, electroluminescence (EL) or photoluminescence (PL) images of polycrystalline cells can be obtained, both images being similar. Figure 1(a) exemplifies the electroluminescence image. Images can have a bit depth of 16 bits or higher.

2. Image processing

Image processing according to the invention is mainly information extraction of permanent defects in EL/PL images. PL or EL images are the result of radiation recombination, so the brightness of the pixels should be proportional to the excess carrier Δn and background doping concentration (p ₀ or n ₀ ). In the case of a certain implantation concentration, Δn is related to the minority carrier lifetime at the location of the pixel. Some crystal structure defects in polycrystals are small in size and strong in recombination ability, which will bring about sudden changes in the spatial scale of Δn, and corresponding sudden changes in pixel brightness. The background doping concentration is caused by the segregation of the ingot process and the diffusion of the battery process. The characteristics of these two processes determine that it is impossible to cause a sudden change in the EL (PL) brightness, but only bring brightness on a large scale. uneven. The embodiment of the present invention exemplarily adopts 50×50 maximum value filtering, subtracts from the original image, and then undergoes linear transformation (this step is optional, the purpose of linear transformation is to convert the brightness difference into minority carrier lifetime based on the assumed calibration value ) and use a mask to remove the part of the grid lines to obtain the minority carrier lifetime image (see Figure 1b), and calculate the average minority carrier lifetime to obtain the minority carrier lifetime parameter LT. The form of maximum filtering is as follows:

β _i,j =M _i,j -max(R _i,j ) (Formula 1)

In the above formula 1, M _i,j represents the brightness of the pixel point (i,j) to be investigated currently, max(R _i,j ) represents the maximum value in the neighborhood of the pixel currently to be investigated, and Β _i,j represents the difference.

Through the above processing, the minority carrier lifetime parameter LT is extracted from the EL/PL image, which can be used as a quantitative parameter of silicon wafer quality.

Supplementary explanation: The brightness value on the minority carrier lifetime image is proportional to the minority carrier lifetime in principle. This method examines the relative value of the brightness deviation, so it is not necessary to calibrate the specific ratio of the two, and the minority carrier lifetime can be directly represented by the brightness value.

3. Standard cell test and standard curve acquisition

According to the present invention, a group of systematically selected polysilicon wafers can be selected, for example, 50-100 wafers, and these standard wafers have different quality levels. The selection method can be to select multiple silicon rods at equal intervals after slicing to ensure that the quality of the silicon wafers is representative. Throw silicon wafers into a stable process to make cells. Test the V _oc and EL images of each battery, and use the method in step 2 to calculate its minority carrier lifetime parameter LT. Draw the corresponding V _oc and LT into a scatter diagram, and the primary relationship shown in Figure 2 can be obtained, and its analytical formula can be fitted according to the primary relationship

V _oc =k·LT+b (Formula 2)

In the above formula, b is a constant, and the coefficient k represents the influence of the quality of the silicon chip represented by LT on the open circuit voltage V _oc . Therefore, for silicon wafer sources of different quality, after knowing the minority carrier lifetime parameter LT, the quality can be judged, and the influence of quality difference on battery performance (V _oc ) can be judged.

4. Process and chip source evaluation of any batch of polycrystalline cells

According to the present invention, a batch of batteries with unknown technology and chip source can be taken, the V _oc1 of the batteries can be measured, and the minority carrier lifetime parameter LT1 can be calculated according to the EL (PL) image. Calculate the average value of LT1, and substitute the average value into formula 2 to calculate V _oc0 , let α=V _oc0 -V _oc1 , then α is the V _oc difference between the measured cell and the standard cell due to the process. The stability of the process can be evaluated by monitoring the size of α. For example, when the magnitude of α exceeds a threshold, it can be considered that the unknown process to be evaluated has a large deviation compared with the standard process.

As mentioned above, the minority carrier lifetime parameter LT itself can represent the quality of the silicon wafer. Therefore, the quality of the silicon wafer can be judged by monitoring the parameter LT. It is also possible to substitute the LT difference △LT between the two chip sources (between the silicon wafer to be tested and the reference silicon wafer) into Equation 2 to obtain the equivalent opening voltage difference △V _oc between the chip sources.

The foregoing describes various aspects of the invention. The above description is only for expressing the technical principles and concepts of the present invention, and should not be regarded as limiting the scope of the present invention. For example, the above describes the scheme of evaluating both the process and the chip source of polycrystalline cells, but those skilled in the art should understand that the present invention should cover the embodiment of evaluating the process alone and the quality of the chip source alone.

Example 1:

Embodiment 1 aims to extract quantitative parameters for characterizing the quality of silicon wafers of polycrystalline cells. Example 1 may include:

1) Obtain the EL/PL image of the solar cell;

2) The EL/PL image is processed to extract the minority carrier lifetime parameter LT, which is used as a quantitative parameter to characterize the quality of the silicon wafer of the polycrystalline cell.

Further, based on the minority carrier lifetime parameter LT, the quality of the silicon wafer source can be judged, and the quality of the silicon wafer source can be monitored online.

Example 2:

Example 2 aims to evaluate the influence of the quality of the polycrystalline silicon wafer on the open circuit voltage of the solar cell. Example 1 may include:

1) Select a certain batch of silicon wafers, and make cells in a certain process.

2) Test battery V _oc and EL, and calculate its minority carrier lifetime parameter LT.

3) It can be seen from the standard film source V _oc and LT curves in Figure 2 that the LT calculated in step 2 is linearly related to V _oc . Therefore, the relationship between V _oc and minority carrier lifetime LT can be fitted according to the first-order relationship to obtain the influence of unit LT on battery V _oc (k in Equation 2).

Example 3:

Example 3 aims to evaluate the influence of the cell manufacturing process on the open circuit voltage of the solar cell. Example 3 may include:

1) On the premise that the relationship between the open circuit voltage and life of the standard chip is known (as shown in the fitting curve formula in Figure 2),

Test a group of polycrystalline solar cells with unknown silicon source and cell technology, and get V _oc1 and LT1 of each cell.

2) Calculate the average value of LT1, substitute the average value into formula 2, and calculate the average V _oc0 under the standard chip process.

3) The difference α between V _oc1 and V _oc0 is the difference of V _oc between the tested battery and the standard sheet process.

Further, based on the difference α, the stability of the manufacturing process of the solar cell can be monitored online.

The effect of the invention

The invention uses the EL (PL) image of the cell to extract quantitative parameters to characterize the quality of the silicon sheet of the polycrystalline cell. Further, based on the extracted quantitative parameters and combined with the V _oc test, the present invention can quickly determine the pros and cons of the battery technology and polysilicon wafer source. The test time of the two test methods is less than 1 second, and can be made into an online mode to monitor the stability of the battery process and the quality of the multi-chip source.

Claims (10)

1. A method for extracting quantitative parameters for characterizing the quality of silicon wafers of polycrystalline cells, comprising: Obtain electroluminescence EL images or photoluminescence PL images of polycrystalline cells; processing the EL or PL image to obtain a minority carrier lifetime image, wherein the processing of the EL or PL image includes: performing maximum filtering on the EL image or PL image, subtracting the filtered image from the original image, An optional linear transformation is performed on the subtracted image and a mask is used to remove the raster lines; calculating a minority carrier lifetime parameter LT of the polycrystalline battery based on the minority carrier lifetime image; and The minority carrier lifetime parameter LT is used as a quantitative parameter of silicon wafer quality. 2. The method according to claim 1, wherein the form of the maximum value filter is: β _i,j = M _i,j -max(R _i,j ), Among them, M _i,j represents the brightness of the pixel point (i,j) to be investigated currently, max(R _i,j ) represents the maximum value in the neighborhood of the pixel to be investigated currently, and Β _i,j represents the difference between the two. 3. The method according to claim 1, wherein the brightness of each pixel on the minority carrier lifetime image corresponds to the minority carrier lifetime of the pixel position on the silicon wafer. 4. The method according to claim 1, wherein the brightness of each pixel on the minority carrier lifetime image corresponds to the permanent defect information of the pixel position on the silicon wafer. 5. The method according to claim 1, wherein the average minority carrier lifetime is calculated based on the minority carrier lifetime image to obtain the minority carrier lifetime parameter LT. 6. A method for monitoring the quality of an online polysilicon wafer source for solar cells, comprising: According to the method according to any one of claims 1-5, the minority carrier lifetime parameter LT is obtained online; and The minority carrier lifetime parameter LT is used as a quantitative parameter of silicon wafer quality to compare quality differences among wafer sources. 7. A method for evaluating the influence of polycrystalline silicon chip source quality on the open circuit voltage of polycrystalline cells, comprising: Select batches of standard polycrystalline silicon wafers, and manufacture batches of standard polycrystalline cells under standard processes; For each of the standard polycrystalline cells in the batch, use the method of any one of claims 1-5 to obtain the corresponding minority carrier lifetime parameter LT as a quantitative parameter of silicon wafer quality; For each of the batch of standard polycrystalline cells, measuring its corresponding open circuit voltage V _oc ; and Based on the minority carrier lifetime parameter LT and the open circuit voltage V _oc of the batch of standard polycrystalline cells, a primary analytical formula is fitted: V _oc =k·LT+b Among them, b is a constant, and the coefficient k represents the influence of the quality of the silicon chip source on V _oc . 8. The method according to claim 7, characterized in that, after a plurality of silicon rods are sliced, they are equally selected to select the batch of standard polysilicon wafers, and the batches of polysilicon wafers have two or more quality grade. 9. A method for evaluating the influence of a manufacturing process of a solar cell on the open circuit voltage of a polycrystalline cell, comprising: According to the method described in claim 7 or 8, obtain the relational expression V _oc =k·LT+b of V _oc and LT under the standard sheet technology; Test the open circuit voltage V _oc1 of each of the batch polycrystalline cells fabricated by the process to be evaluated; According to the method according to any one of claims 1-5, testing the minority carrier lifetime parameter LT1 of each of the batch polycrystalline cells; Calculate the average value of LT1, and substitute the average value into the relational formula V _oc =k·LT+b to obtain the average open circuit voltage V _oc0 under the standard chip process; and The difference α between V _oc1 and V _oc0 is used to represent the difference in open circuit voltage V _oc between the process to be evaluated and the standard chip process. 10. An online process monitoring method for solar cells, comprising: Obtaining the difference α online according to the method according to claim 9; and Based on the difference α, the stability of the process to be evaluated compared to the standard sheet process is judged.