CN103300844B - Twelve-lead electrocardiosignal synchronous acquisition module - Google Patents

Abstract

A twelve-lead electrocardiosignal synchronous acquisition module belongs to the technical field of medical devices and solves the problems that the existing twelve-lead electrocardiogram adopts wired measurement, so the detection is inconvenient and the measuring equipment is high in cost. The twelve-lead electrocardiosignal synchronous acquisition module comprises a body surface electrode, an electrocardiosignal input circuit, a differential amplification circuit, a filter circuit, a lead selection circuit, a signal amplification circuit, a analog-digital conversion circuit, a single chip computer and a level switching circuit all connected in sequence. When in use, the twelve-lead electrocardiosignal synchronous acquisition module disclosed by the invention is connected with an embedded WIFI module, and then connected with a computer in a wireless manner, so a low-cost domestic twelve-lead electrocardiogram wireless measuring system is established, domestic wireless measurement of the electrocardiogram is realized, the electrocardiogram detection is convenient, and the detecting equipment is low in cost.

Description

A kind of 12 lead electrocardiosignal synchronous acquisition module

Technical field

The invention belongs to armarium technical field, particularly a kind of electrocardiogram signal acquisition device.

Background technology

It is important cardiac function and heart disease indagation means that twelve-lead electrocardiogram detects.Existing twelve-lead electrocardiogram adopts wired measuring, therefore causes and detects the higher of inconvenience and measurement device price, and the measurement of twelve-lead electrocardiogram often can only be completed in hospital.

Summary of the invention

For solving existing twelve-lead electrocardiogram, adopt wired measuring, detect inconvenience and the high problem of measurement device cost, the invention provides a kind of 12 lead electrocardiosignal synchronous acquisition module, its technical scheme is as follows:

A kind of 12 lead electrocardiosignal synchronous acquisition module:

Comprise successively the external electrode, electrocardiosignal input circuit, differential amplifier circuit, the filter circuit that connect, lead and select circuit, signal amplification circuit, analog to digital conversion circuit, one-chip computer and level shifting circuit.

Preferred version as the inventive method:

Described external electrode comprises right crus of diaphragm RF electrode, left foot LF electrode, left hand L electrode, right hand R electrode, and electrode V1, electrode V2, electrode V3, electrode V4, electrode V5 and electrode V6, wherein right crus of diaphragm electrode RF earth terminal;

Described electrocardiosignal input circuit comprises four-operational amplifier LM324, and resistance is resistance R 101, resistance R 102, resistance R 103, resistance R 104, resistance R 105, resistance R 106, resistance R 107, resistance R 108 and the resistance R 109 of 10K ohm, and Wilson's network;

Wherein Wilson's network comprises by resistance and is the Y-connection that resistance R 116, resistance R 117 and the resistance R 118 of 30K ohm form, the inner women's head-ornaments of the inner termination of the inner termination of resistance R 116, resistance R 117 and resistance R 118 link together, and form Wilson's network center point; Series resistor R110 and resistance R 111 successively between the external end head of the external end head of resistance R 116 and resistance R 117, series resistor R115 and resistance R 114 successively between the external end head of the external end head of resistance R 116 and resistance R 118, series resistor R112 and resistance R 113 successively between the external end head of resistance R 117 and the external end head of resistance R 118; Resistance R 110, resistance R 111, resistance R 112, resistance R 113, resistance R 114 form triangle with resistance R 115 and are connected; The resistance of resistance R 110, resistance R 111, resistance R 112, resistance R 113, resistance R 114 and resistance R 115 is 20K ohm;

Wherein four-operational amplifier LM324 comprises the first operational amplifier, the 3rd operational amplifier and four-operational amplifier; VCC termination+5V power supply of four-operational amplifier LM324, VEE termination-5V power supply of four-operational amplifier LM324; Left foot LF electrode is connected with the in-phase input end of four-operational amplifier, and the inverting input of four-operational amplifier is connected with the outfan of four-operational amplifier, forms left foot LF voltage follower; Left hand L electrode is connected with the in-phase input end of the 3rd operational amplifier, and the inverting input of the 3rd operational amplifier is connected with the outfan of the 3rd operational amplifier, forms left hand L voltage follower; Right hand R electrode is connected with the in-phase input end of the first operational amplifier, and the inverting input of the first operational amplifier is connected with the outfan of the first operational amplifier, forms right hand R voltage follower; Right hand R voltage follower is connected with the external end head of resistance R 118, and left foot LF voltage follower is connected with the external end head of resistance R 116, and left hand L voltage follower is connected with the external end head of resistance R 117;

Described differential amplifier circuit comprises 12 data amplifier AD620, is respectively U201, U202, U203, U204, U205, U206, U207, U208, U209, U210, U211 and U212; The equal earth terminal of 5 pin of 5 pins of data amplifier U201,5 pins of data amplifier U202,5 pins of data amplifier U203,5 pins of 5 pins of data amplifier U204, data amplifier U205,5 pins of 5 pins of data amplifier U206, data amplifier U207,5 pins of 5 pins of data amplifier U208, data amplifier U209,5 pins of 5 pins of data amplifier U210, data amplifier U211 and data amplifier U212;

Wherein electrode V1 is connected to the in-phase input end of data amplifier U206 after resistance R 106, electrode V2 is connected to the in-phase input end of data amplifier U205 after resistance R 105, electrode V3 is connected to the in-phase input end of data amplifier U204 after resistance R 104, electrode V4 is connected to the in-phase input end of data amplifier U203 after resistance R 103, electrode V5 is connected to the in-phase input end of data amplifier U202 after resistance R 102, and electrode V6 is connected to the in-phase input end of data amplifier U201 after resistance R 101; The inverting input of the inverting input of the inverting input of the inverting input of the inverting input of the inverting input of data amplifier U201, data amplifier U202, data amplifier U203, data amplifier U204, data amplifier U205 and data amplifier U206 is all connected to Wilson's network center point;

Wherein the in-phase input end of data amplifier U207 connects left foot LF voltage follower after resistance R 107, and the inverting input of data amplifier U207 connects left hand L voltage follower after resistance R 108; The in-phase input end of data amplifier U208 connects right hand R voltage follower after resistance R 109, and the inverting input of data amplifier U208 is connected with the Wilson's zero-potential point between resistance R 110 and resistance R 111; The in-phase input end of data amplifier U209 connects left foot LF voltage follower after resistance R 107, and the inverting input of data amplifier U209 connects right hand R voltage follower after resistance R 109; The in-phase input end of data amplifier U210 connects left foot LF voltage follower after resistance R 107, and the inverting input of data amplifier U210 is connected with the Wilson's zero-potential point between resistance R 112 and resistance R 113; The in-phase input end of data amplifier U211 connects left hand L voltage follower after resistance R 108, and the inverting input of data amplifier U211 connects right hand R voltage follower after resistance R 109; The in-phase input end of data amplifier U212 connects left hand L voltage follower after resistance R 108, and the inverting input of data amplifier U212 is connected with the Wilson's zero-potential point between resistance R 114 and resistance R 115;

Described filter circuit comprises 12 band filters, each band filter comprises the single order RC high pass filter that a cut-off frequency being connected with the outfan of data amplifier is 0.16Hz, and the single order RC low pass filter that the outfan of single order RC high pass filter is 106Hz with a cut-off frequency is connected;

Described leading selects circuit to comprise simulant electronic switch U301, simulant electronic switch U302, and the phase inverter consisting of audion T301, resistance R 301 and resistance R 302; Simulant electronic switch U301 and simulant electronic switch U302 are multidiameter option switch KCF4051BE; Audion T301 is audion C1815; Connect+5V of the vdd terminal of simulant electronic switch U301 power supply; Connect+5V of the vdd terminal of simulant electronic switch U302 power supply; The VSS end earth terminal of simulant electronic switch U301; VEE termination-5V power supply of simulant electronic switch U301; The VSS end earth terminal of simulant electronic switch U302; VEE termination-5V power supply of simulant electronic switch U302; Wherein the resistance of resistance R 301 is 22K ohm, and the resistance of resistance R 302 is 1M ohm, and the inner termination of resistance R 301 is connected with the colelctor electrode of audion T301, connect+5V of the external end head of resistance R 301 power supply; The inner termination of resistance R 302 is connected with the base stage of audion T301; The sheet choosing end INH of the colelctor electrode connecting analog electrical switch U301 of audion T301, the grounded emitter end of audion T301;

Wherein the outfan of data amplifier U201 via a described band filter after, output signal V6 is connected to the X3 end of simulant electronic switch U301; The outfan of data amplifier U202 via a described band filter after, output signal V5 is connected to the X2 end of simulant electronic switch U301; The outfan of data amplifier U203 via a described band filter after, output signal V4 is connected to the X1 end of simulant electronic switch U301; The outfan of data amplifier U204 via a described band filter after, output signal V3 is connected to the X0 end of simulant electronic switch U301; The outfan of data amplifier U205 via a described band filter after, output signal V2 is connected to the X7 end of simulant electronic switch U302; The outfan of data amplifier U206 via a described band filter after, output signal V1 is connected to the X6 end of simulant electronic switch U302; The outfan of data amplifier U207 via a described band filter after, output signal III is connected to the X2 end of simulant electronic switch U302; The outfan of data amplifier U208 via a described band filter after, output signal aVR is connected to the X3 end of simulant electronic switch U302; The outfan of data amplifier U209 via a described band filter after, output signal II is connected to the X1 end of simulant electronic switch U302; The outfan of data amplifier U210 via a described band filter after, output signal aVF is connected to the X5 end of simulant electronic switch U302; The outfan of data amplifier U211 via a described band filter after, output signal I is connected to the X0 end of simulant electronic switch U302; The outfan of data amplifier U212 via a described band filter after, output signal aVL is connected to the X4 end of simulant electronic switch U302;

Wherein the A of the A of simulant electronic switch U301 end, simulant electronic switch U302 holds all P1.0 ends of the unit's of being connected to sheet machine AT89C2051; The B end of described simulant electronic switch U301, the B end of simulant electronic switch U302 be the P1.1 end of the unit's of being connected to sheet machine AT89C2051 all; The C end of described simulant electronic switch U301, the C end of simulant electronic switch U302 be the P1.2 end of the unit's of being connected to sheet machine AT89C2051 all; The P1.3 end of sheet choosing end INH, the sheet machine AT89C2051 of unit of the external end head connecting analog electrical switch U302 of resistance R 302;

Described signal amplification circuit comprises data amplifier U303, and data amplifier U303 is data amplifier AD620; Between 1 pin of data amplifier U303 and 8 pins, connecting resistance is the potentiometer R303 of 1K ohm; Outfan X, the outfan X of simulant electronic switch U302 of the in-phase input end connecting analog electrical switch U301 of data amplifier U303, the reverse inter-input-ing ending grounding end of data amplifier U303, the outfan of data amplifier U303 is received the input AIN0 of A/D converter TLC2543; Connect+5V of the 7 pins power supply of data amplifier U303, connect-5V of the 4 pins power supply of data amplifier U303; 5 pins of data amplifier U303 connect the positive pole of diode D301, the negative pole of diode D301 connects the positive pole of diode D302, the negative pole of diode D302 connects the positive pole of diode D303, and the negative pole of diode D303 connects the positive pole of diode D304, the minus earth end of diode D304; 5 pins of data amplifier U303 connect the resistance R 304 that resistance is 22K ohm, another termination+5V power supply of resistance R 304; The negative pole of the output terminating diode D305 of data amplifier U303, the plus earth end of diode D305;

Analog-digital conversion circuit as described comprises serial a/d transducer TLC2543, and the AIN1 end of A/D converter TLC2543, AIN2 end, AIN3 end, AIN4 end, AIN5 end, AIN6 end, AIN7 end, AIN8 end, AIN9 end, AIN10 end, negative reference voltage end REF-and GND hold equal earth terminal; Connect+5V of the vdd terminal of A/D converter TLC2543 power supply; The synchronised clock end SCLK of A/D converter TLC2543 is connected to the P1.4 end of the described sheet machine AT89C2051 of unit, the serial data input DIN of A/D converter TLC2543 is connected to the P1.5 end of the described sheet machine AT89C2051 of unit, the serial data outfan DOUT of A/D converter TLC2543 is connected to the P1.6 end of the described sheet machine AT89C2051 of unit, and the sheet choosing end CS of A/D converter TLC2543 is connected to the P1.7 of the described sheet machine AT89C2051 of unit; Resistance is one termination+5V power supply of the resistance R 401 of 1K ohm, the reference voltage end REF+ of another termination A/D converter TLC2543 of resistance R 401; It is the resistance R 403 of 4.7K ohm that the reference voltage end REF+ of A/D converter TLC2543 is connected in series swept resistance R402 and the resistance that resistance is 5K ohm between holding with ground successively, 3 pins of stabilivolt TL431 connect reference voltage end REF+, 1 pin of stabilivolt TL431 is connected between swept resistance R402 and resistance R 403, the 2 pin earth terminals of stabilivolt TL431;

Described one-chip computer comprises the described sheet machine AT89C2051 of unit, on the sheet machine AT89C2051 of unit, be provided with reset circuit, described reset circuit comprises the VCC end of the sheet machine AT89C2051 of the unit of being connected to and the capacitor C 401 between RST end, one end of reset key K401 connects the VCC end of the sheet machine AT89C2051 of unit, the other end contact resistance R404 of reset key K401, the other end of resistance R 404 connects the RST end of the sheet machine AT89C2051 of unit, one end of resistance R 405 connects the RST end of the sheet machine AT89C2051 of unit, the other end earth terminal of resistance R 405; On the sheet machine AT89C2051 of unit, be provided with oscillating circuit, described oscillating circuit comprises the XTL2 end of the sheet machine AT89C2051 of the unit of being connected to and the crystal oscillator X401 between XTL1 end, the frequency of crystal oscillator X401 is 11.0592MHz, between XTL2 end and XTL1 end, be also serially connected with successively capacitor C 402 and capacitor C 403, earth terminal between capacitor C 402, capacitor C 403; The P1.1 end of the sheet machine AT89C2051 of unit connects pull-up resistor R406, another termination+5V power supply of pull-up resistor R406; The P1.0 end of the sheet machine AT89C2051 of unit connects pull-up resistor R407, another termination+5V power supply of pull-up resistor R407; The GND end earth terminal of the sheet machine AT89C2051 of unit;

Described level shifting circuit comprises level shifting circuit and RS232C interface, and level shifting circuit comprises electrical level transferring chip MAX232, and capacitance is capacitor C 404, capacitor C 405, capacitor C 406 and the capacitor C 407 of 1 microfarad; One termination of capacitor C 404+5V power supply, 2 pins of another termination electrical level transferring chip MAX232 of capacitor C 404; Between 1 pin of electrical level transferring chip MAX232 and 3 pins, connect capacitor C 405; Between 4 pins of electrical level transferring chip MAX232 and 5 pins, connect capacitor C 406; Between 6 pins of electrical level transferring chip MAX232 and 8 pins, connect capacitor C 407; 8 pins of electrical level transferring chip MAX232,10 pin earth terminals; 11 pins of electrical level transferring chip MAX232 connect the TXD end of the described sheet machine AT89C2051 of unit, and 14 pins of electrical level transferring chip MAX232 connect the RXD end of described RS232C interface; The TXD end of described RS232C interface connects 13 pins of electrical level transferring chip MAX232, and 12 pins of electrical level transferring chip MAX232 connect the RXD end of the described sheet machine AT89C2051 of unit; Connect+5V of the 16 pins power supply of electrical level transferring chip MAX232; The GND end earth terminal of described RS232C interface.

During use, acquisition module of the present invention and serial ports are turned to WIFI module and be connected, serial ports turns WIFI module and is connected with computer wireless, can set up low-cost domestic twelve-lead electrocardiogram wireless measuring system, realizes Electrocardiographic family wireless and measures.

The invention solves the problem of the outside transmission of detection, electrocardiosignal digitized and electrocardiosignal of electrocardiosignal, a kind of ECG signal sampling of 12 lead cheaply module is provided, realized the function that 12 lead electrocardiosignal synchronous detecting, analog signal digital and digital signal outwards transmit by serial ports, make twelve-lead electrocardiogram easy to detect, and checkout equipment cost is low.

System work process of the present invention is as follows:

1. when module powers in wait command state;

2. when module receives the order from serial ports, according to order decision, continue to wait for or carry out the work of 12 lead ECG signal sampling: when ordering as " #00H ", continuing to wait for, when order is " #01H～#0FFH ", carry out respectively the 12 lead ecg signal data collection of different pieces of information amount;

3. collecting flowchart: gather 1 byte-> and transmit 1 byte-> and gather 1 byte-> and transmit 1 byte

4. each data that gather and send by serial ports are to take the one-dimension array that " V6, I, II, III, aVR, aVL, aVF, V1, V2, V3, V4, V5 " respectively lead and be arranged in order as the cycle;

5. gathering and send each byte time used by serial ports is 260.0 μ s(measured values).

The concrete technique effect of the present invention is as follows:

1. utilize universal operational amplifier to form the buffer stage that voltage follower leads as left foot LF, left hand L, right hand R, greatly reduce three output resistances that lead, can drive well Wilson's network, improve the accuracy that unipolar chest lead electrocardiosignal is measured.

2. utilize universal data amplifier AD620 to carry out differential amplification to each lead signals, to simplify circuit, reduce costs.

3. each lead signals after utilizing single order RC passive bandpass filters to differential amplification is carried out every straight filtering and anti-aliasing filter, is guaranteeing to have reduced under the prerequisite that electrocardiosignal can correctly be sampled the complexity of circuit (meticulousr filtering is left more economical digital filter for and processed).

4. utilize simulant electronic switch successively each lead signals to be carried out to gating under the control of single-chip microcomputer, meeting each lead signals measurement synchronicity requirement (adjacent time delay 0.26ms that leads, a maximum delay 3.21ms leads, much smaller than QRS wave group persistent period 60ms, also can show by software adjustment the twelve-lead electrocardiogram of Complete Synchronization simultaneously) prerequisite under simplified circuit design.

5. utilize the universal data amplifier of a slice to amplify choosing lead signals to carry out appropriateness.Amplification is adjusted into+200～+ 500 times between, so both guaranteed certainty of measurement, simplified again circuit design.

6. under the control of one-chip computer AT89C2051, carry out controlled data collection: 1. wait for the order from serial ports; 2. according to serial port command, determine whether to carry out data acquisition and how many data of continuous acquisition.

7. continuous data collection: choose and lead under the control of single-chip microcomputer, carry out A/D conversion to choosing to lead, and transformation result is sent by RS232C serial ports; Choose next to lead and it is carried out to A/D conversion and serial data transmission; The 12 lead of take repeats above process as the cycle, until complete the data acquisition amount of requirement.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of a kind of 12 lead electrocardiosignal of the present invention synchronous acquisition module;

Fig. 2 is the algorithm design figure of a kind of 12 lead electrocardiosignal synchronous acquisition module in Fig. 1.

The specific embodiment

A kind of 12 lead electrocardiosignal synchronous acquisition module as shown in Figure 1, consists of following circuit:

1. hardware circuit forms

1.1 electrocardiosignal importations

Electrocardiosignal importation is comprised of LM324 and R101～R118.

Electrocardiosignal is from body surface.By left foot LF, left hand L, right hand R and V1, V2, V3, V4, V5, V6 totally nine external electrodes obtain electrocardiosignaies, right crus of diaphragm electrode RF is connected with the ground end of whole acquisition module.

Six electrode signals of V1～V6 are connected to differential amplification part via six 10K resistance of R106～R101 respectively.

Tri-electrode signals of left foot LF, left hand L and right hand R are connected respectively three operational amplifier in-phase input ends of LM324; The inverting input of each operational amplifier is connected respectively to the outfan of oneself, forms voltage follower; Left foot LF, left hand L and right hand R signal from voltage follower are connected respectively to Wilson's network and differential amplification part; Resistance R 110～R118 forms Wilson's network provides zero-potential point for unipolar chest lead and unipolar extremity lead; Each zero-potential point of Wilson's network is connected respectively to differential amplification part.

LM324 employing ± 5V dual power supply.

1.2 differential amplification parts

Differential amplification part is comprised of data amplifier U201～U212.

Six electrode signals of V1～V6 are connected to respectively the in-phase input end of data amplifier U206～U201 via six 10K resistance of R106～R101, the inverting input of U206～U201 is all connected to Wilson's network center point; The in-phase input end of U207～U212 connects respectively left foot LF voltage follow signal, right hand R voltage follow signal, left foot LF voltage follow signal, left foot LF voltage follow signal, left hand L voltage follow signal, left hand L voltage follow signal, and the inverting input of U207～U212 connects respectively left hand L voltage follow signal, Wilson's zero-potential point, right hand R voltage follow signal, Wilson's zero-potential point, right hand R voltage follow signal, Wilson's zero-potential point; The outfan of data amplifier U201～U212 is exported respectively the differential amplification signal that V6～V1, III, aVR, II, aVF, I, aVL respectively lead, and amplification is+1; U201～U212 adopts conventional data amplifier AD620, ± 5V dual power supply.

1.3 filtering part

Filtering part is comprised of C201～C224, R201～R224.

C201～C212, R201～R212 forms 12 single order RC high pass filters, and cut-off frequency is 0.16Hz; C213～C224, R213～R224 forms 12 single order RC low pass filters, and cut-off frequency is 106Hz; 12 band filters of the common composition of high and low pass filter, band connection frequency is 0.16Hz～106Hz.

The 1.4 selection parts of leading

Lead and select part to be formed by simulant electronic switch U301, U302, audion T301, resistance R 301, R302.

Simulant electronic switch U301, U302 adopt 8 to select 1 multidiameter option switch KCF4051BE, in order to respectively leading and select, the phase inverter that the sheet choosing of two electronic analog swtichs is comprised of audion C1815 is realized, the input resistance of phase inverter adopts the large resistance of 1M, and object is to reduce the control electric current of single chip computer AT 89C2051 control end P1.3.

From lead signals I, II, III, aVR, aVL, aVF, V1, the V2 of wave filter, be connected respectively to input selection end X0～X7 of U302, V3～V6 is connected respectively to input selection end X0～X3 of U301; Multidiameter option switch KCF4051BE(U301, U302) employing ± 5V dual power supply, sheet choosing end INH Low level effective, chip selection signal is from the control end P1.3 of single chip computer AT 89C2051; The A of U301, U302, B, C end be P1.0, P1.1, the P1.2 end of the unit's of receiving sheet machine AT89C2051 respectively, and P1.3 is connected with the sheet choosing end INH of U302, and is connected with the sheet choosing end INH of U301 after the phase inverter forming through R301, T301, R302.

1.5 signal amplifying part are divided

Signal amplifying part is divided by data amplifier U303, potentiometer R303, resistance R 304, diode D301～D305 and is formed.

U303 adopts data amplifier AD620, regulator potentiometer R303 can obtain required amplification ( actual adopted value is A _u=+500); The in-phase input end of AD620 meets the outfan X of U301 and U302, reverse inter-input-ing ending grounding end, and outfan is received the input AIN0 of A/D converter TLC2543; AD620 employing ± 5V dual power supply; Resistance R 304, diode D301～D304 composition+2.4V clamp circuit, object be make output electrocardiosignal be positive voltage, to meet the input requirements of A/D converter TLC2543; Diode D305 is the input protection diode of A/D converter TLC2543, the input terminal voltage of guaranteeing TLC2543-more than 0.6V.

1.6A/D conversion portion

A/D conversion portion is comprised of U401, U402, R401～403.

A/D conversion adopts serial a/d transducer TLC2543(U401), the electrocardiosignal of respectively leading is all from the input of AIN0 end, AIN1～AIN10 and negative reference voltage end REF-ground connection, stabilivolt TL431(U402) and resistance R 401～403 to form mu balanced circuits be provide+4.00V of reference voltage end REF+ normal voltage; The synchronised clock end SCLK of TLC2543, serial data input DIN, serial data outfan DOUT, sheet choosing end CS are connected with P1.4, P1.5, P1.6, the P1.7 of single chip computer AT 89C2051 respectively; The running voltage of TLC2543 is+5V.

1.7 one-chip computer parts

One-chip computer part is by single chip computer AT 89C2051(U403), crystal oscillator X401, reset key K401, resistance R 404～R407, capacitor C 401～C403 form.

The sheet machine AT89C2051(U403 of high performance-price ratio unit that one-chip computer adopts atmel corp to produce); K401, C401, R404, R405 form reset circuit of SCM; X401, C402, C403 form single-chip microcomputer oscillating circuit, and the frequency of crystal oscillator X401 is 11.0592MHz, and adopting this frequency crystal oscillator is in order to obtain more accurate serial communication baud rate; Resistance R 406, R407 are respectively the pull-up resistor of single-chip processor i/o mouth P1.1, P1.0.

1.8 level converting section

Level converting section is comprised of electrical level transferring chip U404, capacitor C 404～C407 and RS232C interface (U405).

Electrical level transferring chip adopts MAX232, and it forms level shifting circuit with capacitor C 404～C407, responsible single-chip microcomputer Transistor-Transistor Logic level and RS232C interface EIA(U.S. Electronic Industries Association) bi-directional conversion between level.

1.9 power pack

Power acquisition use ± 5V dual power supply (the actual 8 joint 1.2V rechargeable battery composition ± 4.8V dual power supplies that adopt) is to module for power supply.

2. Single Chip Microcomputer (SCM) system working method

1.1 electrocardiosignaies are led and are selected to control

The P1 mouth of single chip computer AT 89C2051 is used as common I/O mouth.When P1.3P1.2P1.1P1.0 is output as 0000～0111, choose respectively input X0～X7 of U302, choose respectively I, II, III, aVR, aVL, aVF, V1, V2 respectively to lead; When P1.3P1.2P1.1P1.0 is output as 1000～1011, choose respectively input X0～X3 of U301, choose respectively V3～V6 respectively to lead; So choose respectively I, II, III, aVR, aVL, aVF, each lead signals of V1～V6 when P1.3P1.2P1.1P1.0 is output as 0000～1011, only has selected lead signals just can enter amplifying circuit and A/D change-over circuit.

1.2A/D conversion and control

Under the control of single chip computer AT 89C2051, first making P1.4(is SCLK end) be low level, then to make P1.7(be CS end) be low level, now by DOUT end to A/D transformation result of P1.6 output (actual setting: 8 unsigned numbers, high-order front); Maintenance P1.7 is low level, and making P1.4(is SCLK end) be high level, now TLC2543 reads in an order of the bit word (high-order) from DIN end; Maintenance P1.7 is low level, and making P1.4(is SCLK end) be low level, now TLC2543 is from an A/D transformation result of DOUT end output; Like this, keeping P1.7, be in low level situation, by P1.4, hold the height of level to change, TLC2543 just reads in command word and output A/D transformation result successively from a high position to low level, until 8 order of the bit words and 8 A/D transformation results read in and export complete.

1.3 data communication are controlled

Under the control of single chip computer AT 89C2051, often read the A/D transformation result of 8, just this transformation result (byte) is sent to RS232C serial communication interface through MAX232; Single-chip microcomputer receives the command word from RS232C in interrupt service routine, in order to determine whether to start to gather and start to gather the byte number (byte number of continuous acquisition has determined to gather the lasting time) of rear continuous acquisition.

1.4 single-chip microcomputer mode of operations

Serial communication baud rate is 57600bps, sampled data is 8 bits (12 bytes/samples), single-chip microcomputer is in interrupt service routine when RS232C interface receives command word #01H～#0FFH, and single-chip microcomputer difference continuous acquisition also transmits 1 * 12 * 960～255 * 12 * 960 sampled datas to RS232C interface, collecting flowchart: gather 1 byte-> and transmit 1 byte-> and gather 1 byte-> and transmit 1 byte because the mode of operation of A/D converter TLC2543 is that " export upper one lead next command word-Ben that leads of A/D translation data-read in A/D conversion of leading " three work are synchronously carried out, so the data that single-chip microcomputer gathers and exports are with " V6 at every turn, I, II, III, aVR, aVL, aVF, V1, V2, V3, V4, V5 " one-dimension array of respectively leading and being arranged in order for the cycle, be array element A0, A12, A24 ... it is the signal data that V6 leads, array element A1, A13, A25 ... it is the signal data that I leads, array element A2, A14, A26 ... it is the signal data that II leads, when single-chip microcomputer receives command word #00H, single-chip microcomputer maintains the state of wait command, single-chip microcomputer start or reset after the also state in wait command.

1.5 sample rate tests

Single byte sampling period estimation: by the known serial ports single byte delivery time of serial communication baud rate 57600bps be 139 μ s, serial a/d transducer TLC2543 single byte conversion required time is about 88 μ s, so the single byte sampling period is about 227 μ s; Owing to must also having some judgements, put the process need regular hours such as number the time except above in sampling process, so the sampling period of reality can be slightly larger than estimated value.

Single byte sampling period test: allow single-chip microcomputer continuous acquisition transmit 255 * 12 * 960 sampled datas to RS232C interface by parameter setting, with stopwatch, record these data acquisition required times, thereby calculate average each byte, gathered required time (measured value is 260.0 μ s/Byte); When sending command word #02H to single-chip microcomputer, the sampling time is 5.99 seconds (about tenth of the point clock).

Claims (1)

1. a 12 lead electrocardiosignal synchronous acquisition module, is characterized in that:

Comprise successively the external electrode, electrocardiosignal input circuit, differential amplifier circuit, the filter circuit that connect, lead and select circuit, signal amplification circuit, analog to digital conversion circuit, one-chip computer and level shifting circuit;

Described external electrode comprises right crus of diaphragm RF electrode, left foot LF electrode, left hand L electrode, right hand R electrode, and electrode V1, electrode V2, electrode V3, electrode V4, electrode V5 and electrode V6, wherein right crus of diaphragm electrode RF earth terminal;

Described electrocardiosignal input circuit comprises four-operational amplifier LM324, and resistance is resistance R 101, resistance R 102, resistance R 103, resistance R 104, resistance R 105, resistance R 106, resistance R 107, resistance R 108 and the resistance R 109 of 10K ohm, and Wilson's network;

Wherein Wilson's network comprises by resistance and is the Y-connection that resistance R 116, resistance R 117 and the resistance R 118 of 30K ohm form, the inner women's head-ornaments of the inner termination of the inner termination of resistance R 116, resistance R 117 and resistance R 118 link together, and form Wilson's network center point; Series resistor R110 and resistance R 111 successively between the external end head of the external end head of resistance R 116 and resistance R 117, series resistor R115 and resistance R 114 successively between the external end head of the external end head of resistance R 116 and resistance R 118, series resistor R112 and resistance R 113 successively between the external end head of resistance R 117 and the external end head of resistance R 118; Resistance R 110, resistance R 111, resistance R 112, resistance R 113, resistance R 114 form triangle with resistance R 115 and are connected; The resistance of resistance R 110, resistance R 111, resistance R 112, resistance R 113, resistance R 114 and resistance R 115 is 20K ohm;

Wherein four-operational amplifier LM324 comprises the first operational amplifier, the 3rd operational amplifier and four-operational amplifier; VCC termination+5V power supply of four-operational amplifier LM324, VEE termination-5V power supply of four-operational amplifier LM324; Left foot LF electrode is connected with the in-phase input end of four-operational amplifier, and the inverting input of four-operational amplifier is connected with the outfan of four-operational amplifier, forms left foot LF voltage follower; Left hand L electrode is connected with the in-phase input end of the 3rd operational amplifier, and the inverting input of the 3rd operational amplifier is connected with the outfan of the 3rd operational amplifier, forms left hand L voltage follower; Right hand R electrode is connected with the in-phase input end of the first operational amplifier, and the inverting input of the first operational amplifier is connected with the outfan of the first operational amplifier, forms right hand R voltage follower; Right hand R voltage follower is connected with the external end head of resistance R 118, and left foot LF voltage follower is connected with the external end head of resistance R 116, and left hand L voltage follower is connected with the external end head of resistance R 117;

Described differential amplifier circuit comprises 12 data amplifier AD620, is respectively U201, U202, U203, U204, U205, U206, U207, U208, U209, U210, U211 and U212; The equal earth terminal of 5 pin of 5 pins of data amplifier U201,5 pins of data amplifier U202,5 pins of data amplifier U203,5 pins of 5 pins of data amplifier U204, data amplifier U205,5 pins of 5 pins of data amplifier U206, data amplifier U207,5 pins of 5 pins of data amplifier U208, data amplifier U209,5 pins of 5 pins of data amplifier U210, data amplifier U211 and data amplifier U212;

Wherein electrode V1 is connected to the in-phase input end of data amplifier U206 after resistance R 106, electrode V2 is connected to the in-phase input end of data amplifier U205 after resistance R 105, electrode V3 is connected to the in-phase input end of data amplifier U204 after resistance R 104, electrode V4 is connected to the in-phase input end of data amplifier U203 after resistance R 103, electrode V5 is connected to the in-phase input end of data amplifier U202 after resistance R 102, and electrode V6 is connected to the in-phase input end of data amplifier U201 after resistance R 101; The inverting input of the inverting input of the inverting input of the inverting input of the inverting input of the inverting input of data amplifier U201, data amplifier U202, data amplifier U203, data amplifier U204, data amplifier U205 and data amplifier U206 is all connected to Wilson's network center point;

Wherein the in-phase input end of data amplifier U207 connects left foot LF voltage follower after resistance R 107, and the inverting input of data amplifier U207 connects left hand L voltage follower after resistance R 108; The in-phase input end of data amplifier U208 connects right hand R voltage follower after resistance R 109, and the inverting input of data amplifier U208 is connected with the Wilson's zero-potential point between resistance R 110 and resistance R 111; The in-phase input end of data amplifier U209 connects left foot LF voltage follower after resistance R 107, and the inverting input of data amplifier U209 connects right hand R voltage follower after resistance R 109; The in-phase input end of data amplifier U210 connects left foot LF voltage follower after resistance R 107, and the inverting input of data amplifier U210 is connected with the Wilson's zero-potential point between resistance R 112 and resistance R 113; The in-phase input end of data amplifier U211 connects left hand L voltage follower after resistance R 108, and the inverting input of data amplifier U211 connects right hand R voltage follower after resistance R 109; The in-phase input end of data amplifier U212 connects left hand L voltage follower after resistance R 108, and the inverting input of data amplifier U212 is connected with the Wilson's zero-potential point between resistance R 114 and resistance R 115;

Described filter circuit comprises 12 band filters, each band filter comprises the single order RC high pass filter that a cut-off frequency being connected with the outfan of data amplifier is 0.16Hz, and the single order RC low pass filter that the outfan of single order RC high pass filter is 106Hz with a cut-off frequency is connected;

Described leading selects circuit to comprise simulant electronic switch U301, simulant electronic switch U302, and the phase inverter consisting of audion T301, resistance R 301 and resistance R 302; Simulant electronic switch U301 and simulant electronic switch U302 are multidiameter option switch KCF4051BE; Audion T301 is audion C1815; Connect+5V of the vdd terminal of simulant electronic switch U301 power supply; Connect+5V of the vdd terminal of simulant electronic switch U302 power supply; The VSS end earth terminal of simulant electronic switch U301; VEE termination-5V power supply of simulant electronic switch U301; The VSS end earth terminal of simulant electronic switch U302; VEE termination-5V power supply of simulant electronic switch U302; Wherein the resistance of resistance R 301 is 22K ohm, and the resistance of resistance R 302 is 1M ohm, and the inner termination of resistance R 301 is connected with the colelctor electrode of audion T301, connect+5V of the external end head of resistance R 301 power supply; The inner termination of resistance R 302 is connected with the base stage of audion T301; The sheet choosing end INH of the colelctor electrode connecting analog electrical switch U301 of audion T301, the grounded emitter end of audion T301;

Wherein the outfan of data amplifier U201 via a described band filter after, output signal V6 is connected to the X3 end of simulant electronic switch U301; The outfan of data amplifier U202 via a described band filter after, output signal V5 is connected to the X2 end of simulant electronic switch U301; The outfan of data amplifier U203 via a described band filter after, output signal V4 is connected to the X1 end of simulant electronic switch U301; The outfan of data amplifier U204 via a described band filter after, output signal V3 is connected to the X0 end of simulant electronic switch U301; The outfan of data amplifier U205 via a described band filter after, output signal V2 is connected to the X7 end of simulant electronic switch U302; The outfan of data amplifier U206 via a described band filter after, output signal V1 is connected to the X6 end of simulant electronic switch U302; The outfan of data amplifier U207 via a described band filter after, output signal III is connected to the X2 end of simulant electronic switch U302; The outfan of data amplifier U208 via a described band filter after, output signal aVR is connected to the X3 end of simulant electronic switch U302; The outfan of data amplifier U209 via a described band filter after, output signal II is connected to the X1 end of simulant electronic switch U302; The outfan of data amplifier U210 via a described band filter after, output signal aVF is connected to the X5 end of simulant electronic switch U302; The outfan of data amplifier U211 via a described band filter after, output signal I is connected to the X0 end of simulant electronic switch U302; The outfan of data amplifier U212 via a described band filter after, output signal aVL is connected to the X4 end of simulant electronic switch U302;

Wherein the A of the A of simulant electronic switch U301 end, simulant electronic switch U302 holds all P1.0 ends of the unit's of being connected to sheet machine AT89C2051; The B end of described simulant electronic switch U301, the B end of simulant electronic switch U302 be the P1.1 end of the unit's of being connected to sheet machine AT89C2051 all; The C end of described simulant electronic switch U301, the C end of simulant electronic switch U302 be the P1.2 end of the unit's of being connected to sheet machine AT89C2051 all; The P1.3 end of sheet choosing end INH, the sheet machine AT89C2051 of unit of the external end head connecting analog electrical switch U302 of resistance R 302;

Described signal amplification circuit comprises data amplifier U303, and data amplifier U303 is data amplifier AD620; Between 1 pin of data amplifier U303 and 8 pins, connecting resistance is the potentiometer R303 of 1K ohm; Outfan X, the outfan X of simulant electronic switch U302 of the in-phase input end connecting analog electrical switch U301 of data amplifier U303, the reverse inter-input-ing ending grounding end of data amplifier U303, the outfan of data amplifier U303 is received the input AIN0 of A/D converter TLC2543; Connect+5V of the 7 pins power supply of data amplifier U303, connect-5V of the 4 pins power supply of data amplifier U303; 5 pins of data amplifier U303 connect the positive pole of diode D301, the negative pole of diode D301 connects the positive pole of diode D302, the negative pole of diode D302 connects the positive pole of diode D303, and the negative pole of diode D303 connects the positive pole of diode D304, the minus earth end of diode D304; 5 pins of data amplifier U303 connect the resistance R 304 that resistance is 22K ohm, another termination+5V power supply of resistance R 304; The negative pole of the output terminating diode D305 of data amplifier U303, the plus earth end of diode D305;

Analog-digital conversion circuit as described comprises serial a/d transducer TLC2543, the AIN1 end of A/D converter TLC2543, AIN2 end, AIN3 end, AIN4 end, AIN5 end, AIN6 end, AIN7 end, AIN8 end, AIN9 end, AIN10 end, negative reference voltage end hold equal earth terminal with GND; Connect+5V of the vdd terminal of A/D converter TLC2543 power supply; The synchronised clock end SCLK of A/D converter TLC2543 is connected to the P1.4 end of the described sheet machine AT89C2051 of unit, the serial data input DIN of A/D converter TLC2543 is connected to the P1.5 end of the described sheet machine AT89C2051 of unit, the serial data outfan DOUT of A/D converter TLC2543 is connected to the P1.6 end of the described sheet machine AT89C2051 of unit, and the sheet choosing end CS of A/D converter TLC2543 is connected to the P1.7 of the described sheet machine AT89C2051 of unit; Resistance is one termination+5V power supply of the resistance R 401 of 1K ohm, the reference voltage end REF+ of another termination A/D converter TLC2543 of resistance R 401; It is the resistance R 403 of 4.7K ohm that the reference voltage end REF+ of A/D converter TLC2543 is connected in series swept resistance R402 and the resistance that resistance is 5K ohm between holding with ground successively, 3 pins of stabilivolt TL431 connect reference voltage end REF+, 1 pin of stabilivolt TL431 is connected between swept resistance R402 and resistance R 403, the 2 pin earth terminals of stabilivolt TL431;

Described one-chip computer comprises the described sheet machine AT89C2051 of unit, on the sheet machine AT89C2051 of unit, be provided with reset circuit, described reset circuit comprises the VCC end of the sheet machine AT89C2051 of the unit of being connected to and the capacitor C 401 between RST end, one end of reset key K401 connects the VCC end of the sheet machine AT89C2051 of unit, the other end contact resistance R404 of reset key K401, the other end of resistance R 404 connects the RST end of the sheet machine AT89C2051 of unit, one end of resistance R 405 connects the RST end of the sheet machine AT89C2051 of unit, the other end earth terminal of resistance R 405; On the sheet machine AT89C2051 of unit, be provided with oscillating circuit, described oscillating circuit comprises the XTL2 end of the sheet machine AT89C2051 of the unit of being connected to and the crystal oscillator X401 between XTL1 end, the frequency of crystal oscillator X401 is 11.0592MHz, between XTL2 end and XTL1 end, be also serially connected with successively capacitor C 402 and capacitor C 403, earth terminal between capacitor C 402, capacitor C 403; The P1.1 end of the sheet machine AT89C2051 of unit connects pull-up resistor R406, another termination+5V power supply of pull-up resistor R406; The P1.0 end of the sheet machine AT89C2051 of unit connects pull-up resistor R407, another termination+5V power supply of pull-up resistor R407; The GND end earth terminal of the sheet machine AT89C2051 of unit;

Described level shifting circuit comprises level shifting circuit and RS232C interface, and level shifting circuit comprises electrical level transferring chip MAX232, and capacitance is capacitor C 404, capacitor C 405, capacitor C 406 and the capacitor C 407 of 1 microfarad; One termination of capacitor C 404+5V power supply, 2 pins of another termination electrical level transferring chip MAX232 of capacitor C 404; Between 1 pin of electrical level transferring chip MAX232 and 3 pins, connect capacitor C 405; Between 4 pins of electrical level transferring chip MAX232 and 5 pins, connect capacitor C 406; Between 6 pins of electrical level transferring chip MAX232 and 8 pins, connect capacitor C 407; 8 pins of electrical level transferring chip MAX232,10 pin earth terminals; 11 pins of electrical level transferring chip MAX232 connect the TXD end of the described sheet machine AT89C2051 of unit, and 14 pins of electrical level transferring chip MAX232 connect the RXD end of described RS232C interface; The TXD end of described RS232C interface connects 13 pins of electrical level transferring chip MAX232, and 12 pins of electrical level transferring chip MAX232 connect the RXD end of the described sheet machine AT89C2051 of unit; Connect+5V of the 16 pins power supply of electrical level transferring chip MAX232; The GND end earth terminal of described RS232C interface.