CN103296877B - A kind of harmonic distortion optimization method of power factor controller and circuit - Google Patents
A kind of harmonic distortion optimization method of power factor controller and circuit Download PDFInfo
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- CN103296877B CN103296877B CN201310225449.3A CN201310225449A CN103296877B CN 103296877 B CN103296877 B CN 103296877B CN 201310225449 A CN201310225449 A CN 201310225449A CN 103296877 B CN103296877 B CN 103296877B
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- 238000000034 method Methods 0.000 title claims abstract description 10
- 238000005457 optimization Methods 0.000 title claims abstract description 8
- 238000005070 sampling Methods 0.000 claims abstract description 25
- 239000003990 capacitor Substances 0.000 description 4
- 230000001276 controlling effect Effects 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
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Abstract
Present invention is disclosed a kind of harmonic distortion optimization method of power factor controller, relate to a kind of digital circuit, be applied in the power factor controlling system of critical conduction mode, this system comprises rectifier bridge and multiplier, and the output of multiplier exports the offset voltage for optimizing harmonic distortion; It is characterized in that: after rectification bridge output end, connect the input that two sampling resistors are input to multiplier, and on an input port of multiplier sample line voltage, connect a current source, realize the adjustment to the offset voltage that multiplier exports by the adjustment of the resistance to two sampling resistors, meet the requirement optimizing harmonic distortion.The present invention can overcome the positive and negative intermodulation distortion of conventional art, improve current quality, and structure is simple, easy to adjust.
Description
Technical field
The present invention relates to a kind of digital circuit, especially a kind of optimisation technique of harmonic distortion (THD) of physical circuit of power factor controller.
Background technology
Power factor controlling, also referred to as power factor correction, is usually used in Switching Power Supply.Wherein, in critical conduction mode power factor control system, the half-wave sinusoidal of simple alternating current input signal after rectifier bridge full-wave rectification contains complicated high-frequency interferencing signal.
As Fig. 1, the current model of a Standard ideal is a level and smooth sine wave.And if had harmonic wave intermodulation distortion, will occur when zero passage distortion, affect current quality.
Traditional means overcoming harmonic distortion (THD) need to connect a high-frequency filter capacitor after rectifier bridge, consider except high-frequency interferencing signal, when the simple alternating current line voltage inputted is very little, the ability of system transfers energy reduces, energy above high-frequency filter capacitor cannot be transferred to output, and above high-frequency filter capacitor, remaining voltage can make rectifier bridge diode end.When input sinusoidal ac is pressed in and passes through zero point, input current cannot pass through rectifier bridge diode, and therefore simple alternating current input current there will be intermodulation distortion when simple alternating current input voltage zero crossing, and the THD of simple alternating current input current is increased.
As shown in Figure 2, in order to optimize the harmonic wave intermodulation distortion (THD) of this critical conduction mode power factor control system, existing optimal way adds a fixing offset voltage at multiplier outputs, the ability of system transfers energy when enhancing simple alternating current input voltage is very low, the dump energy accumulated above by high-frequency filter capacitor is discharged into output.Because be fixed offset voltage is integrated in power factor controller internal multiplier output, not by the size of peripheral components free adjustment offset voltage, so, when power factor controlling system is booster type topological structure, fixing offset voltage added by multiplier outputs can make system obtain a good THD value, but in flyback topological structure, this fixing offset voltage may be bigger than normal, the THD of system is increased.Therefore, traditional THD, under different applied environments, usually occurs that THD optimizes not or THD optimizes excessive situation, by peripheral components, the THD in different application systems cannot be adjusted to an optimal value.
Summary of the invention
The object of the invention is the shortcoming of the prioritization scheme according to the said existing critical conduction mode power factor control system of background technology, invent a kind of can in different applied environments, THD can be adjusted to optimum method and specific implementation circuit.
Method of the present invention, specifically: be applied in the power factor controlling system of critical guide pattern, this system comprises rectifier bridge and multiplier, the output of multiplier exports the offset voltage for optimizing harmonic distortion; It is characterized in that: after rectification bridge output end, connect the input that two sampling resistors are input to multiplier, and on an input port of multiplier sample line voltage, connect a current source, realize the adjustment to the offset voltage that multiplier exports by the adjustment of the resistance to two sampling resistors, meet the requirement optimizing harmonic distortion.
This method of the present invention, by the electric current of current source is added on the sampling resistor of line voltage, time near line voltage zero-cross point, the pressure drop that current source produces on sampling resistor introduces an offset voltage at multiplier input, this offset voltage is by regulating by regulating sampling resistor size, the size of the offset voltage of multiplier outputs can be changed like this, reach the object optimizing whole system harmonic distortion (THD).
The circuit of the harmonic distortion optimization of a kind of power factor controller of the present invention, comprise the rectifier bridge be connected with input power, rectifier bridge exports and is connected with two sampling resistors, the parallel connection point of two sampling resistors exports the sample line voltage input end being connected to multiplier, multiplier outputs to load, it is characterized in that: on the sample line voltage input end of multiplier, be also connected with the current source that flows to sampling resistor.
Accompanying drawing explanation
Fig. 1, undistorted input AC current model figure.
Fig. 2, the circuit diagram increasing fixing offset voltage after multiplier of existing employing.
Fig. 3, circuit diagram of the present invention.
Fig. 4, the current model figure of the positive intermodulation distortion of the excessive appearance of sampling resistor.
Fig. 5, the current model figure of the negative intermodulation distortion of the too small appearance of sampling resistor.
Embodiment
As the physical circuit figure of Fig. 3, in technical scheme of the present invention, physical circuit comprises a rectifier bridge be made up of diode 1 and power factor controller below 2, power factor controller 2 mainly comprises multiplier 3, and resistance R1 and resistance R2 is connected on the outside of power factor controller 2, resistance R1 mono-terminated line voltage Vin, the other end of R1 is connected with one end of R2, and be connected to an input (multiplier sample line voltage port) of multiplier 3, be used for the other end ground connection of sample line voltage, R2.Current source Ic output is connected on multiplier sample line voltage port, and flows to resistance R1 and R2.Multiplier 3 one input termination output voltage error amplifier Vcomp, the output of multiplier 3 is connected to load, load is uncertain, under different applied environments, will because of the difference of load, produce different impacts to the power supply input before rectifier bridge, the intermodulation distortion alleged by the present invention just here embodies.
If the gain of multiplier 3 is the output voltage of K, multiplier 3
(during application, R1 is far longer than R2, and above formula ignores R1)
In traditional THD optimisation technique, multiplier exports
From above two equatioies, after adding electric current I c, the output of multiplier 3 introduces an additive factor
be the offset voltage that the present invention produces at multiplier outputs, the multiplier output offset voltage produced by this additive factor replaces the fixing offset voltage Voffset in traditional THD optimisation technique added by multiplier outputs, reaches the object of optimization system THD.
The size that the offset voltage introduced of multiplier outputs can change line voltage sample resistance R1 and R2 by equal proportion regulates arbitrarily, in different application environment, the THD of system is adjusted to an optimal value.The adjustment of sampling resistor R1 and R2 and the current waveform relation of power input, as Fig. 4 and Fig. 5, are the excessive intermodulation distortions causing zero passage to be delayed of sampling resistor respectively, and the too small advanced zero passage intermodulation distortion caused of sampling resistor.So according to aforementioned theory, and the relation of sampling resistor size and power supply wave shape is known, input current can be adjusted to an ideal waveform state, overcome THD intermodulation distortion by adjustment sampling resistor.
Claims (1)
1. the harmonic distortion optimization method of a power factor controller, be applied in the power factor controlling system of critical conduction mode, described power factor controlling system comprises the harmonic distortion optimization circuit of power factor controller, the harmonic distortion optimization circuit of described power factor controller comprises the rectifier bridge and multiplier that are connected with input power, rectification bridge output end is connected with two sampling resistors, sampling resistor is above R1, sampling resistor is below R2, exports the sample line voltage input end being connected to multiplier between two sampling resistors; It is characterized in that: on the sample line voltage input end of multiplier, be also connected with the current source Ic that flows to sampling resistor R2 below, the output voltage of multiplier is
, the output of this multiplier introduces offset voltage, i.e. V
imbalance =KI
cr2Vcomp, wherein K represents multiplier gain, and Vcomp represents output voltage error amplifier value, and Vin represents line magnitude of voltage, and R1 is the resistance value of sampling resistor above, and R2 is the resistance value of sampling resistor below, I
cfor the current value of current source, this offset voltage, for optimizing harmonic distortion, realizes the adjustment to the offset voltage that multiplier exports by the adjustment of the resistance to two sampling resistors, meets the requirement optimizing harmonic distortion.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310225449.3A CN103296877B (en) | 2013-06-07 | 2013-06-07 | A kind of harmonic distortion optimization method of power factor controller and circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310225449.3A CN103296877B (en) | 2013-06-07 | 2013-06-07 | A kind of harmonic distortion optimization method of power factor controller and circuit |
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| Publication Number | Publication Date |
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| CN103296877A CN103296877A (en) | 2013-09-11 |
| CN103296877B true CN103296877B (en) | 2016-03-30 |
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| CN201310225449.3A Active CN103296877B (en) | 2013-06-07 | 2013-06-07 | A kind of harmonic distortion optimization method of power factor controller and circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106685207B (en) * | 2017-01-23 | 2019-04-05 | 昂宝电子（上海）有限公司 | Power control system and method with low input current total harmonic distortion |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202076926U (en) * | 2011-05-31 | 2011-12-14 | 凌太先 | Power factor correction (PFC) circuit with full voltage and high power factor |
| CN203278639U (en) * | 2013-06-07 | 2013-11-06 | 无锡华润矽科微电子有限公司 | Total harmonic distortion optimized circuit for power factor controller |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101026248B1 (en) * | 2004-09-21 | 2011-03-31 | 페어차일드코리아반도체 주식회사 | Power Factor Correction Circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202076926U (en) * | 2011-05-31 | 2011-12-14 | 凌太先 | Power factor correction (PFC) circuit with full voltage and high power factor |
| CN203278639U (en) * | 2013-06-07 | 2013-11-06 | 无锡华润矽科微电子有限公司 | Total harmonic distortion optimized circuit for power factor controller |
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Owner name: JIANGYIN SUNNY ORIENT TECHNOLOGY CO., LTD. Effective date: 20141117 |
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Effective date of registration: 20141117 Address after: 214135 Jiangsu city of Wuxi province Wuxi Linghu Taihu International Science Park Road No. 180 -22 Applicant after: Wuxi China Resources Semico Co., Ltd. Applicant after: Jiangyin Sunny Orient Technology Co., Ltd. Address before: 214135 Jiangsu city of Wuxi province Wuxi Linghu Taihu International Science Park Road No. 180 -22 Applicant before: Wuxi China Resources Semico Co., Ltd. |
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Address after: 214135 -6, Linghu Avenue, Wuxi Taihu international science and Technology Park, Wuxi, Jiangsu, China, 180 Patentee after: China Resources micro integrated circuit (Wuxi) Co., Ltd Address before: No.180-22, Linghu Avenue, Taihu International Science and Technology Park, Wuxi, Jiangsu, 214135 Patentee before: WUXI CHINA RESOURCES SEMICO Co.,Ltd. |