CN103281270B - Forecast decision feedback equalizer - Google Patents
Forecast decision feedback equalizer Download PDFInfo
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- CN103281270B CN103281270B CN201310201939.XA CN201310201939A CN103281270B CN 103281270 B CN103281270 B CN 103281270B CN 201310201939 A CN201310201939 A CN 201310201939A CN 103281270 B CN103281270 B CN 103281270B
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Abstract
The invention discloses a kind of forecast decision feedback equalizer, it comprises decision feedback equalization system, decision feedback equalization system comprises selector, d type flip flop and two adjustable threshold samplers, wherein, decision feedback equalization system is N cover, and N be more than or equal to 2 positive integer, two adjacent cover decision feedback equalization systems, the output of the d type flip flop of front a set of decision feedback equalization system is connected with the control end of the selector of rear a set of decision feedback equalization system, the output of the d type flip flop of last a set of decision feedback equalization system is connected with the control end of the selector of the most front a set of decision feedback equalization system, the frequency of often overlapping the control clock of decision feedback equalization system is that outside inputs frequency analog signal
and the phase place of often overlapping the control clock of decision feedback equalization system is all variant.Forecast decision feedback equalizer of the present invention is not needing to change on the basis of forecast decision feedback equalizer algorithm, by changing the frequency controlling clock, makes the analog signal of outside input can be chosen correctly and obtain correct equilibrium result.
Description
Technical field
The present invention relates to integrated circuit fields, relate more specifically to a kind of forecast decision feedback equalizer.
Background technology
In mobile communications, the finiteness of multipath effect and channel width and the imperfection of the characteristic of channel, cause inevitably producing intersymbol interference during transfer of data, become the principal element affecting communication quality; And the balancing technique of channel can eliminate intersymbol interference and noise, and reduce the error rate.Wherein DFF (DFE) is that a kind of very effective and widely used being used for is eliminated or reduced the measure of multi-path jamming.
Fig. 1 is the structural representation of forecast decision feedback equalizer of the prior art.As shown in Figure 1, existing forecast decision feedback equalizer comprises selector S, a d type flip flop D1 and two adjustable threshold sampler, two adjustable threshold samplers are respectively positive threshold value sampler D2 and negative threshold value sampler D3, the analog signal ADATA of outside input inputs to positive threshold value sampler D2 and negative threshold value sampler D3 respectively, and positive threshold value sampler D2, the clock control end of negative threshold value sampler D3 and d type flip flop D1 is connected with external clock respectively, external clock output clock pulse clk to positive threshold value sampler D2, the clock control end of negative threshold value sampler D3 and d type flip flop D1, and the frequency of clock pulse clk is identical with the analog signal ADATA that outside inputs, thus when the rising edge of clock pulse clk arrives, positive threshold value sampler D2 and negative threshold value sampler D3 samples to external analog signal ADATA, and signal DATA0 and the ADTA1 exported respectively after sampling, positive threshold value sampler D1 is connected with two inputs of selector S respectively with the output of negative threshold value sampler D2, the output of selector S is connected with the input of d type flip flop D3, thus signal DATA0 and the ADTA1 of selector S to input selects and output signal DATA, signal DATA is by the analog signal Dout of stable output after d type flip flop D3, separately, the output of d type flip flop D3 is connected with the control end of selector S, thus the signal Dout that previous judgement obtains is in order to the selection of controlled selector S to next signal.
From the forecast decision feedback equalizer shown in above-mentioned Fig. 1, sampled to inputting analog signal ADATA with positive threshold value sampler D2 and negative threshold value sampler D3 before obtaining previous judgement, positive threshold value sampler D2 the input analog signal level of sampler be greater than certain on the occasion of output just judgement be 1, negative threshold value sampler D3 the input analog signal level of sampler be less than certain negative value export just adjudicate be 0; And the threshold value of positive threshold value sampler D2 and negative threshold value sampler D3 is adjustable, thus make positive threshold value sampler D2 or negative threshold value sampler D3 can complete sampling to inputting analog signal ADATA.According to the previous judgement recovered (i.e. the signal of d type flip flop D3 output), selector S will select correct court verdict in DATA0 and ADTA1, abandons the result of another one mistake, and outputs signal DATA; And pass through the analog signal Dout of d type flip flop D3 stable output, and the analog signal Dout exported controls again the selection of next analog signal by selector S.
Fig. 2 is the sequential chart of the feedback loop of forecast decision feedback equalizer first shown in Fig. 1.Owing to being precomputed by forecast decision feedback equalizer for previous analog signal, therefore selector S only needs correct result to be selected by previous analog signal.As seen from Figure 2, owing to needing to utilize the signal Dout recovered to select, different analog signal DATA0, DATA1 that two threshold value samplers export is adjudicated; Because the frequency of clock pulse clk is identical with the analog signal ADATA that outside inputs, therefore, Dout must be stabilized to its end value before next rising edge clock arrives, and namely the total delay of first feedback path must meet formula (1), correct equilibrium result could be chosen.
T
mux+T
cq＜1UI（1）
Wherein:
T
mux---the delay of MUX;
T
cq---the transmission delay of d type flip flop.
But when carrying out high speed data transfer in the communications, (1) formula is difficult to set up; When the frequency of the analog signal ADATA such as inputted is 10G, UI=100ps, under the current the fastest prevailing technology that can reach, selector postpones about Tmux=75ps, d type flip flop data setup time about Tcq=90ps.75ps+90ps>100ps, therefore said structure selects correct equilibrium result by being difficult to.
Therefore, be necessary to provide a kind of forecast decision feedback equalizer of improvement to overcome above-mentioned defect.
Summary of the invention
The object of this invention is to provide a kind of forecast decision feedback equalizer, forecast decision feedback equalizer of the present invention is not needing to change on the basis of forecast decision feedback equalizer algorithm, by the algorithm using frequency reducing multi-phase clock over-sampling to realize forecast decision feedback equalizer, make the analog signal of outside input can be chosen correctly and obtain correct equilibrium result.
For achieving the above object, the invention provides a kind of forecast decision feedback equalizer, described forecast decision feedback equalizer, comprise decision feedback equalization system, described decision feedback equalization system comprises selector, d type flip flop and two adjustable threshold samplers, two adjustable threshold samplers are respectively positive threshold value sampler and negative threshold value sampler, the analog signal of outside input inputs to described positive threshold value sampler and negative threshold value sampler respectively, and described positive threshold value sampler is connected with control clock respectively with the clock control end of negative threshold value sampler, described positive threshold value sampler is connected with the input of selector respectively with the output of negative threshold value sampler, the output of described selector is connected with the input of described d type flip flop, the clock control end of described d type flip flop is connected with control clock, and the output of described d type flip flop is connected with the control end of described selector, wherein, described decision feedback equalization system is N cover, and N be more than or equal to 2 positive integer, the adjacent described decision feedback equalization system of two covers, the output of the d type flip flop of front a set of decision feedback equalization system is connected with the control end of the selector of rear a set of decision feedback equalization system, the output of the d type flip flop of last a set of decision feedback equalization system is connected with the control end of the selector of the most front a set of decision feedback equalization system, the frequency of often overlapping the control clock of decision feedback equalization system is that outside inputs frequency analog signal
and the phase place of often overlapping the control clock of decision feedback equalization system is all variant.
Preferably, the phase of the every control clock of adjacent two cover decision feedback equalization systems
the phase of the phase place of the control clock of last a set of decision feedback equalization system and the control clock of the most front a set of decision feedback equalization system
t is the cycle controlling clock.
Compared with prior art, forecast decision feedback equalizer of the present invention due to described decision feedback equalization system be N cover, and N be more than or equal to 2 positive integer, and the frequency of often overlapping the control clock of decision feedback equalization system is outside input frequency analog signal
make forecast decision feedback equalizer of the present invention in the analog signal sampling processing procedure to input, only need the transmission delay of each selector and d type flip flop to meet Tmux+Tcq<N*UI and can select correct equilibrium result, and the transmission delay of each selector and d type flip flop will be made to meet above formula, described in relative set, the tricks N of decision feedback equalization system can realize; Therefore forecast decision feedback equalizer of the present invention is easy to realize, and can guarantee to select to obtain correct equilibrium result.
By following description also by reference to the accompanying drawings, the present invention will become more clear, and these accompanying drawings are for explaining the present invention.
Accompanying drawing explanation
Fig. 1 is the structural representation of forecast decision feedback equalizer of the prior art.
Fig. 2 is the sequential chart of the feedback loop of forecast decision feedback equalizer first shown in Fig. 1.
Fig. 3 is the structural representation of a forecast decision feedback equalizer of the present invention embodiment.
Fig. 4 is the sequential chart of the feedback loop of forecast decision feedback equalizer first shown in Fig. 3.
Embodiment
With reference now to accompanying drawing, describe embodiments of the invention, element numbers similar in accompanying drawing represents similar element.As mentioned above, the invention provides a kind of forecast decision feedback equalizer, forecast decision feedback equalizer of the present invention is not needing to change on the basis of forecast decision feedback equalizer algorithm, by the algorithm using frequency reducing multi-phase clock over-sampling to realize forecast decision feedback equalizer, make the analog signal of outside input can be chosen correctly and obtain correct equilibrium result.
Please refer to Fig. 3, Fig. 3 is the structural representation of a forecast decision feedback equalizer of the present invention embodiment.As shown in the figure, forecast decision feedback equalizer of the present invention comprises N and overlaps decision feedback equalization system, and N be more than or equal to 2 positive integer.Wherein, every suit decision feedback equalization system includes selector (being respectively S2, S4, S6, S8), d type flip flop (being respectively D12, D14, D16, D18) and two adjustable threshold samplers, and two adjustable threshold samplers are respectively positive threshold value sampler (being respectively D22, D24, D26, D28) and negative threshold value sampler (being respectively D32, D34, D36, D38); The analog signal ADATA of outside input inputs to each positive threshold value sampler (being respectively D22, D24, D26, D28) and negative threshold value sampler (being respectively D32, D34, D36, D38) respectively, and the clock control end of positive threshold value sampler, negative threshold value sampler and d type flip flop is connected with corresponding control clock respectively, each controls the clock control end of clock output clock pulse (being respectively clk2, clk4, clk6, clk8) to corresponding positive threshold value sampler, negative threshold value sampler and d type flip flop; And the frequency of each clock pulse clk2, clk4, clk6, clk8 is the analog signal ADATA frequency of outside input
thus when the rising edge of each clock pulse clk2, clk4, clk6, clk8 arrives, corresponding positive threshold value sampler and negative threshold value sampler are sampled to external analog signal ADATA, and signal vthp2, vthn2 of exporting respectively after sampling, vthp4, vthn4, vthp6, vthn6, vthp8, vthn8; Positive threshold value sampler is connected with the input of selector respectively with the output of negative threshold value sampler, the output of selector is connected with the input of d type flip flop, thus selector is to signal vthp2, vthn2 of input, vthp4, vthn4, vthp6, vthn6, vthp8, vthn8 carry out selecting and outputing signal OUT2, OUT4, OUT6, OUT8, and the signal that described selector exports is by the analog signal (being respectively Dout2, Dout4, Dout6, Dout8) of d type flip flop stable output.
Particularly, in the one embodiment of the present of invention shown in Fig. 3, N is 4, that is to say to comprise 4 cover decision feedback equalization systems in the forecast decision feedback equalizer of this embodiment, and apparently, in the specific embodiment of the present invention, N value is not limited to 4.In this embodiment, 4 cover decision feedback equalization systems are respectively first set decision feedback equalization system D2, the second cover decision feedback equalization system D4, the 3rd cover decision feedback equalization system D6 and the 4th cover decision feedback equalization system D8; And the frequency of the clock pulse clk2 that respectively cover decision feedback equalization system is corresponding, clk4, clk6, clk8 is the analog signal ADATA frequency of outside input
.Wherein, the positive threshold value sampler D22 of first set decision feedback equalization system D2 is connected with the input of selector S2 respectively with the output of negative threshold value sampler D32, and the output of selector S2 is connected with the input of d type flip flop D12; Annexation between above-mentioned each device, all identical in decision feedback equalization system D4, D6 and D8, in this no longer repeated description.In addition, in DFF of the present invention, the adjacent described decision feedback equalization system of two covers, the output of the d type flip flop of front a set of decision feedback equalization system is connected with the control end of the selector of rear a set of decision feedback equalization system, and the output of the d type flip flop of last a set of decision feedback equalization system is connected with the control end of the selector of the most front a set of decision feedback equalization system; Particularly, the control end that the output and second of the d type flip flop D12 of first set decision feedback equalization system D2 overlaps the selector S4 of decision feedback equalization system D4 is connected, and the control end that the output and the 3rd of the d type flip flop D14 of the second cover decision feedback equalization system D4 overlaps the selector S6 of decision feedback equalization system D6 is connected; Accordingly, the follow-up output that other respectively overlaps the d type flip flop of decision feedback equalization system is connected with the selector of lower a set of decision feedback equalization system, and to the last the output of the d type flip flop D18 of the 4th cover decision feedback equalization system D8 is connected with the control end of the selector S2 of first set decision feedback equalization system D2; Thus the selection of the selector of a set of decision feedback equalization system operates under the signal controlling of the d type flip flop of front a set of decision feedback equalization system output, and the selection operation of the selector of the most front a set of decision feedback equalization system (i.e. D2) of signal controlling that the d type flip flop of last a set of decision feedback equalization system (i.e. D8) exports.
Please combine again with reference to figure 4, describe the course of work of first set decision feedback equalization system D2, wherein in Fig. 4, eliminate the feedback sequential that the second cover decision feedback equalization system D4 and the 3rd overlaps decision feedback equalization system D6; In figure, Clk_send is the tranmitting data register of high-speed serial data, and external analog signal ADATA sends when the rising edge of this clock.When the rising edge of clock pulse clk2 arrives, positive threshold value sampler D22 and negative threshold value sampler D32 samples to inputting analog signal ADATA, positive threshold value sampler D22 the input analog signal level of sampler be greater than certain on the occasion of output just judgement be 1, negative threshold value sampler D32 the input analog signal level of sampler be less than certain negative value export just adjudicate be 0; Selector S2 is according to the court verdict (i.e. the signal of the d type flip flop D8 output of the 4th cover decision feedback equalization system) of the previous round recovered, selector S selects correct court verdict by its input signal vthp2 and vthn2, abandon the result of another one mistake, and pass through the analog signal Dout2 of d type flip flop D2 stable output, and the analog signal Dout2 exported controls again the selection of next analog signal by selector S4.Correspondingly, due to the phase of the control clock of each cover decision feedback equalization system of the present invention
the phase of the phase place of the control clock of last a set of decision feedback equalization system and the control clock of the most front a set of decision feedback equalization system
t is the cycle controlling clock, and the time that the rising edge of the clock pulse of each control clock is arrived also all differs
be in the present embodiment
similarly perform aforesaid operations respectively when the rising edge that it controls the clock pulse of clock arrives, to the last a set of decision feedback equalization system also executes aforesaid operations, and namely forecast decision feedback equalizer of the present invention completes one and takes turns feedback procedure.
From the above, whole forecast decision feedback equalizer will realize selecting correct equilibrium result, the transmission delay of each selector and d type flip flop is only needed to meet Tmux+Tcq<N*UI, thus do not need to change forecast decision feedback equalizer algorithm basis on, above formula can be made to be easy to realize by regulating the tricks arranging decision feedback equalization system N, thus make forecast decision feedback equalizer of the present invention correctly select correct equilibrium result, and whole forecast decision feedback equalizer is easy to realize.
More than in conjunction with most preferred embodiment, invention has been described, but the present invention is not limited to the embodiment of above announcement, and should contain various carry out according to essence of the present invention amendment, equivalent combinations.
Claims (1)
1. a forecast decision feedback equalizer, comprise decision feedback equalization system, described decision feedback equalization system comprises selector, d type flip flop and two adjustable threshold samplers, two adjustable threshold samplers are respectively positive threshold value sampler and negative threshold value sampler, the analog signal of outside input inputs to described positive threshold value sampler and negative threshold value sampler respectively, and described positive threshold value sampler is connected with control clock respectively with the clock control end of negative threshold value sampler, described positive threshold value sampler is connected with the input of selector respectively with the output of negative threshold value sampler, the output of described selector is connected with the input of described d type flip flop, the clock control end of described d type flip flop is connected with control clock, and the output of described d type flip flop is connected with the control end of described selector, it is characterized in that, described decision feedback equalization system is N cover, and N be more than or equal to 2 positive integer, the adjacent described decision feedback equalization system of two covers, the output of the d type flip flop of front a set of decision feedback equalization system is connected with the control end of the selector of rear a set of decision feedback equalization system, the output of the d type flip flop of last a set of decision feedback equalization system is connected with the control end of the selector of the most front a set of decision feedback equalization system, the frequency of often overlapping the control clock of decision feedback equalization system is that outside inputs frequency analog signal
and the phase of the every control clock of adjacent two cover decision feedback equalization systems
the phase of the phase place of the control clock of last a set of decision feedback equalization system and the control clock of the most front a set of decision feedback equalization system
t is the cycle controlling clock.
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| US8233523B2 (en) * | 2008-06-20 | 2012-07-31 | Fujitsu Limited | Multidimensional asymmetric bang-bang control |
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