CN103278248A - Single-photon detector dead time control device - Google Patents
Single-photon detector dead time control device Download PDFInfo
- Publication number
- CN103278248A CN103278248A CN201210584935XA CN201210584935A CN103278248A CN 103278248 A CN103278248 A CN 103278248A CN 201210584935X A CN201210584935X A CN 201210584935XA CN 201210584935 A CN201210584935 A CN 201210584935A CN 103278248 A CN103278248 A CN 103278248A
- Authority
- CN
- China
- Prior art keywords
- module
- signal
- flip flop
- dead time
- type flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Photometry And Measurement Of Optical Pulse Characteristics (AREA)
- Measurement Of Unknown Time Intervals (AREA)
Abstract
The invention discloses a single-photon detector dead time control device. The device comprises a main control module, an avalanche signal screening module, a D flip flop pulse shaping module, a D flip flop frequency division module and a gating module. The device is characterized in that the main control module is electrically connected with the D flip flop pulse shaping module and outputs a first dead time control signal to the D flip flop pulse shaping module; the D flip flop pulse shaping module is electrically connected with the gating module and outputs a second dead time control signal to the gating module; the gating module is electrically connected with the avalanche signal screening module and outputs a synchronous enable signal to the avalanche signal screening module; the avalanche signal screening module, the D flip flop pulse shaping module and the D flip flop frequency division module are sequentially and electrically connected with one another; and the D flip flop frequency division module is electrically connected with the main control module and outputs a photon detection signal to the main control module. The device is stable and reliable and responds quickly.
Description
Technical field
The present invention relates to a kind of dead time controller of the single-photon detector for the two-forty optical signal detection, relate in particular to a kind of single-photon detector dead time control device.
Background technology
The control of single-photon detector dead time refers to that producing two path control signal by the dead time control circuit after APD detects a light signal makes gating circuit and avalanche signal treatment circuit enter the disable state, and this moment, single-photon detector was to produce any detection counting.After through one period dead time, the dead time control circuit can produce two path control signal again and enable gating circuit and avalanche signal treatment circuit, and this moment, single-photon detector entered normal operating conditions again.In other words, single-photon detector is exactly the highly sensitive detecting device that utilizes the avalanche effect of avalanche photo diode (APD) to make photocurrent obtain doubling.Existing single-photon detector circuit part is made up of gating circuit and avalanche signal treatment circuit substantially, and adopts the dead time control circuit to suppress the secret mark number that the afterpulse effect causes.Along with the development of single-photon detecting survey technology, people require also more and more higher to the detection rate of single-photon detector.The speed of the post processing circuitry of single-photon detector is also just in urgent need to be improved at present.In post processing circuitry, the dead time control circuit is also very big to the influence of the detection rate of detector and detection efficiency, and traditional dead time control circuit response speed is slow, can not satisfy the requirement of high detection rate.Therefore unusual a kind of dead time control circuit that can be applicable to high detection rate of demand.Traditional dead time control circuit scheme as shown in Figure 1, it is traditional dead time control procedure, its process is after light signal causes the snowslide of APD pipe, the avalanche signal treatment circuit can be screened faint avalanche signal out again and deliver to main control chip FPGA through after a series of processing, and then by FPGA generation two-way dead time control signal, one the tunnel is used for the control gate control circuit, and another road is used for control avalanche signal treatment circuit (frame of broken lines part).Fig. 2 is traditional dead time control avalanche signal treatment circuit sketch, and wherein the first dead time control signal is produced by FPGA just, has omitted dead time control signal 2 here, and its principle also is to produce output by FPGA with the first dead time control signal.
Summary of the invention
The object of the present invention is to provide a kind of reliable and stable, single-photon detector dead time control device that response speed is fast.
For realizing above-mentioned technical purpose problem, the technical scheme that the present invention takes is: single-photon detector dead time control device comprises main control module, avalanche signal examination module, d type flip flop shaping pulse module, d type flip flop frequency division module and gate module; It is characterized in that: main control module is electrically connected with d type flip flop shaping pulse module and the first dead time control signal is exported to d type flip flop shaping pulse module; D type flip flop shaping pulse module is electrically connected and exports the second dead time control signal with the gate module and gives the gate module; The gate module is electrically connected and synchronous enabled signal is exported to avalanche signal screen module with avalanche signal examination module; Avalanche signal is screened module, d type flip flop shaping pulse module and d type flip flop frequency division module and is electrically connected successively; The d type flip flop frequency division module is electrically connected with main control module and the output photon detectable signal is given main control module.
Compared with prior art, benefit analysis of the present invention is as follows:
1, as shown in Figure 3 and Figure 4, synchronous enabled signal has been added in avalanche signal has screened on the comparer, rather than on d type flip flop 1.Because when light signal and gating pulse are added to the APD pipe simultaneously, the time that the APD pipe really begins snowslide is uncertain, it may appear at any moment in the gatewidth time, this just makes that sending into the avalanche signal of screening comparer shakes in the certain hour scope, if adding, comparer do not enable control, the pulse of comparer output also will be shaken so, because its width has only the burst pulse of hundreds of psec.When the two-forty optical signal detection, this shake will seriously cause miscount.The solution that the present invention adopts is to observe avalanche signal pulse overlap district by oscillograph, then synchronous enabled signal is snapped to this overlay region in time, only meeting output when synchronous enabled signal rising edge arrives of comparer so, output signal will be a signal that pulse front edge is stable like this.
Can see very intuitively from Fig. 3 and Fig. 4 that 2, the generation of dead time control signal of the present invention also is different from traditional circuit.Traditional way is just to produce two-way dead time control signal after must detecting detectable signal at final main control chip FPGA to deliver to gating circuit and avalanche signal treatment circuit respectively.Obviously when taking place just can enter the disable state through a bigger time-delay detector after avalanche signal is screened output, well imagine, circuit did not also have enough time to enter disable state (dead time state) after an avalanche signal produced when the two-forty optical signal detection, next avalanche process just has been triggered, at this moment the counting of final main control chip just is difficult to avoid several influence of calculating mentally that afterpulse produces, the calculating mentally number and also will increase greatly of detector.Way in the circuit of the present invention is to screen output signal to d type flip flop 1 when comparer produces snowslide, d type flip flop 1 upgrade the output back just immediately wherein one tunnel output signal deliver to gating circuit as dead time control signal 2 and make gating circuit enter the disable state.We can know from Fig. 3 and Fig. 4, after d type flip flop 1 has responded a snowslide examination output signal, even next avalanche signal arrival d type flip flop 2 can not upgrade output yet, this moment, the avalanche signal treatment circuit also entered the disable state in fact in other words, at this moment have only and export the first dead time control signal when main control chip and make it produce set for d type flip flop 2, the avalanche signal treatment circuit just can enter enabled state again.Clearly this new-type circuit is to screen the output back and just can make detector enter the disable state immediately detecting avalanche signal, just exports the dead time control signal conversely after must detecting detectable signal at final main control chip FPGA unlike traditional circuit to make detector enter the disable state.Identical is that two kinds of schemes all are just to export the dead time control signal at FPGA behind the full dead time value T of meter to enable detector again.
3, all need d type flip flop to carry out the shaping of RC circuit reset in the traditional circuit and could make that pulse width reaches requirement.We know that the RC circuit reset has its intrinsic shortcoming, and owing to RC circuit meeting fast charging and discharging, this brings the malreduction problem probably when the two-forty signal transmits, and circuit reliability is not high.The present invention adopts the mode of d type flip flop frequency division to obtain enough big pulse width, and makes the detection counting mode of this moment become an i.e. expression of level upset of every generation to obtain one and survey and count.Analysis chart 3 and Fig. 4 export the pulse width of high-low level as can be known more than or equal to the dead time value, this means that the time of surveying the counting use was included in the necessary dead time of detector circuit itself, do not have extra holding time axle, survey the time that counting has all taken a count pulse separately unlike traditional circuit at every turn.This new-type circuit can reliably be applicable to the two-forty optical signal detection effectively thus.
In a word, the single-photon detector dead time control device that this single-photon detector dead time control device is reliable and stable, response speed is fast.
Description of drawings
Fig. 1 is dead time control circuit block diagram in the prior art.
Fig. 2 is dead time control avalanche signal treatment circuit synoptic diagram traditional in the prior art.
Fig. 3 is circuit block diagram of the present invention.
Fig. 4 is circuit diagram of the present invention.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described further.
Embodiment
Embodiment 1
Referring to Fig. 3 and Fig. 4, this single-photon detector dead time control device comprises main control module, avalanche signal examination module, d type flip flop shaping pulse module, d type flip flop frequency division module and gate module; It is characterized in that: main control module is connected with d type flip flop shaping pulse module point and the first dead time control signal is exported to d type flip flop shaping pulse module; D type flip flop shaping pulse module is electrically connected and exports the second dead time control signal with the gate module and gives the gate module; The gate module is electrically connected and synchronous enabled signal is exported to avalanche signal screen module with avalanche signal examination module; Avalanche signal is screened module, d type flip flop shaping pulse module and d type flip flop frequency division module and is electrically connected successively; The d type flip flop frequency division module is connected with main control module point and the output photon detectable signal is given main control module.
This single-photon detector dead time control device has bigger improvement at signal processing method, and at first, this single-photon detector dead time control device has avoided utilizing the RC shaping mode of d type flip flop; Again, synchronous enabled signal has been added in the avalanche signal examination and has compared on---having adopted the high-speed comparator of the single power supply of littler encapsulation---, rather than is added on the d type flip flop; At last, the output of final detectable signal is not by d type flip flop shaping mode, but by d type flip flop frequency division mode, make the output counting become to detect level that the i.e. expression of upset takes place at every turn and obtain a photon detection counting, rather than traditional represent to obtain a photon detection counting to detect a pulse signal at every turn.
In the present embodiment, as shown in Figure 3 and Figure 4, synchronous enabled signal has been added in avalanche signal has screened on the comparer, rather than on d type flip flop 1.Because when light signal and gating pulse are added to the APD pipe simultaneously, the time that the APD pipe really begins snowslide is uncertain, it may appear at any moment in the gatewidth time, this just makes that sending into the avalanche signal of screening comparer shakes in the certain hour scope, if adding, comparer do not enable control, the pulse of comparer output also will be shaken so, because its width has only the burst pulse of hundreds of psec.When the two-forty optical signal detection, this shake will seriously cause miscount.The solution that the present invention adopts is to observe avalanche signal pulse overlap district by oscillograph, then synchronous enabled signal is snapped to this overlay region in time, only meeting output when synchronous enabled signal rising edge arrives of comparer so, output signal will be a signal that pulse front edge is stable like this.
Can see very intuitively that from Fig. 3 and Fig. 4 the generation of dead time control signal of the present invention also is different from traditional circuit.Traditional way is just to produce two-way dead time control signal after must detecting detectable signal at final main control chip FPGA to deliver to gating circuit and avalanche signal treatment circuit respectively.Obviously when taking place just can enter the disable state through a bigger time-delay detector after avalanche signal is screened output, well imagine, avalanche signal produces the back circuit disable state that also do not have enough time to enter when the two-forty optical signal detection, it is the dead time state, next avalanche process just has been triggered, at this moment the counting of final main control chip just is difficult to avoid several influence of calculating mentally that afterpulse produces, the calculating mentally number and also will increase greatly of detector.Way in the circuit of the present invention is to screen output signal to d type flip flop when comparer produces snowslide, d type flip flop upgrade the output back just immediately wherein one tunnel output signal second deliver to gating circuit as the dead time control signal and make gating circuit enter the disable state.We can know from Fig. 3 and Fig. 4, after d type flip flop has responded a snowslide examination output signal, even next avalanche signal arrival d type flip flop can not upgrade output yet, this moment, the avalanche signal treatment circuit also entered the disable state in fact in other words, at this moment have only and export the first dead time control signal when main control chip and make it produce set to d type flip flop, the avalanche signal treatment circuit just can enter enabled state again.Clearly this new-type circuit is to screen the output back and just can make detector enter the disable state immediately detecting avalanche signal, just exports the dead time control signal conversely after must detecting detectable signal at final main control chip FPGA unlike traditional circuit to make detector enter the disable state.Identical is that two kinds of schemes all are just to export the dead time control signal at FPGA behind the full dead time value T of meter to enable detector again.
All need d type flip flop to carry out the shaping of RC circuit reset in the traditional circuit and could make that pulse width reaches requirement.We know that the RC circuit reset has its intrinsic shortcoming, and owing to RC circuit meeting fast charging and discharging, this brings the malreduction problem probably when the two-forty signal transmits, and circuit reliability is not high.The present invention adopts the mode of d type flip flop frequency division to obtain enough big pulse width, and makes the detection counting mode of this moment become an i.e. expression of level upset of every generation to obtain one and survey and count.Analysis chart 3 and Fig. 4 export the pulse width of high-low level as can be known more than or equal to the dead time value, this means that the time of surveying the counting use was included in the necessary dead time of detector circuit itself, do not have extra holding time axle, survey the time that counting has all taken a count pulse separately unlike traditional circuit at every turn.This new-type circuit can reliably be applicable to the two-forty optical signal detection effectively thus.
In a word, the single-photon detector dead time control device that this single-photon detector dead time control device is reliable and stable, response speed is fast.
Claims (1)
1. a single-photon detector dead time control device comprises main control module, avalanche signal examination module, d type flip flop shaping pulse module, d type flip flop frequency division module and gate module; It is characterized in that: main control module is electrically connected with d type flip flop shaping pulse module and the first dead time control signal is exported to d type flip flop shaping pulse module; D type flip flop shaping pulse module is electrically connected and exports the second dead time control signal with the gate module and gives the gate module; The gate module is electrically connected and synchronous enabled signal is exported to avalanche signal screen module with avalanche signal examination module; Avalanche signal is screened module, d type flip flop shaping pulse module and d type flip flop frequency division module and is electrically connected successively; The d type flip flop frequency division module is electrically connected with main control module and the output photon detectable signal is given main control module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210584935.XA CN103278248B (en) | 2012-12-30 | 2012-12-30 | Single-photon detector dead time control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210584935.XA CN103278248B (en) | 2012-12-30 | 2012-12-30 | Single-photon detector dead time control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103278248A true CN103278248A (en) | 2013-09-04 |
| CN103278248B CN103278248B (en) | 2016-01-13 |
Family
ID=49060834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210584935.XA Active CN103278248B (en) | 2012-12-30 | 2012-12-30 | Single-photon detector dead time control device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103278248B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105067522A (en) * | 2015-08-05 | 2015-11-18 | 宁波工程学院 | Quasi real-time photomultiplier background deduction device and method |
| CN108828616A (en) * | 2018-06-12 | 2018-11-16 | 南京理工大学 | The photon counting laser radar and constant false alarm control method of monopulse ranging can be achieved |
| CN110987201A (en) * | 2019-12-20 | 2020-04-10 | 国开启科量子技术(北京)有限公司 | Method and device for realizing single photon detector dead time control circuit |
| CN112945379A (en) * | 2021-02-03 | 2021-06-11 | 中国科学院长春光学精密机械与物理研究所 | System for setting dead time and filtering noise of single photon detector |
| CN114235175A (en) * | 2021-12-27 | 2022-03-25 | 中国人民解放军战略支援部队信息工程大学 | Single photon sequential detection array, system, method, device and storage medium |
| CN116087628A (en) * | 2023-04-10 | 2023-05-09 | 国仪量子(合肥)技术有限公司 | Measurement method, device and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2466299A (en) * | 2008-12-19 | 2010-06-23 | Toshiba Res Europ Ltd | Single photon detection using variable delay component to cancel periodic signal variations |
| CN201828343U (en) * | 2010-09-27 | 2011-05-11 | 南通墨禾量子科技发展有限公司 | Optical-pulse synchronous single-photon detector with high time resolution and low noise |
| CN102230828A (en) * | 2011-04-07 | 2011-11-02 | 华东师范大学 | Method for detecting gigahertz single photon with low time jitter and low noise |
| JP2012013600A (en) * | 2010-07-02 | 2012-01-19 | Mitsubishi Electric Corp | Single photon detector |
| CN203249696U (en) * | 2012-12-30 | 2013-10-23 | 安徽问天量子科技股份有限公司 | Single-photon detector dead time controlling device |
-
2012
- 2012-12-30 CN CN201210584935.XA patent/CN103278248B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2466299A (en) * | 2008-12-19 | 2010-06-23 | Toshiba Res Europ Ltd | Single photon detection using variable delay component to cancel periodic signal variations |
| JP2012013600A (en) * | 2010-07-02 | 2012-01-19 | Mitsubishi Electric Corp | Single photon detector |
| CN201828343U (en) * | 2010-09-27 | 2011-05-11 | 南通墨禾量子科技发展有限公司 | Optical-pulse synchronous single-photon detector with high time resolution and low noise |
| CN102230828A (en) * | 2011-04-07 | 2011-11-02 | 华东师范大学 | Method for detecting gigahertz single photon with low time jitter and low noise |
| CN203249696U (en) * | 2012-12-30 | 2013-10-23 | 安徽问天量子科技股份有限公司 | Single-photon detector dead time controlling device |
Non-Patent Citations (2)
| Title |
|---|
| 冯雪冬: "红外波段单光子探测器及其在量子通信领域中的应用", 《光子技术》, no. 2, 30 June 2006 (2006-06-30) * |
| 权菊香: "Si-APD单光子探测器的全主动抑制技术", 《激光与光电子进展》, vol. 43, no. 5, 31 May 2006 (2006-05-31) * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105067522A (en) * | 2015-08-05 | 2015-11-18 | 宁波工程学院 | Quasi real-time photomultiplier background deduction device and method |
| CN108828616A (en) * | 2018-06-12 | 2018-11-16 | 南京理工大学 | The photon counting laser radar and constant false alarm control method of monopulse ranging can be achieved |
| CN108828616B (en) * | 2018-06-12 | 2022-06-28 | 南京理工大学 | Photon counting laser radar capable of realizing monopulse ranging and constant false alarm control method |
| CN110987201A (en) * | 2019-12-20 | 2020-04-10 | 国开启科量子技术(北京)有限公司 | Method and device for realizing single photon detector dead time control circuit |
| CN112945379A (en) * | 2021-02-03 | 2021-06-11 | 中国科学院长春光学精密机械与物理研究所 | System for setting dead time and filtering noise of single photon detector |
| CN112945379B (en) * | 2021-02-03 | 2024-03-12 | 中国科学院长春光学精密机械与物理研究所 | System for dead time setting and noise filtering of single photon detector |
| CN114235175A (en) * | 2021-12-27 | 2022-03-25 | 中国人民解放军战略支援部队信息工程大学 | Single photon sequential detection array, system, method, device and storage medium |
| CN116087628A (en) * | 2023-04-10 | 2023-05-09 | 国仪量子(合肥)技术有限公司 | Measurement method, device and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103278248B (en) | 2016-01-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103278248A (en) | Single-photon detector dead time control device | |
| CN103148950B (en) | Integrated gating active quenching/restoring circuit | |
| CN203249696U (en) | Single-photon detector dead time controlling device | |
| Frach et al. | The digital silicon photomultiplier—System architecture and performance evaluation | |
| CN105652259B (en) | Laser ranging readout sequence circuit and method based on Geiger mode angular position digitizer (APD) array | |
| CN102760052B (en) | Based on stochastic source and the random number extracting method of photon room and time randomness | |
| CN103505236B (en) | Time-to-digital converter for medical imaging system | |
| EP3367131A1 (en) | A higher pixel density histogram time of flight sensor | |
| CN100458383C (en) | Method for collecting snowslide signal of APD single photon detector | |
| CN103698770A (en) | Multi-channel laser echo time measurement system based on FPGA (Field Programmable Gate Array) chip | |
| CN107806931A (en) | Gate complementary type Photo Counting System | |
| CN104199117B (en) | A kind of infrared and ultraviolet composite flame detecting device and its detection method | |
| CN101871968A (en) | Reliable time scale pulse measurement method and measurement device thereof | |
| CN108761557B (en) | A kind of chiasma type light curtain detection device based on FPGA | |
| CN105245203B (en) | High-precision low-speed clock duty ratio detecting system and method | |
| CN102998008A (en) | Symmetrical double-avalanche-photo-diode (APD) balanced near-infrared photon detector | |
| CN105606232A (en) | Optical signal detection realization method and system | |
| CN108036861B (en) | A kind of single-photon detector of shared digital quantizer | |
| CN209069421U (en) | A kind of test device of single-photon detector | |
| CN109219758A (en) | Optical sensor, electronic equipment | |
| CN103759840A (en) | Semiconductor infrared single-photon detector snow slide signal screening device and method | |
| CN103383545A (en) | High-speed miniature pulse signal collecting circuit | |
| CN111504482B (en) | Single photon detection device and method capable of restraining back pulse | |
| CN109946706A (en) | Optical sensor and electronic equipment | |
| CN104881268A (en) | Optical photon random source device and random order extraction method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: 241003 No. 12, Zhanghe Road, hi tech Zone, Anhui, Wuhu Patentee after: Anhui Asky Quantum Technology Co., Ltd. Address before: 241002 Anhui science and technology innovation public service center, Wuhu national hi tech Zone, Yijiang Patentee before: Anhui Asky Quantum Technology Co., Ltd. |