CN103269231A - Broadcast channel (BCH) code error-detecting correction method and circuit as well as fault-tolerant storage device - Google Patents

Abstract

The invention provides a broadcast channel (BCH) code error-detecting correction method and circuit as well as a fault-tolerant storage device. The method comprises the following steps of: calculating a syndrome to be compared of a BCH data group to be checked according to a supervision matrix of the BCH data group to be checked subjected to BCH encoding; if the syndrome to be compared is not 0, comparing the syndrome to be compared with multiple standard syndromes, and correcting the corresponding data in the BCH data group to be checked based on the standard syndromes with the minimum data bits different from the syndrome to be compared and minimum specified error bits. Compared with the original correction capacity of the BCH codes, the BCH error-detecting correction method can utilize the check codes to the greatest degree, and the correction capacity is improved; and moreover, the BCH code error-detecting correction circuit can consist of a pure logic circuit, a clock is not required, only gate delay exists, and the method is applied to the condition that a serial peripheral interface (SPI) and the like have special requirements on a timing sequence.

Description

BCH code EDC error detect correction method, circuit and fault tolerant memory

Technical field

The present invention relates to field of data storage, particularly relate to a kind of BCH code EDC error detect correction method, circuit and fault tolerant memory.

Background technology

Phase transition storage is a kind of semiconductor high resistant characteristic and technology of realizing storage of the metal low-resistance characteristic during crystalline state when utilizing the phase-change material amorphous state, and its reliability is considered from three aspects usually: data keep, i.e. the ability of memory cells maintain numerical value; Endurance, namely memory cell is for the endurance of read-write number of times; Read-write is disturbed, namely chip when read-write for the interference of memory cell.Wherein, the data of phase transition storage keep all depending on storage medium itself with endurance, and the read-write interference is then relevant with array structure and the read-write electric current that provides.Read-write disturbs the inefficacy cause that multiple reason is also arranged, and common have write operation to cause closing on the unit to be affected, and during read operation, material internal defect or pollution cause temperature to give birth to the effect of writing from volume increase, destroy storage data etc.

For reducing above possible inefficacy, improve the reliability of memory, detect and correct for a small amount of random error and can further promote the storage accuracy rate, therefore, press for the reliability that error-correcting code circuit (ECC) improves memory is set.

BCH code is an important subclass in the cyclic code, and it has the ability of entangling a plurality of random errors, and tight Algebraic Structure is arranged, and is a most thorough class sign indicating number of studying at present.BCH code satisfies formula

Wherein m is the figure place that needs the data of storage, and k is the figure place of checking data, and t is maximum error code figure places that coding can be corrected, and for the m and the t that fix, the k that satisfies formula seldom can make the equal sign establishment, and the figure place that can correct also only limits to the t position and below the t position.Have many efficient decoding schemes that become system now based on Bose-Chaudhuri-Hocquenghem Code, for taking full advantage of the characteristic of its circulation, the implementations that adopt serial more, can there be certain clock delay thus, a kind of comparatively typical implementation method is computing syndrome, adopt the gloomy algorithm of Peter to obtain wrong multinomial subsequently, the Yong Qianshi search circuit obtains errors present and corrects again.

Yet the typical decoding scheme of this kind is difficult to be applicable to the memory that sequential is had special requirement owing to there is clock delay.

Summary of the invention

The shortcoming of prior art the object of the present invention is to provide a kind of BCH code EDC error detect correction method and circuit in view of the above, under the assurance of realization to the t position error correction of BCH code, entangles the above mistake in a part of t position, and wherein, t is the maximum error code figure places that can correct.

Another object of the present invention is to provide a kind of fault tolerant memory.

Reach other relevant purposes for achieving the above object, the invention provides a kind of BCH code EDC error detect correction method, it comprises at least:

1) based on the syndrome to be compared of calculating described BCH data group to be tested through the check matrix of the BCH data group to be tested of Bose-Chaudhuri-Hocquenghem Code;

2) if described syndrome to be compared is not 0, then described syndrome to be compared and a plurality of standard correction are compared, and proofread and correct corresponding data in the described BCH data group to be tested based on the minimum and specified wrong figure place of the number of data bits different with described syndrome to be compared also minimum standard correction.

The present invention also provides a kind of BCH code EDC error detect correction circuit, and it comprises at least:

Generative circuit is for the syndrome to be compared of calculating described BCH data group to be tested based on the check matrix that passes through the BCH data group to be tested of Bose-Chaudhuri-Hocquenghem Code;

Error correction circuit, be used for if described syndrome to be compared is not 0, then described syndrome to be compared and a plurality of standard correction are compared, and proofread and correct corresponding data in the described BCH data group to be tested based on the minimum and specified wrong figure place of the number of data bits different with described syndrome to be compared also minimum standard correction.

The present invention also provides a kind of fault tolerant memory, and it comprises at least:

Storage array;

The read-write control unit that is connected with described storage array;

Based on the coding unit of Bose-Chaudhuri-Hocquenghem Code, be used for data to be stored are carried out sending into described read-write control unit behind the Bose-Chaudhuri-Hocquenghem Code;

Aforesaid BCH code EDC error detect correction circuit is connected with described read-write control unit, is used for the data that described read-write control unit is read are carried out exporting after the error correction;

Interface unit is connected with described coding unit and BCH code EDC error detect correction circuit respectively, and the data to be stored that are used for inserting are sent into described coding unit and carried out Bose-Chaudhuri-Hocquenghem Code and the data after the error correction of described BCH code EDC error detect correction circuit are exported.

As mentioned above, BCH code EDC error detect correction method of the present invention, circuit and fault tolerant memory have following beneficial effect: can maximally utilise check digit, satisfy formula

Prerequisite under, wherein m is the figure place that needs the data of storage, k is the figure place of check digit, maximum error code figure places that the t coding can be corrected are entangled under the assurance of t dislocation finishing BCH code, entangle the mistake more than a part of t position; And circuit can be realized with the form of pure logic, does not contain clock, only has gate delay, is fit to be applied to SPI interface and so on has special requirement to sequential situation.

Description of drawings

Fig. 1 is shown as the flow chart of BCH code EDC error detect correction method of the present invention.

Fig. 2 is shown as BCH code EDC error detect correction circuit diagram of the present invention.

Fig. 3 is shown as fault tolerant memory schematic diagram of the present invention.

The element numbers explanation

1 BCH code EDC error detect correction circuit

11 generative circuits

12 comparison circuits

13 error correction circuits

2 fault tolerant memories

21 storage arrays

22 read-write control units

23 coding units

24 BCH code EDC error detect correction circuit

25 interface units

S1～S2 step

Embodiment

Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be used by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.

See also Fig. 1 to Fig. 3.Need to prove, the diagram that provides in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and size drafting when implementing according to reality, kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also may be more complicated.

As shown in Figure 1, the invention provides a kind of BCH code EDC error detect correction method.Described BCH code EDC error detect correction method comprises step S1 and S2.

In step S1, calculate the syndrome to be compared of described BCH data group to be tested based on the check matrix that passes through the BCH data group to be tested of Bose-Chaudhuri-Hocquenghem Code.

Wherein, described check matrix is determined based on the generating mode of BCH data group to be tested.For BCH(m+k, k) sign indicating number, its generator matrix G=[I _mQ], check matrix H=[Q then ^TI _m], wherein, m is the figure place of data bit, k is the figure place of check digit, I _mUnit matrix for m * m.

For example, BCH data group to be tested adopts the generator matrix with BCH (16,8) sign indicating number to form, and for BCH (16,8) sign indicating number, because it is the shortening sign indicating number of BCH (17,9), the generator polynomial of BCH (17,9) is: g (D)=D ⁸+ D ⁷+ D ⁶+ D ⁴+ D ²+ D, then the generator matrix of BCH (17,9) is through being transformed to G '=[I _mQ] form:

$G^{\text{'}}=\left[\begin{array}{ccccccccccccccccc}1& 0& 0& 0& 0& 0& 0& 0& 0& 1& 1& 1& 0& 1& 0& 1& 1\\ 0& 1& 0& 0& 0& 0& 0& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0\\ 0& 0& 1& 0& 0& 0& 0& 0& 0& 0& 1& 0& 0& 1& 1& 1& 1\\ 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 1& 0& 0& 1& 1& 0& 0\\ 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 1& 0& 0& 1& 1& 0\\ 0& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 1& 0& 0& 1& 1\\ 0& 0& 0& 0& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0& 0& 1& 0\\ 0& 0& 0& 0& 0& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0& 0& 1\\ 0& 0& 0& 0& 0& 0& 0& 0& 1& 1& 1& 0& 1& 0& 1& 1& 1\end{array}\right]$

Save the generator matrix G that first row, first row just shorten to BCH (16,8) sign indicating number:

$G=\left[\begin{array}{cc}{I}_8& Q\end{array}\right]=\left[\begin{array}{cccccccccccccccc}1& 0& 0& 0& 0& 0& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0\\ 0& 1& 0& 0& 0& 0& 0& 0& 0& 1& 0& 0& 1& 1& 1& 1\\ 0& 0& 1& 0& 0& 0& 0& 0& 1& 1& 0& 0& 1& 1& 0& 0\\ 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 1& 0& 0& 1& 1& 0\\ 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 1& 0& 0& 1& 1\\ 0& 0& 0& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0& 0& 1& 0\\ 0& 0& 0& 0& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0& 0& 1\\ 0& 0& 0& 0& 0& 0& 0& 1& 1& 1& 0& 1& 0& 1& 1& 1\end{array}\right]$

If represent 8 bit data positions with a15-a8, a7-a0 represents 8 bit check positions, and is as follows from the generator matrix G formula of can encoding:

a7=a15+a13+a10+a8；

a6=a14+a13+a12+a10+a9+a8；

a5=a12+a11+a10+a9；

a4=a15+a11+a10+a9+a8；

a3=a15+a14+a13+a9；

a2=a15+a14+a13+a12+a8；

a1=a15+a14+a12+a11+a10+a8；

a0=a14+a11+a9+a8，

Wherein, above-mentioned various and follow-up various in "+" number all represent to be illustrated XOR at this; Can get the check matrix H of BCH (16,8) sign indicating number from above-mentioned generator matrix G:

$H=\left[\begin{array}{cc}{Q}^T& I_8\end{array}\right]=\left[\begin{array}{cccccccccccccccc}1& 0& 1& 0& 0& 1& 0& 1& 1& 0& 0& 0& 0& 0& 0& 0\\ 0& 1& 1& 1& 0& 1& 1& 1& 0& 1& 0& 0& 0& 0& 0& 0\\ 0& 0& 1& 1& 1& 1& 0& 0& 0& 1& 0& 0& 0& 0& 0& 0\\ 1& 0& 0& 0& 1& 1& 1& 1& 0& 0& 0& 1& 0& 0& 0& 0\\ 1& 1& 1& 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 0& 0& 0\\ 1& 1& 1& 1& 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 0& 0\\ 1& 1& 0& 1& 1& 1& 0& 1& 0& 0& 0& 0& 0& 0& 1& 0\\ 0& 1& 0& 0& 1& 0& 1& 1& 0& 0& 0& 0& 0& 0& 0& 1\end{array}\right]$

If represent 8 bit correction with S1-S8, based on above-mentioned check matrix H, can calculate the syndrome to be compared of BCH (16,8) sign indicating number according to following formula:

S1=a7+a15+a13+a10+a8；

S2=a6+a14+a13+a12+a10+a9+a8；

S3=a5+a12+a11+a10+a9；

S4=a4+a15+a11+a10+a9+a8；

S5=a3+a15+a14+a13+a9；

S6=a2+a15+a14+a13+a12+a8；

S7=a1+a15+a14+a12+a11+a10+a8；

S8=a0+a14+a11+a9+a8。

In step S2, if described syndrome to be compared is not 0, then described syndrome to be compared and a plurality of standard correction are compared, and proofread and correct corresponding data in the described BCH data group to be tested based on the minimum and specified wrong figure place of the number of data bits different with described syndrome to be compared also minimum standard correction.

Preferably, described syndrome S to be compared and 0 can be compared, if the result is 0, then export not error message of data; Otherwise, with described syndrome S to be compared respectively with the sub-S of standard correction _Ref1, S _Ref2... S _RefnThe variant data bits that compares acquisition is: k1, k2 ... .kn, wherein, k2 minimum, and the sub-S of the corresponding standard correction of k2 _Ref2, S _RefiIn, the sub-S of standard correction _Ref2The figure place of specified error bit is 1, the sub-S of standard correction _RefiThe figure place of specified error bit is 3, because the sub-S of standard correction _Ref2The figure place of specified error bit is less than the sub-S of standard correction _RefiThe figure place of specified error bit is then based on the sub-S of standard correction _Ref2Specified errors present is proofreaied and correct the corresponding data in the described BCH data group to be tested.

Preferably, if described syndrome to be compared is not 0, then each standard correction can be carried out ascending sort according to the figure place of specified error bit separately, subsequently described syndrome to be compared is compared with each standard correction in regular turn, in case have and identical standard correction of described syndrome to be compared, then based on proofreading and correct corresponding data in the described BCH data group to be tested with identical standard correction of described syndrome to be compared; Otherwise in case 1 bit data position standard correction different with described syndrome to be compared arranged, then based on described syndrome to be compared only different standard correction in 1 bit data position proofread and correct corresponding data in the described BCH data group to be tested; Otherwise in case 2 bit data positions standard correction different with described syndrome to be compared arranged, then based on described syndrome to be compared only different standard correction in 2 bit data positions proofread and correct corresponding data in the described BCH data group to be tested; Otherwise ..., until in case t bit data position standard correction different with described syndrome to be compared arranged, then based on described syndrome to be compared only different standard correction in t bit data position proofread and correct corresponding data in the described BCH data group to be tested; Wherein, t is the predetermined integers more than or equal to 1, and t can wait to preestablish based on circuit or shared area or the power consumption of chip that coding figure place, error correction are adopted, and preferably, t is less than or equal to BCH(m+k, k) the maximum error code figure place of energy error correction.

Wherein, standard correction is to adopt misdata group when makeing mistakes based on data bit and/or check digit according to formula S=B ' H ^TCalculate institute in advance and obtain, wherein, B ' is data bit and/or the check digit misdata group when makeing mistakes.

For example, for BCH (16,8), if when data bit and check digit have 0-2 error code position, based on standard correction that aforesaid check matrix obtains, listed as following table one:

Table one:

S1	S2	S3	S4	S5	S6	S7	S8	Error bit a
									0	0	0	0	0	0	0	0	Error-free
1	0	0	1	1	1	1	0	15
									0	1	0	0	1	1	1	1	14
1	1	0	0	1	1	0	0	13
									0	1	1	0	0	1	1	0	12
0	0	1	1	0	0	1	1	11
									1	1	1	1	0	0	1	0	10
0	1	1	1	1	0	0	1	9
									1	1	0	1	0	1	1	1	8
1	1	0	1	0	0	0	1	15,14
									0	1	0	1	0	0	1	0	15,13
1	1	1	1	1	0	0	0	15,12
									1	0	1	0	1	1	0	1	15,11
0	1	1	0	1	1	0	0	15,10
									1	1	1	0	0	1	1	1	15,9
0	1	0	0	1	0	0	1	15,8
									1	0	0	0	0	0	1	1	14,13
0	0	1	0	1	0	0	1	14,12
									0	1	1	1	1	1	0	0	14,11
1	0	1	1	1	1	0	1	14,10
									0	0	1	1	0	1	1	0	14,9
1	0	0	1	1	0	0	0	14,8
									1	0	1	0	1	0	1	0	13,12
1	1	1	1	1	1	1	1	13,11
									0	0	1	1	1	1	1	0	13,10
1	0	1	1	0	1	0	1	13,9
									0	0	0	1	1	0	1	1	13,8
0	1	0	1	0	1	0	1	12,11
									1	0	0	1	0	1	0	0	12,10
0	0	0	1	1	1	1	1	12,9
									1	0	1	1	0	0	0	1	12,8
1	1	0	0	0	0	0	1	11,10
									0	1	0	0	1	0	1	0	11,9
1	1	1	0	0	1	0	0	11,8

1	0	0	0	1	0	1	1	10,9
									0	0	1	0	0	1	0	1	10,8
1	0	1	0	1	1	1	0	9,8

Wherein, only listed the situation that data bit is made mistakes in the table one, comprise 2 bit data positions and the 1 bit data position situation of makeing mistakes only, because only check digit has 1 or 2 to make mistakes, do not relate to data bit, thus do not need to correct yet, therefore, preferably, being used for comparative standard syndrome can not comprise and only indicate standard correction that errors present is check digit.

Thus, if be used for comparative standard syndrome, do not comprise and to indicate the standard correction period of the day from 11 p.m. to 1 a.m that errors present is check digit, then if after syndrome to be compared and each standard correction compared, it is minimum and be not 0 the sub-S of standard correction to obtain the minimum and specified wrong figure place of the number of data bits different with described syndrome to be compared _Refj, then also need the sub-S of this standard correction _RefjThe figure place of the data bit different with described syndrome to be compared and the sub-S of this standard correction _RefjSpecified wrong figure place sum M1 is with comparing with value M2 of the data addition gained of described each data bit of syndrome to be compared, if M2 is greater than M1, then based on the sub-S of this standard correction _RefjProofread and correct the corresponding data in the described BCH data group to be tested, otherwise, if M2 is smaller or equal to M1, show then in the described BCH data group to be tested that only check digit is made mistakes, so can directly export described BCH data group to be tested.

As seen, for formula

If only utilize the mode of BCH (16,8) sign indicating number to correct 2 or 2 error codes that following data bit is made mistakes, check code then Planting combination wastes, if adopt BCH code EDC error detect correction method of the present invention, not only can correct

Kind of 2 and 2 error codes that following data bit is made mistakes can also correct that 3 bit data positions make mistakes

118 kinds of error codes in the situation of kind almost are the residue combinations that has utilized check code fully, and the decoding ability is further improved.

As shown in Figure 2, the invention provides a kind of BCH code EDC error detect correction circuit.This BCH code EDC error detect correction circuit 1 comprises at least: generative circuit 11, and error correction circuit 12.

Described generative circuit 11 is used for calculating based on the check matrix that passes through the BCH data group to be tested of Bose-Chaudhuri-Hocquenghem Code the syndrome to be compared of described BCH data group to be tested.

For example, by the check matrix of aforementioned BCH (16,8) as seen, described generative circuit 11 can adopt the syndrome S to be compared that calculates BCH data group to be tested such as logic gates such as XORs.

Described error correction circuit 12 is used for if described syndrome to be compared is not 0, then described syndrome to be compared and a plurality of standard correction are compared, and proofread and correct corresponding data in the described BCH data group to be tested based on the minimum and specified wrong figure place of the number of data bits different with described syndrome to be compared also minimum standard correction.

For example, error correction circuit 12 compares described syndrome S to be compared and 0, if the result is 0, then exports not error message of data; Otherwise, with described syndrome S to be compared respectively with the sub-S of standard correction _Ref1, S _Ref2... S _RefnThe variant data bits that compares acquisition is: k1, k2 ... .kn, wherein, k2 minimum, and the sub-S of the corresponding standard correction of k2 _Ref2With S _RefiIn, the sub-S of standard correction _Ref2The figure place of specified error bit is 1, the sub-S of standard correction _RefiThe figure place of specified error bit is 3, because the sub-S of standard correction _Ref2The figure place of specified error bit is less than the sub-S of standard correction _RefiThe figure place of specified error bit, then error correction circuit 12 is based on the sub-S of standard correction _Ref2Specified errors present is proofreaied and correct the corresponding data in the described BCH data group to be tested.

Again for example, error correction circuit 12 comprises sub-error correction unit.If described syndrome to be compared is not 0, then sub-error correction unit is carried out ascending sort with each standard correction according to the figure place of specified error bit separately, subsequently described syndrome to be compared is compared with each standard correction in regular turn, in case have and identical standard correction of described syndrome to be compared, then based on proofreading and correct corresponding data in the described BCH data group to be tested with identical standard correction of described syndrome to be compared; Otherwise in case 1 bit data position standard correction different with described syndrome to be compared arranged, then sub-error correction unit based on described syndrome to be compared only different standard correction in 1 bit data position proofread and correct corresponding data in the described BCH data group to be tested; Otherwise in case 2 bit data positions standard correction different with described syndrome to be compared arranged, then sub-error correction unit based on described syndrome to be compared only different standard correction in 2 bit data positions proofread and correct corresponding data in the described BCH data group to be tested; Otherwise ... until in case t bit data position standard correction different with described syndrome to be compared arranged, then sub-error correction unit based on described syndrome to be compared only different standard correction in t bit data position proofread and correct corresponding data in the described BCH data group to be tested; Wherein, t is the predetermined integers more than or equal to 1, and t can wait to preestablish based on coding figure place, error correction circuit 12 shared area or power consumptions, and preferably, t is less than or equal to BCH(m+k, k) the maximum error code figure place of energy error correction.

In addition, when being used for comparative standard syndrome, do not comprise indicating the standard correction period of the day from 11 p.m. to 1 a.m that errors present is check digit that described error correction circuit also comprises: and the value comparing unit.

It is also minimum and be not 0 the sub-S of standard correction that described and value comparing unit are used for that syndrome to be compared and each standard correction are compared the minimum and specified wrong figure place of the acquisition number of data bits different with described syndrome to be compared _RefjAfter, again with the sub-S of this standard correction _RefjThe figure place of the data bit different with described syndrome to be compared and the sub-S of this standard correction _RefjSpecified wrong figure place sum M1 is with comparing with value M2 of the data addition gained of described each data bit of syndrome to be compared, if M2 is greater than M1, then based on the sub-S of this standard correction _RefjProofread and correct the corresponding data in the described BCH data group to be tested, otherwise, if M2 is smaller or equal to M1, show then in the described BCH data group to be tested that only check digit is made mistakes, then directly export described BCH data group to be tested.

Preferably, described error correction circuit can adopt combinational logic circuit to realize.

As shown in Figure 3, the invention provides a kind of fault tolerant memory.Described fault tolerant memory 2 comprises at least: storage array 21, read-write control unit 22, coding unit 23, BCH code EDC error detect correction circuit 24 and interface unit 25.

Described storage array 21 is used for the storage data, and preferably, it is made of a plurality of phase-change memory cells.

Described read-write control unit 22 connects described storage array 21, is used for data are write described storage array 21, perhaps data is read by described storage array 21.

Described coding unit 23 is used for data to be stored are carried out sending into described read-write control unit 22 behind the Bose-Chaudhuri-Hocquenghem Code.

Particularly, described coding unit 23 adopts A=DG to come data D to be stored is encoded, and wherein, G is generator matrix, G=[I _mQ], I _mBe the unit matrix of m * m, Q is any matrix of m * k, and D is the matrix of 1 * m.

Preferably, described coding unit 23 can adopt such as logic gates such as XORs and realize.

Described BCH code EDC error detect correction circuit 24 is connected with described read-write control unit 22, be used for the data that described read-write control unit 22 is read are carried out exporting after the error correction, its structure is identical with aforementioned BCH code EDC error detect correction circuit 1 shown in Figure 2, and is contained in this by reference, is not described in detail in this.

Described interface unit 25 is connected with described coding unit 23 and BCH code EDC error detect correction circuit 24 respectively, and the data to be stored that are used for inserting are sent into described coding unit 23 and carried out Bose-Chaudhuri-Hocquenghem Code and the data after 24 error correction of described BCH code EDC error detect correction circuit are exported.

Preferably, described interface unit 25 is the SPI interface unit.

In sum, BCH code EDC error detect correction method of the present invention and circuit are compared with the former correction capability of BCH code by syndrome to be compared and standard correction being compared the errors present of specified data, can maximally utilise check digit, are satisfying formula

Prerequisite under, finish BCH code and entangle under the assurance of t dislocation, entangle the above mistake in a part of t position, further improved error correcting capability; Wherein, m is the figure place that needs data bit stored, and k is the figure place of check digit, maximum error code figure places that the t coding can be corrected; And BCH code EDC error detect correction circuit of the present invention can be made of pure logic gates, and only there is gate delay in clock when not required, is fit to be applied to SPI interface and so on has special requirement to sequential situation; In addition, reasons such as balance area or power consumption can reduce the decoding step, allow the errors present combination variety as far as possible close to 2 ^kSo the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.

Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any person skilled in the art scholar all can be under spirit of the present invention and category, and above-described embodiment is modified or changed.Therefore, have in the technical field under such as and know that usually the knowledgeable modifies or changes not breaking away from all equivalences of finishing under disclosed spirit and the technological thought, must be contained by claim of the present invention.

Claims (9)

1. a BCH code EDC error detect correction method is characterized in that, described BCH code EDC error detect correction method comprises at least:

1) based on the syndrome to be compared of calculating described BCH data group to be tested through the check matrix of the BCH data group to be tested of Bose-Chaudhuri-Hocquenghem Code;

2) if described syndrome to be compared is not 0, then described syndrome to be compared and a plurality of standard correction are compared, and proofread and correct corresponding data in the described BCH data group to be tested based on the minimum and specified wrong figure place of the number of data bits different with described syndrome to be compared also minimum standard correction.

2. BCH code EDC error detect correction method according to claim 1 is characterized in that described step 2) also comprise:

If described syndrome to be compared is not 0, then according to specified wrong figure place ascending order order, described syndrome to be compared is compared with each standard correction in regular turn, in case have and identical standard correction of described syndrome to be compared, then proofread and correct corresponding data in the described BCH data group to be tested based on standard correction therewith; Otherwise in case 1 bit data position standard correction different with described syndrome to be compared arranged, then based on described syndrome to be compared only different standard correction in 1 bit data position proofread and correct corresponding data in the described BCH data group to be tested; Otherwise in case 2 bit data positions standard correction different with described syndrome to be compared arranged, then based on described syndrome to be compared only different standard correction in 2 bit data positions proofread and correct corresponding data in the described BCH data group to be tested; Otherwise ..., until in case t bit data position standard correction different with described syndrome to be compared arranged, then based on described syndrome to be compared only different standard correction in t bit data position proofread and correct corresponding data in the described BCH data group to be tested; Wherein, t is the predetermined integers more than or equal to 1.

3. BCH code EDC error detect correction method according to claim 1 and 2, it is characterized in that, when being used for comparative standard syndrome, do not comprise and to indicate standard correction that errors present is check digit, and not with the identical standard correction period of the day from 11 p.m. to 1 a.m of syndrome to be compared, then if the data addition gained of described each data bit of relatively syndrome and value, minimum greater than the number of data bits different with described syndrome to be compared, and specified wrong figure place is the quantity of the data bit different with described syndrome to be compared of minimum standard correction and specified wrong figure place sum also, then minimum based on this number of data bits different with described syndrome to be compared, and specified wrong figure place also minimum standard correction is proofreaied and correct corresponding data in the described BCH data group to be tested, otherwise think that mistake does not appear in the data bit of described BCH data group to be tested, do not do to correct and handle.

4. BCH code EDC error detect correction circuit, it is characterized in that: described BCH code EDC error detect correction circuit comprises at least:

Generative circuit is for the syndrome to be compared of calculating described BCH data group to be tested based on the check matrix that passes through the BCH data group to be tested of Bose-Chaudhuri-Hocquenghem Code;

Error correction circuit, be used for if described syndrome to be compared is not 0, then described syndrome to be compared and a plurality of standard correction are compared, and proofread and correct corresponding data in the described BCH data group to be tested based on the minimum and specified wrong figure place of the number of data bits different with described syndrome to be compared also minimum standard correction.

5. BCH code EDC error detect correction circuit according to claim 4, it is characterized in that: described error correction circuit also comprises:

Sub-error correction unit, be used for if described syndrome to be compared is not 0, then according to specified wrong figure place ascending order order, described syndrome to be compared is compared with each standard correction in regular turn, in case have and identical standard correction of described syndrome to be compared, then proofread and correct corresponding data in the described BCH data group to be tested based on standard correction therewith; Otherwise in case 1 bit data position standard correction different with described syndrome to be compared arranged, then based on described syndrome to be compared only different standard correction in 1 bit data position proofread and correct corresponding data in the described BCH data group to be tested; Otherwise in case 2 bit data positions standard correction different with described syndrome to be compared arranged, then based on described syndrome to be compared only different standard correction in 2 bit data positions proofread and correct corresponding data in the described BCH data group to be tested; Otherwise ..., until in case t bit data position standard correction different with described syndrome to be compared arranged, then based on described syndrome to be compared only different standard correction in t bit data position proofread and correct corresponding data in the described BCH data group to be tested; Wherein, t is the predetermined integers more than or equal to 1.

6. according to claim 4 or 5 described BCH code EDC error detect correction circuit, it is characterized in that, when being used for comparative standard syndrome, do not comprise indicating the standard correction period of the day from 11 p.m. to 1 a.m that errors present is check digit that described error correction circuit also comprises:

With the value comparing unit, be used for not exist and the identical standard correction period of the day from 11 p.m. to 1 a.m of syndrome to be compared, if the data addition gained of described each data bit of relatively syndrome and value, minimum greater than the number of data bits different with described syndrome to be compared, and specified wrong figure place is the quantity of the data bit different with described syndrome to be compared of minimum standard correction and specified wrong figure place sum also, then minimum based on this number of data bits different with described syndrome to be compared, and specified wrong figure place also minimum standard correction is proofreaied and correct corresponding data in the described BCH data group to be tested, otherwise think that mistake does not appear in the data bit of described BCH data group to be tested, do not do to correct and handle.

7. a fault tolerant memory is characterized in that, described fault tolerant memory comprises at least:

Storage array;

The read-write control unit that is connected with described storage array;

Based on the coding unit of Bose-Chaudhuri-Hocquenghem Code, be used for data to be stored are carried out sending into described read-write control unit behind the Bose-Chaudhuri-Hocquenghem Code;

Each described BCH code EDC error detect correction circuit of claim 4 to 6 is connected with described read-write control unit, is used for the data that described read-write control unit is read are carried out exporting after the error correction;

Interface unit is connected with described coding unit and BCH code EDC error detect correction circuit respectively, and the data to be stored that are used for inserting are sent into described coding unit and carried out Bose-Chaudhuri-Hocquenghem Code and the data after the error correction of described BCH code EDC error detect correction circuit are exported.

8. fault tolerant memory according to claim 7 is characterized in that, described storage array is made of a plurality of phase-change memory cells.

9. fault tolerant memory according to claim 7 is characterized in that, described interface unit comprises the SPI interface unit.

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