CN103269126A

CN103269126A - Intelligent low-voltage molded case circuit breaker controller based on Ethernet communication

Info

Publication number: CN103269126A
Application number: CN2013101757921A
Authority: CN
Inventors: 周亚军; 徐平; 李晓军; 颜喜清; 陈文博
Original assignee: Hangzhou Dianzi University
Current assignee: Shanghai Molesitong Electrical Co ltd
Priority date: 2013-05-10
Filing date: 2013-05-10
Publication date: 2013-08-28
Anticipated expiration: 2033-05-10
Also published as: CN103269126B

Abstract

The invention discloses an intelligent low-voltage molded case circuit breaker controller based on the Ethernet communication. The intelligent low-voltage molded case circuit breaker controller based on the Ethernet communication comprises a power supply and trip circuit, a MCU circuit, a data acquisition circuit, a human-computer interface circuit, a communication module and a remote control module, wherein the power supply and trip circuit comprises a rectifying circuit, a self-generated power supply circuit, an external power supply interface and trip interface circuit and a system working power supply circuit; the data acquisition circuit comprises a current acquisition circuit and a voltage acquisition circuit; the human-computer interface circuit comprises a liquid crystal display circuit, an LED circuit, a keying circuit and a code switch circuit; the communication module comprises an Ethernet interface circuit and an RS485 interface circuit; the remote control circuit comprises an execution circuit, a state output circuit and a feedback circuit. The intelligent low-voltage molded case circuit breaker controller based on the Ethernet communication can dynamically monitor and display various electrical parameters, carry out real-time data interaction with a remote monitoring terminal through the Ethernet and achieve telemetering, remote control, remote communication and remote regulation on an on-site circuit breaker.

Description

Intelligent low-pressure breaker of plastic casing controller based on ethernet communication

Technical field

The present invention relates to a kind of controller, specifically be based on the intelligent low-pressure breaker of plastic casing controller of ethernet communication.

Background technology

Low-pressure plastic shell circuit breaker is widely used in the low-voltage distribution system, is the basis of distribution network.Detection and the defencive function of existing intelligent type low-voltage breaker of plastic casing are single, generally do not have liquid crystal and show that can not show electrical energy parameter in real time, intelligent degree is not high, does not possess Ethernet networking communication function, can't satisfy the application demand in the intelligent grid.Progressively expansion along with development and national economy and town and country power distribution network; no matter be that people are more and more higher in automation control, managerial skills and the intelligentized requirement of aspects such as monitoring, control, protection to electric power system aspect generating, transmission of electricity, distribution or electricity consumption.

Country supports energetically intelligent grid and invests in 12 planning, and the added value of intelligent type low-voltage electric equipment products also will be increased dramatically.The research of intelligent plastic housing circuit breaker, for improving grid automation level, improving China's low voltage electrical apparatus industry competitiveness has significance.

Summary of the invention

The present invention is the intelligent controller of communicating by letter that low-pressure plastic shell circuit breaker is used.Can realize the kinds of protect function, the protection parameter can arrange, and can record electric network fault, intelligent degree height; Have good man computer interface, can show real-time electric parameter; Have Ethernet and 485 two kinds of communication functions.

For realizing above-mentioned functions, the present invention adopts following technical scheme.

The present invention is made up of power supply and trip circuit, MCU circuit, data acquisition circuit, man-machine interface circuit, communication module and remote control module.Power supply and trip circuit comprise rectification circuit, authigenic power supply circuit, external power source interface and dropout interface circuit, system works power circuit.

In the described rectification circuit in the A commutating phase circuit inlet wire of the first rectifier bridge BG1 connect No. 1, No. 2 ports of the first connector J1, the outlet anode connects the LP1 network, negative terminal connects an end of the 3rd resistance R 3, the other end of the 3rd resistance R 3 connects an end of LA network and the 5th capacitor C 5, and the other end of the 5th capacitor C 5 connects GND; One end of the 8th resistance R 8 connects the outlet negative terminal of the first rectifier bridge BG1, and the other end of the 8th resistance R 8 connects GND; The circuit of structure has four as mentioned above, except A commutating phase circuit, also comprises B commutating phase circuit, C commutating phase circuit, N commutating phase circuit, and the end of going into of their rectifier bridge connects the first connector J1 or the second connector J2 respectively; The LA network is corresponding with connecting, corresponding LB network, LC network, the LN network of connecting respectively of its excess-three circuit.

The negative electrode of transient state killer tube D13 connects the LP1 network in the described authigenic power supply circuit, and the anode of transient state killer tube D13 connects GND; The grid of the first N-channel MOS pipe Q1 connects an end of the 12 diode D12 negative electrode and the 19 resistance R 19, and the other end of the 19 resistance R 19 connects GND; The source electrode of the first N-channel MOS pipe Q1 connects the LP1 network, and the drain electrode of the first N-channel MOS pipe Q1 connects GND; The anode of the 12 diode D12 connects No. 69 control output pins of MCU chip U9 in the MCU circuit; The anode of the 3rd diode D3 connects the LP1 network, and the negative electrode of the 3rd diode D3 connects the Vzs network; One end of the 17 capacitor C 17 connects the Vzs network, and the other end connects GND; The positive pole of the 15 capacitor C 15 connects the Vzs network, and negative pole connects GND; The positive pole of the 16 capacitor C 16 connects the Vzs network, and negative pole connects GND; One end of the 14 resistance R 14 connects the Vzs network, and the other end connects the PAD network; One end of the 20 resistance R 20 connects the PAD network, and the other end connects GND; One end of the 19 capacitor C 19 connects the PAD network, and the other end connects GND; The PAD network is linked No. 15 input pins of MCU chip U9 in the MCU circuit.

The 7th diode D7 negative electrode connects the Vzs network in described external power source and the dropout interface circuit, and anode connects the OUTPOWER network; GND connects the OUTGND network; OUTPWR network and OUTGND network are connected to the 3rd connector J3 respectively; The 8th diode D8 anode connects the Vzs network, and negative electrode connects the tenth diode D10 negative electrode; The anode of the tenth diode D10 connects the source electrode of the second N-channel MOS pipe Q2; The two ends of the 4th connector J4 connect the two poles of the earth of the tenth diode D10 respectively; The drain electrode of the second N-channel MOS pipe Q2 connects GND, and grid connects the negative electrode of the 14 diode D14, and the anode of the 14 diode D14 connects No. 68 pins of MCU chip U9 in the MCU circuit; The 21 capacitor C 21 is in parallel with the 24 resistance R 24, and the two ends after the parallel connection connect grid and the GND of the second N-channel MOS pipe Q2 respectively; The 4th diode D4 anode connects the Vzs network, and negative electrode connects the LP2 network; The 14 capacitor C 14 1 ends connect the LP2 network, and the other end connects GND.

Described system works power circuit comprises+the 3.3V power circuit ,+5V power circuit, analog circuit power supply, treatment circuit; + 3.3V power circuit connects LP2 network and+3.3V network; + 5V power circuit connects LP2 network and+5V network; Analog circuit power supply connection+5V network and VDDA; The ground treatment circuit connects AGND, GND and DGND.

No. 1 pin, No. 2 pins, No. 3 pins, No. 4 pins of EEPROM device U8 all were connected to DGND during described MCU circuit comprised, No. 8 pin connection+3.3V networks, No. 6 pins are connected to No. 92 pins of MCU chip U9, and No. 5 pins of EEPROM device U8 are connected to No. 93 pins of MCU chip U9; One end connection+3.3V network of the 72 resistance R 72, the other end connects No. 6 pins of EEPROM device U8; One end connection+3.3V network of the 73 resistance R 73, the other end connects No. 5 pins of EEPROM device U8; One end connection+3.3V network of the 55 capacitor C 55, the other end connects DGND; The end of the first crystal oscillator Y1 connects an end of the 56 capacitor C 56, and the other end of the first crystal oscillator Y1 connects an end of the 57 capacitor C 57; An end that does not link to each other with the first crystal oscillator Y1 of the 56 capacitor C 56 and the 57 capacitor C 57 all is connected DGND; One end of the 78 resistance R 78 connects No. 8 pins of MCU chip U9, one end of the 79 resistance R 79 connects No. 9 pins of MCU chip U9, and the 78 resistance R 78 and that end that does not link to each other with MCU chip U9 of the 79 resistance R 79 are connected the two ends of the first crystal oscillator Y1 respectively; The end of the second crystal oscillator Y2 connects an end of the 58 capacitor C 58, and the other end connects an end of the 60 capacitor C 60; An end that does not link to each other with the second crystal oscillator Y2 of the 58 capacitor C 58 and the 60 capacitor C 60 all is connected DGND; The second crystal oscillator Y2 is connected No. 12 pins of MCU chip U9 with the 58 capacitor C 58 continuous those ends, the other end connects an end of the 82 resistance R 82; The other end of the 82 resistance R 82 connects No. 13 pins of MCU chip U9; The two ends of the 81 resistance R 81 connect the two ends of the second crystal oscillator Y2 respectively; One end connection+5V network of the 61 capacitor C 61, the other end connects AGND; No. 1 pin connection+5V network of reference voltage chip U10, No. 3 pin connects AGND, and No. 2 pin connects the VREF+ network; The positive pole of the 62 capacitor C 62 connects the VREF+ network, and negative pole connects AGND; The two ends of the 63 capacitor C 63 connect the two ends of the 62 capacitor C 62 respectively; The reset No. 3 pin connection+3.3V networks of chip U12, No. 1 pin connects DGND, and No. 2 pins connect No. 14 pins of MCU chip U9 and an end of the 59 capacitor C 59; The other end of the 59 capacitor C 59 connects DGND; One end of the 74 resistance R 74 connects No. 94 pins of MCU chip U9, and the other end connects DGND; One end of the 86 resistance R 86 connects No. 37 pins of MCU chip U9, and the other end connects DGND; The 64 capacitor C 64, the 65 capacitor C 65, the 66 capacitor C 66, the 67 capacitor C 67, the 68 capacitor C 68, the 69 capacitor C 69, the 70 capacitor C 70,71 parallel connections of the 71 capacitor C, end connection+3.3V network after the parallel connection, the other end connects DGND; No. 6 pins of MCU chip U9, No. 11 pins, No. 28 pins, No. 50 pins, No. 75 pins, No. 100 pins all connect+the 3.3V network, No. 21 pin connects the VREF+ network, No. 22 pin connects the VDDA pin, No. 19 pin connects AGND, and No. 10 pins, No. 20 pins, No. 27 pins, No. 49 pins, No. 74 pins, No. 99 pins connect DGND.

Described data acquisition circuit comprises current acquisition circuit and voltage collection circuit; The current acquisition circuit has four, and it goes into LA network, LB network, LC network, LN network that end connects rectification circuit respectively, and output connects the respective pins of MCU chip U9 in the MCU circuit respectively; The input of voltage collection circuit connects corresponding connectors respectively, and output then connects the respective pins of MCU chip U9 in the MCU circuit.

The man-machine interface circuit comprises liquid crystal display circuit, led circuit, key circuit, coding switch circuit; They link to each other with the MCU circuit respectively.

LCD U14 No. 1 pin in the described liquid crystal display circuit, No. 2 pins, No. 3 pins, No. 4 pins, No. 5 pins connect No. 64 pins of MCU chip U9 in the MCU circuit respectively, No. 63 pins, No. 62 pins, No. 61 pins, No. 60 pins, No. 7 pins of LCD U14 connect DGND, No. 8 pins of LCD U14, No. 14 pins, No. 15 pins, No. 16 pins, No. 17 pins, No. 18 pin connects the 82 capacitor C 82 respectively, the 77 capacitor C 77, the 78 capacitor C 78, the 79 capacitor C 79, the 80 capacitor C 80, the 81 capacitor C 81 end separately, these electric capacity other end separately all connects DGND; No. 9 pins of LCD U14 link to each other with No. 8 pins; The two ends of the 76 capacitor C 76 connect No. 10 pins and No. 11 pins of LCD U14 respectively; The two ends of the 72 capacitor C 72 connect No. 12 pins and No. 13 pins of LCD U14 respectively.

Described key circuit has 5, and an end connection+3.3V network of the 92 resistance R 92 in each key circuit, the other end connect No. 71 pins of MCU chip U9 in the MCU circuit and the end of the first button S1; The other end of the first button S1 connects DGND; One end connection+3.3V network of the 93 resistance R 93, the other end connect No. 70 pins of MCU chip U9 in the MCU circuit and the end of button S2; The other end of the second button S2 connects DGND; One end connection+3.3V network of the 94 resistance R 94, the other end connect No. 66 pins of MCU chip U9 in the MCU circuit and the end of the 3rd button S3; The other end of the 3rd button S3 connects DGND; One end connection+3.3V network of the 95 resistance R 95, the other end connect No. 65 pins of MCU chip U9 in the MCU circuit and the end of the 4th button S4; The other end of the 4th button S4 connects DGND; The 96 resistance R 96 1 end connection+3.3V networks, the other end connect No. 54 pins of MCU chip U9 in the MCU circuit and the end of the 5th button S5; The other end of the 5th button S5 connects DGND.

Described led circuit has 3, and an end of the 91 resistance R 91 connects No. 44 pins of MCU chip U9 in the MCU circuit in each led circuit, and the other end connects the anode of the 3rd light-emitting diode DS3; The negative electrode of the 3rd light-emitting diode DS3 connects DGND; One end of the 97 resistance R 97 connects No. 45 pins of MCU chip U9 in the MCU circuit, and the other end connects the anode of the 4th light-emitting diode DS4; The negative electrode of the 4th Light-Emitting Diode DS4 connects DGND; One end of the 102 resistance R 102 connects No. 46 pins of MCU chip U9 in the MCU circuit, and the other end connects the anode of the 5th Light-Emitting Diode DS5; The negative electrode of the 5th Light-Emitting Diode DS5 connects DGND.

Described coding switch circuit has 2, the 87 resistance R 87, the 88 resistance R 88, the 89 resistance R 89, the 90 resistance R 90 one termination+3.3V network separately in each coding switch circuit, the other end connect No. 2 pins of the first code switch U11, No. 3 pins, No. 4 pins, No. 5 pins respectively; No. 1 pin of the first code switch U11, No. 6 pins connect DGND, and No. 2 pins of the first code switch U11, No. 3 pins, No. 4 pins, No. 5 pins connect No. 88 pins of MCU chip U9 in the MCU circuit, No. 86 pins, No. 85 pins, No. 84 pins respectively; The 98 resistance R 98, the 99 resistance R 99, the 100 resistance R 100, the 101 resistance R 101 one termination+3.3V network separately, the other end connect No. 2 pins of the second code switch U13, No. 3 pins, No. 4 pins, No. 5 pins respectively; No. 1 pin of the second code switch U13, No. 6 pins connect DGND, and No. 2 pins of the second code switch U13, No. 3 pins, No. 4 pins, No. 5 pins connect No. 83 pins of MCU chip U9 in the MCU circuit, No. 82 pins, No. 81 pins, No. 80 pins respectively.

Communication module comprises ethernet interface circuit and RS485 interface circuit; Ethernet interface circuit links to each other with the MCU circuit by the MII interface; The RS485 interface circuit connects the MCU circuit.

The 73 capacitor C 73, the 74

capacitor C

74,75 parallel connections of the 75 capacitor C in the described ethernet interface circuit, the end connection+3.3V network after the parallel connection, the other end connects DGND; One end of the 111 resistance R 111 connects No. 7 pins of Ethernet PHY controller U15, and the other end connects an end of the 84 resistance R 84; The other end of the 84 resistance R 84 connects No. 53 pins of MCU chip U9 in the MCU circuit; The 112 resistance R 112 1 end connection+3.3V networks, the other end connect No. 7 pins of Ethernet PHY controller U15; No. 1 pin of the 6th exclusion RN6, No. 2 pins, No. 3 pins, No. 4 pins connect No. 13 pins of Ethernet PHY controller U15, No. 14 pins, No. 16 pins, No. 17 pins respectively, No. 5 pins of the 6th exclusion RN6, No. 6 pins, No. 7 pins, No. 8 pin connection+3.3V networks; The 116 resistance R 116 and the 117 resistance R 117 1 end connection+3.3V networks, the other end connects No. 20 pins of Ethernet PHY controller U15, No. 21 pins respectively; The 85 capacitor C 85, the 86 capacitor C 86, the 87 capacitor C 87,88 parallel connections of the 88 capacitor C, end after the parallel connection connects DGND, the other end connects RFB network, No. 18 pins, No. 23 pins, No. 37 pins of RFB network connection Ethernet PHY controller U15; One end of the 113 resistance R 113 connects DGND, and the other end connects No. 24 pins of Ethernet PHY controller U15; No. 5 pins of the 5th exclusion RN5, No. 6 pins, No. 7 pins, No. 8 pins and+3.3V network connection, No. 1 pin of the 5th exclusion RN5, No. 2 pins, No. 3 pins connect No. 28 pins of Ethernet PHY controller U15, No. 27 pins, No. 26 pins respectively; One end connection+3.3V network of the 109 resistance R 109, the other end connect No. 30 pins of Ethernet PHY controller U15; The 110 resistance R 110 1 ends connect No. 25 pins of MCU circuit MCU chip U9, and the other end connects No. 30 pins of Ethernet PHY controller U15; The 83 capacitor C 83 is connected DGND respectively with an end of the 84 capacitor C 84, and the other end connects the two ends of the 3rd crystal oscillator Y3 respectively; The end of the 3rd crystal oscillator Y3 connects No. 34 pins of Ethernet PHY controller U15, and the other end connects an end of the 108 resistance R 108; The other end of the 108 resistance R 108 connects No. 33 pins of Ethernet PHY controller U15; No. 22 pins of Ethernet PHY controller U15, No. 32 pins, No. 48 pin connection+3.3V networks; No. 15 pins of Ethernet PHY controller U15, No. 19 pins, No. 35 pins, No. 36 pins, No. 47 pins connect DGND; No. 29 pins of Ethernet PHY controller U15 are connected to No. 14 pins of MCU circuit MCU chip U9; No. 1 pin of Ethernet PHY controller, No. 5 pins, No. 6 pins, No. 45 pins connect the end of the 3rd exclusion RN3 respectively, and the other end of the 3rd exclusion RN3 connects No. 18 pins of MCU circuit MCU chip U9, No. 17 pins, No. 95 pins, No. 58 pins successively respectively; No. 2 pins of Ethernet PHY controller, No. 3 pins, No. 4 pins connect the end of the 4th exclusion RN4 respectively, and the other end of the 4th exclusion RN4 connects No. 48 pins of MCU circuit MCU chip U9, No. 51 pins, No. 52 pins successively respectively; No. 40 pins of Ethernet PHY controller, No. 41 pins, No. 42 pins, No. 46 pins connect the end of the first exclusion RN1 respectively, and the other end of the first exclusion RN1 connects No. 23 pins of MCU chip U9 in the MCU circuit, No. 47 pins, No. 26 pins, No. 59 pins successively respectively; No. 38 pins of Ethernet PHY controller U15, No. 39 pins, No. 43 pins, No. 44 pins connect the end of the second exclusion RN2 respectively, and the other end of the second exclusion RN2 is connected to No. 24 pins of MCU chip U9 in the controller circuitry, No. 55 pins, No. 56 pins, No. 57 pins successively respectively; No. 1 pin of RJ45 interface CN3, No. 2 pins, No. 3 pins, No. 6 pins, No. 10 pins, No. 11 pins connect No. 17 pins of Ethernet PHY controller U15, No. 16 pins, No. 14 pins, No. 13 pins, No. 28 pins, No. 26 pins respectively; No. 9 pins of RJ45 interface CN3, No. 12 pins connect the 121 resistance R 121, the 119 resistance R 119 end separately respectively, and an other end of these two resistance all connects+the 3.3V network; No. 8 pins of RJ45 interface CN3 connect AGND; No. 4 pins of RJ45 interface CN3, No. 5 pin connection+3.3V networks.

An end connection+3.3V network of the 114 resistance R 114 in the described RS485 interface circuit, the other end connects No. 6 pins of transceiver U16; The two ends of the 118 resistance R 118 connect No. 6 pins of transceiver U16, No. 7 pins respectively; One end of the 122 resistance R 122 connects DGND, and the other end connects No. 7 pins of transceiver U16; The two ends of the 91 capacitor C 91 connect DGND and+3.3V network respectively; No. 1 pin of transceiver U16, No. 2 pins, No. 3 pins, No. 4 pins connect No. 79 pins of MCU chip U9 in the MCU circuit, No. 43 pins, No. 43 pins, No. 78 pins respectively; No. 8 pins of transceiver U16, No. 5 pins connect respectively+3.3V network and DGND; No. 6 pins of transceiver U16 connect an end of resistance R 115, and the other end of the 115 resistance R 115 connects No. 3 pins of common mode inhibition device T1; No. 7 pins of transceiver U16 connect an end of the 120 resistance R 120, the other end of the 120 resistance R 120 connects No. 1 pin of common mode inhibition device T1; No. 2 pins of common mode inhibition device T1, No. 4 pins link to each other with the 5th connector J5 respectively.

Remote control module comprises executive circuit, state output circuit and feedback circuit; Executive circuit, state output circuit, feedback circuit are connected to the MCU circuit respectively.

Described executive circuit has 2, and the 4th optocoupler isolator U20 No. 1 pin connects an end of the 126 resistance R 126, the other end connection+3.3V network of the 126 resistance R 126 in each executive circuit; No. 3 pins of the 4th optocoupler isolator U20 are connected to No. 39 pins that connect MCU chip U9 in the MCU circuit, No. 4 pin connection-24V networks of the 4th optocoupler isolator U20; No. 6 pins of the 4th optocoupler isolator U20 connect an end of the 77 resistance R 77, and the other end of the 77 resistance R 77 connects the base stage of the first triode Q4; One end connection+24V network of the 76 resistance R 76, the other end connects the base stage of the first triode Q4; The emitter of the first triode Q4 connects the negative electrode of the first light-emitting diode DS1, the collector electrode connection-24V network of the first triode Q4; The anode of the first light-emitting diode DS1 connects an end of the 75 resistance R 75; Other end connection+24V the network of the 75 resistance R 75; The 15 diode D15 is in parallel with the input of first relay K 1, and the negative electrode connection+24V network of the 15 diode D15, the anode of the 15 diode D15 connect the first triode Q4 emitter; The output of first relay K 1 links to each other with the tenth connector CN1; Another one in the executive circuit is identical with foregoing circuit; The 4th optocoupler isolator U20 No. 3 pins are connected to No. 39 pins that connect MCU chip U9 in the MCU circuit in the foregoing circuit, and corresponding with it, the respective pins of another one executive circuit is connected to No. 38 pins of MCU chip U9 in the MCU circuit.

Described state output circuit and state-feedback circuit comprise 3 state output circuits; Wherein in the state output circuit, one end connection+3.3V network of the 13 resistance R 13, the other end connects No. 1 pin of the first optocoupler isolator U17, No. 3 pins of the first optocoupler isolator U17 connect No. 40 pins of MCU chip U9 in the MCU circuit, No. 4 pin connection-24V networks of the first optocoupler isolator U17, No. 6 pins of the first optocoupler isolator U17 link to each other with connector J9; The circuit of above-mentioned annexation has 3; The first optocoupler isolator U17 No. 3 pins are connected to No. 40 pins of MCU chip U9 in the MCU circuit in the foregoing circuit, corresponding with it, the respective pins of two other state output circuit is connected to No. 41 pins of MCU chip U9 in the MCU circuit, No. 42 pins respectively; In four pins of the 9th connector J9, wherein three link to each other another one connection-24V network respectively with three state output circuits; State-feedback circuit: No. 1 pin of the 5th optocoupler isolator U21 connects an end of the 140 resistance R 140, the other end of the 140 resistance R 140 links to each other with the pin of the 7th connector J7, another pin of the 7th connector J7 connects No. 3 pins of the 5th optocoupler isolator U21, No. 6 pins of the 5th optocoupler isolator U21 are connected to an end of the 142 resistance R 142, other end connection+3.3V the network of the 142 resistance R 142, No. 6 pins of the 5th photoelectrical coupler U21 connect No. 87 pins of MCU chip U9 in the MCU circuit, and No. 4 pins of the 5th photoelectrical coupler U21 photoelectrical coupler connect DGND.

In the above-mentioned circuit for remotely controlling ,-24V network ,+the 24V network connects No. 1 pin and No. 2 pins of connector J8 respectively.

An end connection+3.3V networking of the 103 resistance R 103 in the described emulation interface circuit, the other end links to each other with No. 1 pin of the 12 connector JP1, one end connection+3.3V networking of the 104 resistance R 104, the other end links to each other with No. 3 pins of the 12 connector JP1, one end connection+3.3V networking of the 105 resistance R 105, the other end links to each other with No. 4 pins of the 12 connector JP1, one end connection+3.3V networking of the 106 resistance R 106, the other end links to each other with No. 5 pins of the 12 connector JP1, one end of the 107 resistance R 107 connects DGND, and the other end links to each other with No. 2 pins of the 12 connector JP1; No. 1 pin of the 12 connector JP1, No. 2 pins, No. 3 pins, No. 4 pins, No. 5 pins, No. 6 pins connect No. 89 pins of MCU chip U9 in the MCU circuit, No. 76 pins, No. 72 pins, No. 77 pins, No. 90 pins, No. 14 pins respectively; No. 7 pin connection+3.3V networks of the 12 connector JP1, No. 8 pins of the 12 connector JP1 connect DGND.

The present invention has following beneficial effect with respect to prior art: the low-pressure plastic shell circuit breaker of using this intelligent controller, outside possessing the basic defencive function such as overload long delay, short circuit short time delay and short circuit instantaneous protection that conventional circuit breaker has, also have overvoltage, under-voltage protection, fault pre-alarming, self-diagnostic function; And can record electric network fault information, can carry out dynamic monitoring and demonstration to every electric parameter (as: electric current, voltage, active power, reactive power, apparent power, power factor), it is mutual to carry out real time data by Ethernet and remote monitoring end, thereby realizes on-the-spot circuit breaker is implemented remote measurement, remote control, distant news, remote regulating.Low-pressure plastic shell circuit breaker intelligent controller of the present invention can adapt to the automation requirement that intelligent power distribution net system improves constantly, and makes the scheduling of low-voltage distribution system, operation and maintenance realize networking, improves the level of informatization and the reliability of whole system.Can also select sex-linked demand by adaptation zone in addition, thereby selective protection is rationally mated.

Description of drawings

Fig. 1 system hardware entire block diagram;

Fig. 2 controller main program flow chart;

Fig. 3 rectification circuit;

Fig. 4 authigenic power supply circuit;

Fig. 5 external power supply and dropout interface circuit;

Fig. 6 3.3V power circuit;

Fig. 7 5V power circuit;

Fig. 8 analog circuit power supply and ground treatment circuit;

Fig. 9 MCU circuit;

Figure 10 A phase current sampling circuit;

Figure 11 N phase current sampling circuit;

Figure 12 A phase voltage sample circuit;

Figure 13 man-machine interface circuit;

Figure 14 ethernet interface circuit;

Figure 15 RS485 interface circuit;

Figure 16 remote control module;

Figure 17 emulation interface circuit.

Embodiment

Below in conjunction with accompanying drawing the present invention is described further.

The present invention is made up of power supply and trip circuit, MCU circuit, data acquisition circuit, man-machine interface circuit, communication module, remote control module, and system forms as shown in Figure 1.The controller main program flow as shown in Figure 2.

Power supply and trip circuit comprise rectification circuit, authigenic power supply circuit, external power source interface and dropout interface circuit, system works power circuit.

Described rectification circuit comprises the first rectifier bridge BG1, the second rectifier bridge BG2, the 3rd rectifier bridge BG3, the 4th rectifier bridge BG4, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10, the 11 resistance R 11, the five capacitor C 5, the 6th capacitor C 6, the 8th capacitor C 8, the 9th capacitor C 9, the first connector J1, the second connector J2.Wherein A commutating phase circuit as shown in Figure 3.The inlet wire of the first rectifier bridge BG1 connects No. 1, No. 2 ports of the first connector J1, the outlet anode connects the LP1 network, negative terminal connects an end of the 3rd resistance R 3, and the other end of the 3rd resistance R 3 connects an end of LA network and the 5th capacitor C 5, and the other end of the 5th capacitor C 5 connects GND.One end of the 8th resistance R 8 connects the outlet negative terminal of the first rectifier bridge BG1, and the other end of the 8th resistance R 8 connects GND.The circuit of structure has 4 as mentioned above, except A commutating phase circuit, also comprises B commutating phase circuit, C commutating phase circuit, N commutating phase circuit, and the end of going into of their rectifier bridge connects the first connector J1 or the second connector J2 respectively; The LA network is corresponding with connecting, corresponding LB network, LC network, the LN network of connecting respectively of its excess-three circuit.

Described authigenic power supply circuit as shown in Figure 4.Circuit comprises the 14 resistance R 14, the 19 resistance R 19, the 20 resistance R 20, the 15 capacitor C 15, the 16 capacitor C 16, the 17 capacitor C 17, the 19 capacitor C 19, Transient Suppression Diode D13, the first N-channel MOS pipe Q1, the 3rd diode D3, the 12 diode D12.The negative electrode of transient state killer tube D13 connects the LP1 network, and the anode of transient state killer tube D13 connects GND.The grid of the first N-channel MOS pipe Q1 connects an end of the 12 diode D12 negative electrode and the 19 resistance R 19, and the other end of the 19 resistance R 19 connects GND; The source electrode of the first N-channel MOS pipe Q1 connects the LP1 network, and the drain electrode of the first N-channel MOS pipe Q1 connects GND.The anode of the 12 diode D12 connects No. 69 control output pins of MCU chip U9 in the MCU circuit; The anode of the 3rd diode D3 connects the LP1 network, and the negative electrode of the 3rd diode D3 connects the Vzs network.One end of the 17 capacitor C 17 connects the Vzs network, and the other end connects GND; The positive pole of the 15 capacitor C 15 connects the Vzs network, and negative pole connects GND; The positive pole of the 16 capacitor C 16 connects the Vzs network, and negative pole connects GND; One end of the 14 resistance R 14 connects the Vzs network, and the other end connects the PAD network; One end of the 20 resistance R 20 connects the PAD network, and the other end connects GND; One end of the 19 capacitor C 19 connects the PAD network, and the other end connects GND; The PAD network is linked No. 15 input pins of MCU chip U9 in the MCU circuit.

Described external power source and dropout interface circuit are as shown in Figure 5.Circuit comprises: the 4th diode D4, the 7th diode D7, the 8th diode D8, the tenth diode D10, the 14 diode D14, the 14 capacitor C 14, the 21 capacitor C 21, the 24 resistance R 24, the second N-channel MOS pipe Q2, the 3rd connector J3, the 4th connector J4.The model of the 4th diode D4, the 7th diode D7, the 8th diode D8, the tenth diode D10, the 14 diode D14 can be selected MBR0540, and the model of the second N-channel MOS pipe Q2 can be selected STD35NF06L.The 7th diode D7 negative electrode connects the Vzs network, and anode connects the OUTPOWER network; GND connects the OUTGND network; OUTPWR network and OUTGND network are connected to the 3rd connector J3 respectively.The 8th diode D8 anode connects the Vzs network, and negative electrode connects the tenth diode D10 negative electrode; The anode of the tenth diode D10 connects the source electrode of the second N-channel MOS pipe Q2; The two ends of the 4th connector J4 connect the two poles of the earth of the tenth diode D10 respectively; The drain electrode of the second N-channel MOS pipe Q2 connects GND, and grid connects the negative electrode of the 14 diode D14, and the anode of the 14 diode D14 connects No. 68 pins of MCU chip U9 in the MCU circuit; The 21 capacitor C 21 is in parallel with the 24 resistance R 24, and the two ends after the parallel connection connect grid and the GND of the second N-channel MOS pipe Q2 respectively; The 4th diode D4 anode connects the Vzs network, and negative electrode connects the LP2 network; The 14 capacitor C 14 1 ends connect the LP2 network, and the other end connects GND.

Described system works power circuit comprises+the 3.3V power circuit ,+5V power circuit, analog circuit power supply, treatment circuit.+ 3.3V power circuit connects LP2 network and+3.3V network; + 5V power circuit connects LP2 network and+5V network; Analog circuit power supply connection+5V network and VDDA; The ground treatment circuit connects AGND, GND and DGND.

Described+the 3.3V power circuit is as shown in Figure 6.Circuit comprises second source converter U2, the 5th diode D5, the 6th diode D6, the 11 diode D11, the 12 resistance R 12, the 15 resistance R 15, the 16 resistance R 16, the 18 resistance R 18, the 21 resistance R 21, the 23 resistance R 23, the tenth capacitor C 10, the 11 capacitor C 11, the 12 capacitor C 12, the 13 capacitor C 13, the 18 capacitor C 18, the 20 capacitor C 20, the second inductance L 2.The model of second source converter U2 is LT1934, and the 5th diode D5 and the 11 diode D11 model can be selected MBR0540, and the 6th diode D6 model can be selected CMDSH-3.The 5th diode D5 anode connects the LP2 network, and negative electrode connects an end of the 12 resistance R 12, and the other end of the 12 resistance R 12 connects anodal and the 16 resistance R 16 1 ends of the 11 capacitor C 11; The other end of the 16 resistance R 16 connects the negative pole of the 11 capacitor C 11 and the positive pole of the 18 capacitor C 18, and the negative pole of the 18 capacitor C 18 connects DGND; The two ends of the 21 resistance R 21 connect the two ends of the 18 capacitor C 18 respectively; One end of the 18 resistance R 18 connects No. 5 pins of second source converter U2, and the other end connects No. 4 pins of second source converter U2; No. 5 pins of second source converter U2 connect the positive pole of the 11 capacitor C 11, No. 4 pins connect an end of the 20 capacitor C 20, the other end of the 20 capacitor C 20 connects DGND, No. 2 pins of second source converter U2 connect DGND, No. 3 pins connect an end of the 23 resistance R 23, and the other end of the 23 resistance R 23 connects DGND; No. 6 pins of second source converter U2 and No. 1 pin are connected the two ends of the tenth capacitor C 10 respectively; The negative electrode of the 11 diode D11 connects No. 6 pins of second source converter U2, and anode connects DGND; One end of the 13 capacitor C 13 connects No. 3 pins of second source converter U2, other end connection+3.3V network; One end of second inductance L 2 connects No. 6 pins of second source converter U2, other end connection+3.3V network; The 6th diode D6 negative electrode connects No. 1 pin of second source converter U2, anode connection+3.3V network; One end connection+3.3V network of the 15 resistance R 15, the other end connects No. 3 pins of second source converter U2; Positive pole connection+3.3V the network of the 12 capacitor C 12, negative pole connects DGND.

Described+5V power circuit network is as shown in Figure 7.Circuit comprises the first supply convertor U1, the first diode D1, the second diode D2, first resistance R 1, second resistance R 2, the 7th resistance R 7, first capacitor C 1, second capacitor C 2, the 3rd capacitor C 3, the 4th capacitor C 4, the 7th capacitor C 7, the 22 capacitor C 22, the 23 capacitor C 23, the 24 capacitor C 24, the 25 capacitor C 25, the 26 capacitor C 26, the 27 capacitor C 27, the 28 capacitor C 28, the 29 capacitor C 29, the 30 capacitor C 30, the 31 capacitor C 31, the 32 capacitor C 32, the 33 capacitor C 33, the 34 capacitor C 34, first inductance L, 1, the first magnetic bead FB1, the second magnetic bead FB2.The model of the first voltage changer U1 is LT1934, and the first diode D1 model can be selected CMPD914.The 22 capacitor C 22, the 23 capacitor C 23, the 24 capacitor C 24, the 27 capacitor C 27, the 28

capacitor C

28,29 parallel connections of the 29 capacitor C, the end after the parallel connection connects the LP2 network, and the other end connects AGND; The first magnetic bead FB1 connects with the second magnetic bead FB2, and the end after the series connection connects the LP2 network, and the other end connects the LP3 network; The 25 capacitor C 25, the 26 capacitor C 26, the 30 capacitor C 30, the 31 capacitor C 31, the 32 capacitor C 32, the 33

capacitor C

33,34 parallel connections of the 34 capacitor C, end after the parallel connection connects the LP3 network, and the other end connects AGND.One end of first resistance R 1 connects the LP3 network, and the other end connects the positive pole of the 4th capacitor C 4, and the negative pole of the 4th capacitor C 4 connects AGND; One end of the 7th capacitor C 7 connects the positive pole of the 4th capacitor C 4, and the other end connects AGND; No. 5 pins of the first supply convertor U1 and No. 4 pins all are connected the positive pole of the 4th capacitor C 4, No. 2 pin connects AGND, No. 3 pins connect an end of the 7th resistance R 7, the other end of the 7th resistance R 7 connects AGND, and No. 6 pins of the first supply convertor U1 and No. 1 pin are connected the two ends of first capacitor C 1 respectively; The negative electrode of the second diode D2 connects No. 6 pins of the first supply convertor U1, and anode connects AGND; One end of the 3rd capacitor C 3 connects No. 3 pins of the first supply convertor U1, other end connection+5V network; One end of first inductance L 1 connects No. 6 pins of the first supply convertor U1, other end connection+5V network; The negative electrode of the first diode D1 connects No. 1 pin of the first supply convertor U1, anode connection+5V network; One end connection+5V network of second resistance R 2, the other end connects No. 3 pins of the first supply convertor U1; Positive pole connection+5V the network of second capacitor C 2, the other end connects AGND.

Described analog circuit power supply as shown in Figure 8.Circuit comprises the 35 capacitor C 35, the 36 capacitor C 36, the 37 capacitor C 37, the 38 capacitor C 38, the three supply convertor U3.The model of the 3rd supply convertor U3 is LM1117T-3.3.Positive pole connection+5V the network of the 35 capacitor C 35, negative pole connects AGND; The two ends of the 37 capacitor C 37 connect the two ends of the 35 capacitor C 35 respectively; No. 3 pin connection+5V networks of the 3rd supply convertor U3, No. 2 pin connects the VDDA network, and No. 1 pin connects AGND; The positive pole of the 36 capacitor C 36 connects the VDDA network, and negative pole connects AGND; The two ends of the 38 capacitor C 38 link to each other with the two ends of the 36 capacitor C 36 respectively.

Described ground treatment circuit comprises the 3rd magnetic bead FB3 as shown in Figure 8, and an end connects AGND, and the other end connects GND and DGND.

Described MCU circuit as shown in Figure 9.Comprise the 72 resistance R 72, the 73 resistance R 73, the 74 resistance R 74, the 78 resistance R 78, the 79 resistance R 79, the 81 resistance R 81, the 82 resistance R 82, the 86 resistance R 86, the 55 capacitor C 55, the 56 capacitor C 56, the 57 capacitor C 57, the 58 capacitor C 58, the 59 capacitor C 59, the 60 capacitor C 60, the 61 capacitor C 61, the 62 capacitor C 62, the 63 capacitor C 63, the 64 capacitor C 64, the 65 capacitor C 65, the 66 capacitor C 66, the 67 capacitor C 67, the 68 capacitor C 68, the 69 capacitor C 69, the 70 capacitor C 70, the 71 capacitor C 71, EEPROM device U8, the first crystal oscillator Y1, the second crystal oscillator Y2, reference voltage chip U10, the chip U12 that resets, MCU chip U9.The model of EEPROM device U8 is 24LC16; The model of reference voltage chip U10 is REF3133; The model of chip U12 of resetting is FM809; MCU chip U9 adopts 32 MCU, and model is STM32F107VC.No. 1 pin of EEPROM device U8, No. 2 pins, No. 3 pins, No. 4 pins all are connected to DGND, No. 8 pin connection+3.3V networks, No. 6 pins are connected to No. 92 pins of MCU chip U9, and No. 5 pins of EEPROM device U8 are connected to No. 93 pins of MCU chip U9; One end connection+3.3V network of the 72 resistance R 72, the other end connects No. 6 pins of EEPROM device U8; One end connection+3.3V network of the 73 resistance R 73, the other end connects No. 5 pins of EEPROM device U8; One end connection+3.3V network of the 55 capacitor C 55, the other end connects DGND; The end of the first crystal oscillator Y1 connects an end of the 56 capacitor C 56, and the other end of the first crystal oscillator Y1 connects an end of the 57 capacitor C 57; An end that does not link to each other with the first crystal oscillator Y1 of the 56 capacitor C 56 and the 57 capacitor C 57 all is connected DGND; One end of the 78 resistance R 78 connects No. 8 pins of MCU chip U9, one end of the 79 resistance R 79 connects No. 9 pins of MCU chip U9, and the 78 resistance R 78 and that end that does not link to each other with MCU chip U9 of the 79 resistance R 79 are connected the two ends of the first crystal oscillator Y1 respectively.The end of the second crystal oscillator Y2 connects an end of the 58 capacitor C 58, and the other end connects an end of the 60 capacitor C 60; An end that does not link to each other with the second crystal oscillator Y2 of the 58 capacitor C 58 and the 60 capacitor C 60 all is connected DGND; The second crystal oscillator Y2 is connected No. 12 pins of MCU chip U9 with the 58 capacitor C 58 continuous those ends, the other end connects an end of the 82 resistance R 82; The other end of the 82 resistance R 82 connects No. 13 pins of MCU chip U9; The two ends of the 81 resistance R 81 connect the two ends of the second crystal oscillator Y2 respectively.One end connection+5V network of the 61 capacitor C 61, the other end connects AGND; No. 1 pin connection+5V network of reference voltage chip U10, No. 3 pin connects AGND, and No. 2 pin connects the VREF+ network; The positive pole of the 62 capacitor C 62 connects the VREF+ network, and negative pole connects AGND; The two ends of the 63 capacitor C 63 connect the two ends of the 62 capacitor C 62 respectively; The reset No. 3 pin connection+3.3V networks of chip U12, No. 1 pin connects DGND, and No. 2 pins connect No. 14 pins of MCU chip U9 and an end of the 59 capacitor C 59; The other end of the 59 capacitor C 59 connects DGND; One end of the 74 resistance R 74 connects No. 94 pins of MCU chip U9, and the other end connects DGND; One end of the 86 resistance R 86 connects No. 37 pins of MCU chip U9, and the other end connects DGND.The 64 capacitor C 64, the 65 capacitor C 65, the 66 capacitor C 66, the 67 capacitor C 67, the 68 capacitor C 68, the 69 capacitor C 69, the 70 capacitor C 70,71 parallel connections of the 71 capacitor C, end connection+3.3V network after the parallel connection, the other end connects DGND.No. 6 pins of MCU chip U9, No. 11 pins, No. 28 pins, No. 50 pins, No. 75 pins, No. 100 pins all connect+the 3.3V network, No. 21 pin connects the VREF+ network, No. 22 pin connects the VDDA pin, No. 19 pin connects AGND, and No. 10 pins, No. 20 pins, No. 27 pins, No. 49 pins, No. 74 pins, No. 99 pins connect DGND.

Described data acquisition circuit comprises current acquisition circuit and voltage collection circuit.The current acquisition circuit has four, and it goes into LA network, LB network, LC network, LN network that end connects rectification circuit respectively, and output connects the respective pins of MCU chip U9 in the MCU circuit respectively; The input of voltage collection circuit connects corresponding connectors respectively, and output then connects the respective pins of MCU chip U9 in the MCU circuit.

Described current acquisition circuit comprises the 25 resistance R 25, the 26 resistance R 26, the 27 resistance R 27, the 28 resistance R 28, the 29 resistance R 29, the 30 resistance R 30, the 31 resistance R 31, the 32 resistance R 32, the 33 resistance R 33, the 34 resistance R 34, the 35 resistance R 35, the 36 resistance R 36, the 37 resistance R 37, the 38 resistance R 38, the 39 resistance R 39, the 40 resistance R 40, the 41 resistance R 41, the 42 resistance R 42, the 43 resistance R 43, the 44 resistance R 44, the 45 resistance R 45, the 46 resistance R 46, the 47 resistance R 47, the 48 resistance R 48, the 49 resistance R 49, the 50 resistance R 50, the 51 resistance R 51, the 39 capacitor C 39, the 40 capacitor C 40, the 41 capacitor C 41, the 42 capacitor C 42, the 43 capacitor C 43, the 44 capacitor C 44, the 45 capacitor C 45, the 46 capacitor C 46, the 47 capacitor C 47, the 48 capacitor C 48, the 49 capacitor C 49, the 50 capacitor C 50, the first operational amplifier U5, the second operational amplifier U6, gating chip U4.The model of the first operational amplifier U5 and the second operational amplifier U6 is LM224, and the model of gating chip U4 is MC74HC4053.

A phase acquisition circuit in the current acquisition circuit as shown in figure 10.The 29 resistance R 29 1 ends connect the LA network in the rectification circuit, and the other end connects No. 6 pins of the second operational amplifier U6, and the two ends of the 30 resistance R 30 connect No. 6 pins and No. 7 pins of the second operational amplifier U6 respectively; One end of the 25 resistance R 25 connects No. 14 pins of gating chip, and the other end connects No. 7 pins of the second operational amplifier U6; No. 4 pin connection+5V networks of the second operational amplifier U6, No. 6 pins connect No. 12 pins of gating chip, No. 5 and No. 2 pins connection AGND of the second operational amplifier U6; The 37 resistance R 37 1 ends connect No. 7 pins of the second operational amplifier U6, and the other end connects an end of the 33 resistance R 33 and an end of the 43 capacitor C 43; The other end of the 33 resistance R 33 connects No. 5 pins of the first operational amplifier U5; The other end of the 43 capacitor C 43 connects No. 7 pins of the second operational amplifier U5; One end of the 39 capacitor C 39 connects No. 5 pins of the first operational amplifier U5, and the other end connects AGND; No. 4 pin connection+5V networks of the first operational amplifier U5, No. 6, No. 7 pin links together; One end of the 31 resistance R 31 connects No. 7 pins of the first operational amplifier U5, and the other end connects the AAD network; The 40 capacitor C 40 is in parallel with the 34 resistance R 34, and the end after the parallel connection connects AGND, and the other end connects the AAD network; AAD connects No. 29 pins of MCU chip U9 in the MCU circuit.The circuit of above-mentioned form has 3, except A phase current Acquisition Circuit, also comprises B phase current Acquisition Circuit, C phase current Acquisition Circuit.A phase current Acquisition Circuit connects the LA network, and corresponding with it, other two circuit connect LB network, LC network respectively; A phase current Acquisition Circuit connects No. 12 pins of gating chip U4, and corresponding with it, other two circuit connect No. 2 pins and No. 5 pins of gating chip U4 respectively; A phase current Acquisition Circuit connects No. 14 pins of gating chip U4, and corresponding with it, other two circuit connect No. 15 pins of gating chip U4, No. 4 pins respectively.No. 6 pins of gating chip U4, No. 9 pins, No. 10 pins, No. 11 pins connect No. 1 pin of MCU chip U9 in the MCU circuit, No. 98 pins, No. 97 pins, No. 96 pins respectively.

N phase acquisition circuit in the current acquisition circuit as shown in figure 11.One end of the 42 resistance R 42 connects the LN network in the rectification circuit, and the other end connects No. 13 pins of the second operational amplifier U6, and the two ends of the 43 resistance R 43 connect No. 13 pins and No. 14 pins of the second operational amplifier U6 respectively; No. 4 pin connection+5V networks of the second operational amplifier U6, No. 12 pins and No. 11 pins connect AGND; One end of the 51 resistance R 51 connects No. 14 pins of the second operational amplifier U6, and the other end connects an end of the 48 resistance R 48 and an end of the 50 capacitor C 50; The other end of the 48 resistance R 48 connects No. 12 pins of the first operational amplifier U5; The other end of the 50 capacitor C 50 connects No. 14 pins of the first operational amplifier U5; One end of the 46 capacitor C 46 connects No. 12 pins of the first operational amplifier U5, and the other end connects AGND; No. 4 pin connection+5V networks of the first operational amplifier U5, No. 13, No. 14 pin links together; One end of the 45 resistance R 45 connects No. 14 pins of the first operational amplifier U5, and the other end connects the NAD network; The 48 capacitor C 48 is in parallel with the 49 resistance R 49, and the end after the parallel connection connects AGND, and the other end connects the NAD network; No. 32 pins of MCU chip U9 in the NAD network connection MCU circuit.

Described voltage collection circuit comprises the 6th connector J6, the 52 resistance R 52, the 53 resistance R 53, the 54 resistance R 54, the 55 resistance R 55, the 56 resistance R 56, the 57 resistance R 57, the 58 resistance R 58, the 59 resistance R 59, the 60 resistance R 60, the 61 resistance R 61, the 62 resistance R 62, the 63 resistance R 63, the 64 resistance R 64, the 65 resistance R 65, the 66 resistance R 66, the 67 resistance R 67, the 68 resistance R 68, the 69 resistance R 69, the 70 resistance R 70, the 71 resistance R 71, the 123 resistance R 123, the 124 resistance R 124, the 125 resistance R 125, the 127 resistance R 127, the 128 resistance R 128, the 129 resistance R 129, the 130 resistance R 130, the 131 resistance R 131, the 133 resistance R 133, the 134 resistance R 134, the 135 resistance R 135, the 136 resistance R 136, the 137 resistance R 137, the 138 resistance R 138, the 139 resistance R 139, the 141 resistance R 141, the 51 capacitor C 51, the 52 capacitor C 52, the 53 capacitor C 53, the 54 capacitor C 54, the 92 capacitor C 92, the 93 capacitor C 93, the 94 capacitor C 94, the 95 capacitor C 95, the 96 capacitor C 96, the 97 capacitor C 97, the 98 capacitor C 98, the 99 capacitor C 99, the three operational amplifier U7.The model of the 3rd operational amplifier U7 is LM224.

A phase voltage Acquisition Circuit in the voltage collection circuit as shown in figure 12.One end of the 52 resistance R 52 connects AGND, and the other end connects No. 2 pins of the 3rd operational amplifier U7; One end of the 53 resistance R 53 connects No. 2 pins of the 3rd operational amplifier U7, and the other end connects No. 1 pin of the 3rd operational amplifier U7; The 57 resistance R 57 is connected with the 58 resistance R 58, the end connection+5V network after the series connection, and the other end connects No. 3 pins of the 3rd operational amplifier U7; No. 3 pins of the 3rd operational amplifier U7 connect the MA network, No. 4 pin connection+5V networks, and No. 11 pin connects AGND, and No. 1 pin connects an end of the 56 resistance R 56; The other end of the 56 resistance R 56 connects No. 33 pins of MCU chip in an end of the 51 capacitor C 51 and the MCU circuit, and the other end of the 51 capacitor C 51 connects AGND; One end of the 92 capacitor C 92 connects the 6th connector J6, the other end connects an end of the 123 resistance R 123, the other end of the 123 resistance R 123 connects an end of the 124 resistance R 124, the other end of the 124 resistance R 124 connects an end of the 125 resistance R 125, and the other end of the 125 resistance R 125 connects the MA network; The 93 capacitor C 93 is in parallel with the 127 resistance R 127, and the end after the parallel connection connects the MA network, and the other end connects AGND.Circuit with above-mentioned annexation has 4, except A phase voltage Acquisition Circuit, also comprises B phase voltage Acquisition Circuit, C phase voltage Acquisition Circuit, N phase voltage Acquisition Circuit.Foregoing circuit connects No. 33 pins of MCU chip in the MCU circuit, and corresponding with it, its excess-three circuit connects No. 34 pins of MCU chip in the MCU circuit, No. 35 pins, No. 36 pins respectively.

The man-machine interface circuit comprises liquid crystal display circuit, led circuit, key circuit, coding switch circuit.They link to each other with the MCU circuit respectively.

Described liquid crystal display circuit is shown in a figure among Figure 13.Circuit comprises LCD U14, the 72 capacitor C 72, the 76 capacitor C 76, the 77 capacitor C 77, the 78 capacitor C 78, the 79 capacitor C 79, the 80 capacitor C 80, the 81 capacitor C 81, the 82 capacitor C 82.The model of LCD U14 is KMC12232-A-00-SGA.No. 1 pin of LCD U14, No. 2 pins, No. 3 pins, No. 4 pins, No. 5 pins connect No. 64 pins of MCU chip U9 in the MCU circuit respectively, No. 63 pins, No. 62 pins, No. 61 pins, No. 60 pins, No. 7 pins of LCD U14 connect DGND, No. 8 pins of LCD U14, No. 14 pins, No. 15 pins, No. 16 pins, No. 17 pins, No. 18 pin connects the 82 capacitor C 82 respectively, the 77 capacitor C 77, the 78 capacitor C 78, the 79 capacitor C 79, the 80 capacitor C 80, the 81 capacitor C 81 end separately, these electric capacity other end separately all connects DGND; No. 9 pins of LCD U14 link to each other with No. 8 pins; The two ends of the 76 capacitor C 76 connect No. 10 pins and No. 11 pins of LCD U14 respectively; The two ends of the 72 capacitor C 72 connect No. 12 pins and No. 13 pins of LCD U14 respectively.

Described key circuit has 5, and one in the key circuit shown in b figure among Figure 13.Key circuit comprises the 92 resistance R 92, the 93 resistance R 93, the 94 resistance R 94, the 95 resistance R 95, the 96 resistance R 96, the first button S1, the second button S2, the 3rd button S3, the 4th button S4, the 5th button S5.One end connection+3.3V network of the 92 resistance R 92, the other end connect No. 71 pins of MCU chip U9 in the MCU circuit and the end of the first button S1; The other end of the first button S1 connects DGND.One end connection+3.3V network of the 93 resistance R 93, the other end connect No. 70 pins of MCU chip U9 in the MCU circuit and the end of button S2; The other end of the second button S2 connects DGND.One end connection+3.3V network of the 94 resistance R 94, the other end connect No. 66 pins of MCU chip U9 in the MCU circuit and the end of the 3rd button S3; The other end of the 3rd button S3 connects DGND.One end connection+3.3V network of the 95 resistance R 95, the other end connect No. 65 pins of MCU chip U9 in the MCU circuit and the end of the 4th button S4; The other end of the 4th button S4 connects DGND.The 96 resistance R 96 1 end connection+3.3V networks, the other end connect No. 54 pins of MCU chip U9 in the MCU circuit and the end of the 5th button S5; The other end of the 5th button S5 connects DGND.

Described led circuit has 3, and one of them of led circuit is shown in c figure among Figure 13.Led circuit comprises the 91 resistance R 91, the 97 resistance R 97, the 102 resistance R 102, the 3rd light-emitting diode DS3, the 4th light-emitting diode DS4, the 5th light-emitting diode DS5.One end of the 91 resistance R 91 connects No. 44 pins of MCU chip U9 in the MCU circuit, and the other end connects the anode of the 3rd light-emitting diode DS3; The negative electrode of the 3rd light-emitting diode DS3 connects DGND.One end of the 97 resistance R 97 connects No. 45 pins of MCU chip U9 in the MCU circuit, and the other end connects the anode of the 4th light-emitting diode DS4; The negative electrode of the 4th Light-Emitting Diode DS4 connects DGND.One end of the 102 resistance R 102 connects No. 46 pins of MCU chip U9 in the MCU circuit, and the other end connects the anode of the 5th Light-Emitting Diode DS5; The negative electrode of the 5th Light-Emitting Diode DS5 connects DGND.

Described coding switch circuit has 2, and one of them of coding switch circuit is shown in d figure among Figure 13.Coding switch circuit comprises the 87 resistance R 87, the 88 resistance R 88, the 89 resistance R 89, the 90 resistance R 90, the 98 resistance R 98, the 99 resistance R 99, the 100 resistance R 100, the 101 resistance R 101, the first code switch U11, the second code switch U13.The 87 resistance R 87, the 88 resistance R 88, the 89 resistance R 89, the 90 resistance R 90 one termination+3.3V network separately, the other end connect No. 2 pins of the first code switch U11, No. 3 pins, No. 4 pins, No. 5 pins respectively; No. 1 pin of the first code switch U11, No. 6 pins connect DGND, and No. 2 pins of the first code switch U11, No. 3 pins, No. 4 pins, No. 5 pins connect No. 88 pins of MCU chip U9 in the MCU circuit, No. 86 pins, No. 85 pins, No. 84 pins respectively.The 98 resistance R 98, the 99 resistance R 99, the 100 resistance R 100, the 101 resistance R 101 one termination+3.3V network separately, the other end connect No. 2 pins of the second code switch U13, No. 3 pins, No. 4 pins, No. 5 pins respectively; No. 1 pin of the second code switch U13, No. 6 pins connect DGND, and No. 2 pins of the second code switch U13, No. 3 pins, No. 4 pins, No. 5 pins connect No. 83 pins of MCU chip U9 in the MCU circuit, No. 82 pins, No. 81 pins, No. 80 pins respectively.

Communication module comprises ethernet interface circuit and RS485 interface circuit.Ethernet interface circuit links to each other with the MCU circuit by the MII interface; The RS485 interface circuit connects the MCU circuit.

Described ethernet interface circuit as shown in figure 14.Circuit comprises the first exclusion RN1, the second exclusion RN2, the 3rd exclusion RN3, the 4th exclusion RN4, the 5th exclusion RN5, the 6th exclusion RN6, the 84 resistance R 84, the 111 resistance R 111, the 112 resistance R 112, the 119 resistance R 119, the 121 resistance R 121, the 116 resistance R 116, the 117 resistance R 117, the 113 resistance R 113, the 108 resistance R 108, the 110 resistance R 110, the 109 resistance R 109, the 73 capacitor C 73, the 74 capacitor C 74, the 75 capacitor C 75, the 83 capacitor C 83, the 84 capacitor C 84, the 85 capacitor C 85, the 86 capacitor C 86, the 87 capacitor C 87, the 88 capacitor C 88, the 89 capacitor C 89, the 90 capacitor C 90, the 3rd crystal oscillator Y3, Ethernet PHY controller U15, RJ45 interface CN3.The model of Ethernet PHY controller U15 is DP83848I; The model of RJ45 interface CN3 can be selected HR911105A.The 73 capacitor C 73, the 74 capacitor C 74,75 parallel connections of the 75 capacitor C, the end connection+3.3V network after the parallel connection, the other end connects DGND.One end of the 111 resistance R 111 connects No. 7 pins of Ethernet PHY controller U15, and the other end connects an end of the 84 resistance R 84; The other end of the 84 resistance R 84 connects No. 53 pins of MCU chip U9 in the MCU circuit.The 112 resistance R 112 1 end connection+3.3V networks, the other end connect No. 7 pins of Ethernet PHY controller U15.No. 1 pin of the 6th exclusion RN6, No. 2 pins, No. 3 pins, No. 4 pins connect No. 13 pins of Ethernet PHY controller U15, No. 14 pins, No. 16 pins, No. 17 pins respectively, No. 5 pins of the 6th exclusion RN6, No. 6 pins, No. 7 pins, No. 8 pin connection+3.3V networks.The 116 resistance R 116 and the 117 resistance R 117 1 end connection+3.3V networks, the other end connects No. 20 pins of Ethernet PHY controller U15, No. 21 pins respectively.The 85 capacitor C 85, the 86 capacitor C 86, the 87 capacitor C 87,88 parallel connections of the 88 capacitor C, end after the parallel connection connects DGND, the other end connects RFB network, No. 18 pins, No. 23 pins, No. 37 pins of RFB network connection Ethernet PHY controller U15.One end of the 113 resistance R 113 connects DGND, and the other end connects No. 24 pins of Ethernet PHY controller U15.No. 5 pins of the 5th exclusion RN5, No. 6 pins, No. 7 pins, No. 8 pins and+3.3V network connection, No. 1 pin of the 5th exclusion RN5, No. 2 pins, No. 3 pins connect No. 28 pins of Ethernet PHY controller U15, No. 27 pins, No. 26 pins respectively.One end connection+3.3V network of the 109 resistance R 109, the other end connect No. 30 pins of Ethernet PHY controller U15.The 110 resistance R 110 1 ends connect No. 25 pins of MCU circuit MCU chip U9, and the other end connects No. 30 pins of Ethernet PHY controller U15.The 83 capacitor C 83 is connected DGND respectively with an end of the 84 capacitor C 84, and the other end connects the two ends of the 3rd crystal oscillator Y3 respectively.The end of the 3rd crystal oscillator Y3 connects No. 34 pins of Ethernet PHY controller U15, and the other end connects an end of the 108 resistance R 108; The other end of the 108 resistance R 108 connects No. 33 pins of Ethernet PHY controller U15.No. 22 pins of Ethernet PHY controller U15, No. 32 pins, No. 48 pin connection+3.3V networks; No. 15 pins of Ethernet PHY controller U15, No. 19 pins, No. 35 pins, No. 36 pins, No. 47 pins connect DGND; No. 29 pins of Ethernet PHY controller U15 are connected to No. 14 pins of MCU circuit MCU chip U9; No. 1 pin of Ethernet PHY controller, No. 5 pins, No. 6 pins, No. 45 pins connect the end of the 3rd exclusion RN3 respectively, and the other end of the 3rd exclusion RN3 connects No. 18 pins of MCU circuit MCU chip U9, No. 17 pins, No. 95 pins, No. 58 pins successively respectively.No. 2 pins of Ethernet PHY controller, No. 3 pins, No. 4 pins connect the end of the 4th exclusion RN4 respectively, and the other end of the 4th exclusion RN4 connects No. 48 pins of MCU circuit MCU chip U9, No. 51 pins, No. 52 pins successively respectively.No. 40 pins of Ethernet PHY controller, No. 41 pins, No. 42 pins, No. 46 pins connect the end of the first exclusion RN1 respectively, and the other end of the first exclusion RN1 connects No. 23 pins of MCU chip U9 in the MCU circuit, No. 47 pins, No. 26 pins, No. 59 pins successively respectively.No. 38 pins of Ethernet PHY controller U15, No. 39 pins, No. 43 pins, No. 44 pins connect the end of the second exclusion RN2 respectively, and the other end of the second exclusion RN2 is connected to No. 24 pins of MCU chip U9 in the controller circuitry, No. 55 pins, No. 56 pins, No. 57 pins successively respectively.No. 1 pin of RJ45 interface CN3, No. 2 pins, No. 3 pins, No. 6 pins, No. 10 pins, No. 11 pins connect No. 17 pins of Ethernet PHY controller U15, No. 16 pins, No. 14 pins, No. 13 pins, No. 28 pins, No. 26 pins respectively; No. 9 pins of RJ45 interface CN3, No. 12 pins connect the 121 resistance R 121, the 119 resistance R 119 end separately respectively, and an other end of these two resistance all connects+the 3.3V network; No. 8 pins of RJ45 interface CN3 connect AGND; No. 4 pins of RJ45 interface CN3, No. 5 pin connection+3.3V networks.

Described RS485 interface circuit as shown in figure 15.Circuit comprises transceiver U16, common mode inhibition device T1, the 114 resistance R 114, the 115 resistance R 115,118 resistance R 118, the 120 resistance R 120, the 122 resistance R 122, the 91 capacitor C 91, the five connector J5.Transceiver U16 model is SP3485; The model of common mode inhibition device T1 is B82789C0513.One end connection+3.3V network of the 114 resistance R 114, the other end connects No. 6 pins of transceiver U16; The two ends of the 118 resistance R 118 connect No. 6 pins of transceiver U16, No. 7 pins respectively; One end of the 122 resistance R 122 connects DGND, and the other end connects No. 7 pins of transceiver U16.The two ends of the 91 capacitor C 91 connect DGND and+3.3V network respectively.No. 1 pin of transceiver U16, No. 2 pins, No. 3 pins, No. 4 pins connect No. 79 pins of MCU chip U9 in the MCU circuit, No. 43 pins, No. 43 pins, No. 78 pins respectively; No. 8 pins of transceiver U16, No. 5 pins connect respectively+3.3V network and DGND; No. 6 pins of transceiver U16 connect an end of resistance R 115, and the other end of the 115 resistance R 115 connects No. 3 pins of common mode inhibition device T1; No. 7 pins of transceiver U16 connect an end of the 120 resistance R 120, the other end of the 120 resistance R 120 connects No. 1 pin of common mode inhibition device T1.No. 2 pins of common mode inhibition device T1, No. 4 pins link to each other with the 5th connector J5 respectively.

Remote control module comprises executive circuit, state output circuit, feedback circuit.Executive circuit, state output circuit, feedback circuit are connected to the MCU circuit respectively.

Described executive circuit has 2, circuit comprises the 75 resistance R 75, the 76 resistance R 76, the 77 resistance R 77, the 80 resistance R 80, the 83 resistance R 83, the 85 resistance R 85, the 126 resistance R 126, the 132 resistance R 132, the 4th optocoupler isolator U20, the 6th optocoupler isolator U22, the first light-emitting diode DS1, the second light-emitting diode DS2, the 15 diode D15, the 16 diode D16, first relay K 1, second relay K 2, the 8th connector J8, the tenth connector CN1, the tenth a connector CN2, the first triode Q4, the second triode Q5.The model of the 4th photoelectrical coupler U20, the 6th photoelectrical coupler U22 is TLP-181.In the executive circuit one of them is shown in a figure among Figure 16.No. 1 pin of the 4th optocoupler isolator U20 connects an end of the 126 resistance R 126, the other end connection+3.3V network of the 126 resistance R 126; No. 3 pins of the 4th optocoupler isolator U20 are connected to No. 39 pins that connect MCU chip U9 in the MCU circuit, No. 4 pin connection-24V networks of the 4th optocoupler isolator U20; No. 6 pins of the 4th optocoupler isolator U20 connect an end of the 77 resistance R 77, and the other end of the 77 resistance R 77 connects the base stage of the first triode Q4; One end connection+24V network of the 76 resistance R 76, the other end connects the base stage of the first triode Q4; The emitter of the first triode Q4 connects the negative electrode of the first light-emitting diode DS1, the collector electrode connection-24V network of the first triode Q4.The anode of the first light-emitting diode DS1 connects an end of the 75 resistance R 75; Other end connection+24V the network of the 75 resistance R 75.The 15 diode D15 is in parallel with the input of first relay K 1, and the negative electrode connection+24V network of the 15 diode D15, the anode of the 15 diode D15 connect the first triode Q4 emitter; The output of first relay K 1 links to each other with the tenth connector CN1.Another one in the executive circuit is identical with foregoing circuit.The 4th optocoupler isolator U20 No. 3 pins are connected to No. 39 pins that connect MCU chip U9 in the MCU circuit in the foregoing circuit, and corresponding with it, the respective pins of another one executive circuit is connected to No. 38 pins of MCU chip U9 in the MCU circuit.

Described state output circuit and state-feedback circuit comprise the 13 resistance R 13, the 17 resistance R 17, the 22 R22, the 140 resistance R 140, the 142 resistance R 142, the first optocoupler isolator U17, the second optocoupler isolator U18, the 3rd optocoupler isolator U19, the 4th optocoupler isolator U21, the 7th connector J7, the 9th connector J9.The model of the first optocoupler isolator U17, the second optocoupler isolator U18, the 3rd optocoupler isolator U19, the 4th optocoupler isolator U21 is TLP-181.The state output circuit has 3, and one of them is shown in b figure among Figure 16.Wherein in the state output circuit, one end connection+3.3V network of the 13 resistance R 13, the other end connects No. 1 pin of the first optocoupler isolator U17, No. 3 pins of the first optocoupler isolator U17 connect No. 40 pins of MCU chip U9 in the MCU circuit, No. 4 pin connection-24V networks of the first optocoupler isolator U17, No. 6 pins of the first optocoupler isolator U17 link to each other with connector J9.The circuit of above-mentioned annexation has 3.The first optocoupler isolator U17 No. 3 pins are connected to No. 40 pins of MCU chip U9 in the MCU circuit in the foregoing circuit, corresponding with it, the respective pins of two other state output circuit is connected to No. 41 pins of MCU chip U9 in the MCU circuit, No. 42 pins respectively.In four pins of the 9th connector J9, wherein three link to each other another one connection-24V network respectively with three state output circuits.State-feedback circuit is shown in c figure among Figure 16.No. 1 pin of the 5th optocoupler isolator U21 connects an end of the 140 resistance R 140, the other end of the 140 resistance R 140 links to each other with the pin of the 7th connector J7, another pin of the 7th connector J7 connects No. 3 pins of the 5th optocoupler isolator U21, No. 6 pins of the 5th optocoupler isolator U21 are connected to an end of the 142 resistance R 142, other end connection+3.3V the network of the 142 resistance R 142, No. 6 pins of the 5th photoelectrical coupler U21 connect No. 87 pins of MCU chip U9 in the MCU circuit, and No. 4 pins of the 5th photoelectrical coupler U21 photoelectrical coupler connect DGND.

In the above-mentioned circuit for remotely controlling ,-24V network ,+the 24V network connects No. 1 pin and No. 2 pins of connector J8 respectively, as shown in figure 16.

Described emulation interface circuit as shown in figure 17.Circuit comprises the 103 resistance R 103, the 104 resistance R 104, the 105 resistance R 105, the 106 resistance R 106, the 107 resistance R 107, the 12 connector JP1.One end connection+3.3V networking of the 103 resistance R 103, the other end links to each other with No. 1 pin of the 12 connector JP1, one end connection+3.3V networking of the 104 resistance R 104, the other end links to each other with No. 3 pins of the 12 connector JP1, one end connection+3.3V networking of the 105 resistance R 105, the other end links to each other with No. 4 pins of the 12 connector JP1, one end connection+3.3V networking of the 106 resistance R 106, the other end links to each other with No. 5 pins of the 12 connector JP1, one end of the 107 resistance R 107 connects DGND, and the other end links to each other with No. 2 pins of the 12 connector JP1.No. 1 pin of the 12 connector JP1, No. 2 pins, No. 3 pins, No. 4 pins, No. 5 pins, No. 6 pins connect No. 89 pins of MCU chip U9 in the MCU circuit, No. 76 pins, No. 72 pins, No. 77 pins, No. 90 pins, No. 14 pins respectively.No. 7 pin connection+3.3V networks of the 12 connector JP1, No. 8 pins of the 12 connector JP1 connect DGND.

The concrete course of work of the present invention is:

Controller of the present invention is connected the low-pressure plastic shell circuit breaker release, and insert low voltage electric network, described power circuit produces Vzs, 5V, 3.3V voltage, for entire controller provides power supply; Acquisition Circuit provides voltage, current information to the MCU circuit; The MCU circuit is accepted these information, calculates electric parameter, execute protection function, record trouble data, and is undertaken alternately by man-machine interface; Communication module realizes the interconnected of controller and long-range PC; Remote control module can access the state information of release, for combined floodgate, separating brake, reset instruction provide driving.The controller main program flow chart as shown in Figure 2.

As shown in Figure 3, Figure 4, obtain alternating current from the power network line induction respectively by a current transformer that adds, the mutual inductance electric current of secondary side output is respectively through after the first rectifier bridge BG1, the second rectifier bridge BG2, the 3rd rectifier bridge BG3, the 4th rectifier bridge BG4 rectification, the stack of four phase output terminals, utilize the principle of capacitance energy storage that current signal is converted to voltage signal, so that Monitoring and Controlling.The MCU chip is gathered the voltage at PAD place, obtain the authigenic power supply information of voltage, in conjunction with current power network current, by certain control strategy, output pwm signal, control the ON time and turn-off time ratio of the first N-channel MOS pipe Q1, determine to flow through the electric current of the 3rd diode D3, thereby stablize authigenic power supply voltage.

As shown in Figure 5, be reserved with the external power source interface among the present invention, can be too small at the distribution line electric current, be the controller power supply when authigenic power supply can't provide power supply.When electrical network did not break down, TRIPPWR kept low level by MCU always, made the second N-channel MOS pipe Q2 be in cut-off state, and do not have electric current flow through, so release be failure to actuate because tripping coil interface the 4th connector J4 two ends do not have pressure reduction this moment.Break down when sample circuit detects circuit, MCU sends the instruction of threading off, and controls the second N-channel MOS pipe Q conducting, and this moment, supply voltage was added in the tripping coil two ends, thereby drives the release action.

As shown in Figure 6, be in stablely substantially through the voltage after the authigenic power supply conditioning, produce the required 5V of controller work and 3.3V power supply respectively by the first supply convertor U1, the second two supply convertor U2.Before the supply convertor input, added compound filter circuit---RC among the present invention πThe type filter circuit.The 11 capacitor C 11, the 18 capacitor C 18 are tantalum electric capacity, strobe.For guaranteeing the withstand voltage of front end electric capacity, therefore bear voltage jointly with the 11 capacitor C 11, the 18 capacitor C 18, and increase the 16 resistance R 16,21 two divider resistances of the 21 resistance R.

As shown in Figure 9, in the MCU circuit, extend out eeprom chip by iic bus, with the flexible storage data, as protection parameter, failure logging etc.In order from hardware circuit, to guarantee the reliability of controller, added the chip U12 that resets in the main control chip outside, can prevent effectively that controller from flying because electricity shortage causes control program to run, deadlock or misoperation.

As shown in figure 10, the function of data acquisition circuit is with the electric current in the distribution system, voltage signal after treatment, convert to MCU the A/D port the voltage signal that can accurately identify.MCU chip U9 gathers these signals, and calculates the every electrical quantity in the electrical network, and realizes defencive function on this basis.Electric current in the protection circuit needs rectifier bridge to carry out rectification after changing by current transformer, is example mutually with A, and the 8th resistance R 8 is converted into voltage signal.And owing to line current in the electrical network changes greatly, take different multiples to handle according to the amplitude of signal, utilize operational amplifier and gating chip to give signal with different multiplication factors, the voltage signal assignment at AD pin place is in the analog-to-digital linear zone, improve the precision of gathering.

As shown in figure 12, because line voltage excursion in system's running is little, need not consider signal multiplying power problem.Therefore can isolate by utilizing electric capacity, electric resistance partial pressure is obtained the voltage acquisition signal, flows to MCU chip U9 through filtering, computing after amplifying then.Utilize 5V voltage to the conditioning that superposes of voltage after partial signal, supply with UAA range of signal control that MCU gathers in 0 ~ 3V.

As shown in figure 13, LED light is used to refer to the different work running status of circuit breaker.Wherein three LED are set to green, yellow, redness respectively, are used to refer to normal operating conditions, overload pre-alarm and serious overload-alarm respectively.The present invention has designed 5 key switches and a LCD altogether, shows by button and liquid crystal display screen, realizes the setting to the checking of various electric parameters, set point.The present invention designs two code switchs, is used for coarse adjustment set point on a large scale.

As shown in figure 14, the MCU chip is STM32F107 among the present invention, and this built-in chip type has the media access control layer that satisfies ethernet communication; Network card chip is DP83848C.The present invention adopts the transmission rate of Media Independent Interface (MII) and 100M.Can realize communicating by letter of circuit breaker and long-range PC by Ethernet, realize functions such as protection parameter setting and inquiry, electrical quantity inquiry, running state information inquiry, failure logging inquiry.

As shown in figure 15,485 communications are another kind of communication modes of the present invention, can realize the same energy identical with ethernet communication.Transceiver U16 model is SP3485EN, and this chip internal contains each one of receiver and driver.RO and DI port are respectively the output of receiver and the input of driver, respectively RXD are linked to each other with the TXD interface interface corresponding with MCU chip U9 when carrying out exchanges data with MCU; RE and DE as the data transmit-receive enable port of chip, use the control pin of MCU chip U9 to control this two Enable Pins simultaneously.Voltage when the last pull down resistor on transmitter A, the B line is in idle condition in order to keep the chip transmitting-receiving.For reliability and the antijamming capability that improves transceiver, the present invention has increased the common mode choke chip with common mode inhibition function at the transmitting-receiving interface of transceiver U16, this common mode choke chip can effectively suppress coupled interference and reduce holding wire to the interference of other devices, thereby emc issue occurs in the anti-locking system, improve reliability.

As shown in figure 16, remote control module is the parts of control divide-shut brake in the intelligent breaker, is the indispensable annex that user side is realized the remote control circuit breaker.User side sends to controller by long-range PC monitoring interface that the related command signal is realized combined floodgate, the separating brake of circuit breaker and operation such as reset.Feed motion refers to that the release state is from OFF to ON; Separating brake refers to refer to that the release state is from ON to OFF; Reset and refer to then refer to that the release state is from TRIP to OFF.ETRIP_ON and ETRIP_OFF end signal are low under the initial condition, when needs disconnect circuit breaker, long-range PC is put height by MCU with ETRIP_OFF, the 4th photoelectrical coupler U20 makes relay K 1 closure by controlling the first triode Q4 conducting, form the closing circuit of motor-operating mechanism, the motor in the electrically operated institution is just changeing the pulling handle and is putting the ON state; Similarly, when the needs breaker closing, ETRIP_ON is put height, by relay control electricity behaviour's motor counter-rotating, circuit breaker is put ON close a floodgate again.

Claims

1. based on the intelligent low-pressure breaker of plastic casing controller of ethernet communication, formed by power supply and trip circuit, MCU circuit, data acquisition circuit, man-machine interface circuit, communication module and remote control module, it is characterized in that:

Power supply and trip circuit comprise rectification circuit, authigenic power supply circuit, external power source interface and dropout interface circuit, system works power circuit;

Described rectification circuit comprises the first rectifier bridge BG1, the second rectifier bridge BG2, the 3rd rectifier bridge BG3, the 4th rectifier bridge BG4, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10, the 11 resistance R 11, the five capacitor C 5, the 6th capacitor C 6, the 8th capacitor C 8, the 9th capacitor C 9, the first connector J1, the second connector J2; Wherein the inlet wire of the first rectifier bridge BG1 connects No. 1, No. 2 ports of the first connector J1 in the A commutating phase circuit, the outlet anode connects the LP1 network, negative terminal connects an end of the 3rd resistance R 3, the other end of the 3rd resistance R 3 connects an end of LA network and the 5th capacitor C 5, and the other end of the 5th capacitor C 5 connects GND; One end of the 8th resistance R 8 connects the outlet negative terminal of the first rectifier bridge BG1, and the other end of the 8th resistance R 8 connects GND; The circuit of structure has four as mentioned above, except A commutating phase circuit, also comprises B commutating phase circuit, C commutating phase circuit, N commutating phase circuit, and the end of going into of their rectifier bridge connects the first connector J1 or the second connector J2 respectively; The LA network is corresponding with connecting, corresponding LB network, LC network, the LN network of connecting respectively of its excess-three circuit;

Described authigenic power supply circuit comprises the 14 resistance R 14, the 19 resistance R 19, the 20 resistance R 20, the 15 capacitor C 15, the 16 capacitor C 16, the 17 capacitor C 17, the 19 capacitor C 19, Transient Suppression Diode D13, the first N-channel MOS pipe Q1, the 3rd diode D3, the 12 diode D12; The negative electrode of transient state killer tube D13 connects the LP1 network, and the anode of transient state killer tube D13 connects GND; The grid of the first N-channel MOS pipe Q1 connects an end of the 12 diode D12 negative electrode and the 19 resistance R 19, and the other end of the 19 resistance R 19 connects GND; The source electrode of the first N-channel MOS pipe Q1 connects the LP1 network, and the drain electrode of the first N-channel MOS pipe Q1 connects GND; The anode of the 12 diode D12 connects No. 69 control output pins of MCU chip U9 in the MCU circuit; The anode of the 3rd diode D3 connects the LP1 network, and the negative electrode of the 3rd diode D3 connects the Vzs network; One end of the 17 capacitor C 17 connects the Vzs network, and the other end connects GND; The positive pole of the 15 capacitor C 15 connects the Vzs network, and negative pole connects GND; The positive pole of the 16 capacitor C 16 connects the Vzs network, and negative pole connects GND; One end of the 14 resistance R 14 connects the Vzs network, and the other end connects the PAD network; One end of the 20 resistance R 20 connects the PAD network, and the other end connects GND; One end of the 19 capacitor C 19 connects the PAD network, and the other end connects GND; The PAD network is linked No. 15 input pins of MCU chip U9 in the MCU circuit;

Described external power source and dropout interface circuit comprise the 4th diode D4, the 7th diode D7, the 8th diode D8, the tenth diode D10, the 14 diode D14, the 14 capacitor C 14, the 21 capacitor C 21, the 24 resistance R 24, the second N-channel MOS pipe Q2, the 3rd connector J3, the 4th connector J4; The model of the 4th diode D4, the 7th diode D7, the 8th diode D8, the tenth diode D10, the 14 diode D14 can be selected MBR0540, and the model of the second N-channel MOS pipe Q2 can be selected STD35NF06L; The 7th diode D7 negative electrode connects the Vzs network, and anode connects the OUTPOWER network; GND connects the OUTGND network; OUTPWR network and OUTGND network are connected to the 3rd connector J3 respectively; The 8th diode D8 anode connects the Vzs network, and negative electrode connects the tenth diode D10 negative electrode; The anode of the tenth diode D10 connects the source electrode of the second N-channel MOS pipe Q2; The two ends of the 4th connector J4 connect the two poles of the earth of the tenth diode D10 respectively; The drain electrode of the second N-channel MOS pipe Q2 connects GND, and grid connects the negative electrode of the 14 diode D14, and the anode of the 14 diode D14 connects No. 68 pins of MCU chip U9 in the MCU circuit; The 21 capacitor C 21 is in parallel with the 24 resistance R 24, and the two ends after the parallel connection connect grid and the GND of the second N-channel MOS pipe Q2 respectively; The 4th diode D4 anode connects the Vzs network, and negative electrode connects the LP2 network; The 14 capacitor C 14 1 ends connect the LP2 network, and the other end connects GND;

Described system works power circuit comprises+the 3.3V power circuit ,+5V power circuit, analog circuit power supply, treatment circuit; + 3.3V power circuit connects LP2 network and+3.3V network; + 5V power circuit connects LP2 network and+5V network; Analog circuit power supply connection+5V network and VDDA; The ground treatment circuit connects AGND, GND and DGND;

Described+3.3V power circuit comprises second source converter U2, the 5th diode D5, the 6th diode D6, the 11 diode D11, the 12 resistance R 12, the 15 resistance R 15, the 16 resistance R 16, the 18 resistance R 18, the 21 resistance R 21, the 23 resistance R 23, the tenth capacitor C 10, the 11 capacitor C 11, the 12 capacitor C 12, the 13 capacitor C 13, the 18 capacitor C 18, the 20 capacitor C 20, the second inductance L 2; The model of second source converter U2 is LT1934, and the 5th diode D5 and the 11 diode D11 model can be selected MBR0540, and the 6th diode D6 model can be selected CMDSH-3; The 5th diode D5 anode connects the LP2 network, and negative electrode connects an end of the 12 resistance R 12, and the other end of the 12 resistance R 12 connects anodal and the 16 resistance R 16 1 ends of the 11 capacitor C 11; The other end of the 16 resistance R 16 connects the negative pole of the 11 capacitor C 11 and the positive pole of the 18 capacitor C 18, and the negative pole of the 18 capacitor C 18 connects DGND; The two ends of the 21 resistance R 21 connect the two ends of the 18 capacitor C 18 respectively; One end of the 18 resistance R 18 connects No. 5 pins of second source converter U2, and the other end connects No. 4 pins of second source converter U2; No. 5 pins of second source converter U2 connect the positive pole of the 11 capacitor C 11, No. 4 pins connect an end of the 20 capacitor C 20, the other end of the 20 capacitor C 20 connects DGND, No. 2 pins of second source converter U2 connect DGND, No. 3 pins connect an end of the 23 resistance R 23, and the other end of the 23 resistance R 23 connects DGND; No. 6 pins of second source converter U2 and No. 1 pin are connected the two ends of the tenth capacitor C 10 respectively; The negative electrode of the 11 diode D11 connects No. 6 pins of second source converter U2, and anode connects DGND; One end of the 13 capacitor C 13 connects No. 3 pins of second source converter U2, other end connection+3.3V network; One end of second inductance L 2 connects No. 6 pins of second source converter U2, other end connection+3.3V network; The 6th diode D6 negative electrode connects No. 1 pin of second source converter U2, anode connection+3.3V network; One end connection+3.3V network of the 15 resistance R 15, the other end connects No. 3 pins of second source converter U2; Positive pole connection+3.3V the network of the 12 capacitor C 12, negative pole connects DGND;

Described+5V power circuit network comprises the first supply convertor U1, the first diode D1, the second diode D2, first resistance R 1, second resistance R 2, the 7th resistance R 7, first capacitor C 1, second capacitor C 2, the 3rd capacitor C 3, the 4th capacitor C 4, the 7th capacitor C 7, the 22 capacitor C 22, the 23 capacitor C 23, the 24 capacitor C 24, the 25 capacitor C 25, the 26 capacitor C 26, the 27 capacitor C 27, the 28 capacitor C 28, the 29 capacitor C 29, the 30 capacitor C 30, the 31 capacitor C 31, the 32 capacitor C 32, the 33 capacitor C 33, the 34 capacitor C 34, first inductance L, 1, the first magnetic bead FB1, the second magnetic bead FB2; The model of the first voltage changer U1 is LT1934, and the first diode D1 model can be selected CMPD914; The 22 capacitor C 22, the 23 capacitor C 23, the 24 capacitor C 24, the 27 capacitor C 27, the 28 capacitor C 28,29 parallel connections of the 29 capacitor C, the end after the parallel connection connects the LP2 network, and the other end connects AGND; The first magnetic bead FB1 connects with the second magnetic bead FB2, and the end after the series connection connects the LP2 network, and the other end connects the LP3 network; The 25 capacitor C 25, the 26 capacitor C 26, the 30 capacitor C 30, the 31 capacitor C 31, the 32 capacitor C 32, the 33 capacitor C 33,34 parallel connections of the 34 capacitor C, end after the parallel connection connects the LP3 network, and the other end connects AGND; One end of first resistance R 1 connects the LP3 network, and the other end connects the positive pole of the 4th capacitor C 4, and the negative pole of the 4th capacitor C 4 connects AGND; One end of the 7th capacitor C 7 connects the positive pole of the 4th capacitor C 4, and the other end connects AGND; No. 5 pins of the first supply convertor U1 and No. 4 pins all are connected the positive pole of the 4th capacitor C 4, No. 2 pin connects AGND, No. 3 pins connect an end of the 7th resistance R 7, the other end of the 7th resistance R 7 connects AGND, and No. 6 pins of the first supply convertor U1 and No. 1 pin are connected the two ends of first capacitor C 1 respectively; The negative electrode of the second diode D2 connects No. 6 pins of the first supply convertor U1, and anode connects AGND; One end of the 3rd capacitor C 3 connects No. 3 pins of the first supply convertor U1, other end connection+5V network; One end of first inductance L 1 connects No. 6 pins of the first supply convertor U1, other end connection+5V network; The negative electrode of the first diode D1 connects No. 1 pin of the first supply convertor U1, anode connection+5V network; One end connection+5V network of second resistance R 2, the other end connects No. 3 pins of the first supply convertor U1; Positive pole connection+5V the network of second capacitor C 2, the other end connects AGND;

Described analog circuit power supply comprises the 35 capacitor C 35, the 36 capacitor C 36, the 37 capacitor C 37, the 38 capacitor C 38, the three supply convertor U3; The model of the 3rd supply convertor U3 is LM1117T-3.3; Positive pole connection+5V the network of the 35 capacitor C 35, negative pole connects AGND; The two ends of the 37 capacitor C 37 connect the two ends of the 35 capacitor C 35 respectively; No. 3 pin connection+5V networks of the 3rd supply convertor U3, No. 2 pin connects the VDDA network, and No. 1 pin connects AGND; The positive pole of the 36 capacitor C 36 connects the VDDA network, and negative pole connects AGND; The two ends of the 38 capacitor C 38 link to each other with the two ends of the 36 capacitor C 36 respectively;

Described ground treatment circuit comprises the 3rd magnetic bead FB3, and the 3rd magnetic bead FB3 one end connects AGND, and the other end connects GND and DGND;

Described MCU circuit comprises the 72 resistance R 72, the 73 resistance R 73, the 74 resistance R 74, the 78 resistance R 78, the 79 resistance R 79, the 81 resistance R 81, the 82 resistance R 82, the 86 resistance R 86, the 55 capacitor C 55, the 56 capacitor C 56, the 57 capacitor C 57, the 58 capacitor C 58, the 59 capacitor C 59, the 60 capacitor C 60, the 61 capacitor C 61, the 62 capacitor C 62, the 63 capacitor C 63, the 64 capacitor C 64, the 65 capacitor C 65, the 66 capacitor C 66, the 67 capacitor C 67, the 68 capacitor C 68, the 69 capacitor C 69, the 70 capacitor C 70, the 71 capacitor C 71, EEPROM device U8, the first crystal oscillator Y1, the second crystal oscillator Y2, reference voltage chip U10, the chip U12 that resets, MCU chip U9; The model of EEPROM device U8 is 24LC16; The model of reference voltage chip U10 is REF3133; The model of chip U12 of resetting is FM809; MCU chip U9 adopts 32 MCU, and model is STM32F107VC; No. 1 pin of EEPROM device U8, No. 2 pins, No. 3 pins, No. 4 pins all are connected to DGND, No. 8 pin connection+3.3V networks, No. 6 pins are connected to No. 92 pins of MCU chip U9, and No. 5 pins of EEPROM device U8 are connected to No. 93 pins of MCU chip U9; One end connection+3.3V network of the 72 resistance R 72, the other end connects No. 6 pins of EEPROM device U8; One end connection+3.3V network of the 73 resistance R 73, the other end connects No. 5 pins of EEPROM device U8; One end connection+3.3V network of the 55 capacitor C 55, the other end connects DGND; The end of the first crystal oscillator Y1 connects an end of the 56 capacitor C 56, and the other end of the first crystal oscillator Y1 connects an end of the 57 capacitor C 57; An end that does not link to each other with the first crystal oscillator Y1 of the 56 capacitor C 56 and the 57 capacitor C 57 all is connected DGND; One end of the 78 resistance R 78 connects No. 8 pins of MCU chip U9, one end of the 79 resistance R 79 connects No. 9 pins of MCU chip U9, and the 78 resistance R 78 and that end that does not link to each other with MCU chip U9 of the 79 resistance R 79 are connected the two ends of the first crystal oscillator Y1 respectively; The end of the second crystal oscillator Y2 connects an end of the 58 capacitor C 58, and the other end connects an end of the 60 capacitor C 60; An end that does not link to each other with the second crystal oscillator Y2 of the 58 capacitor C 58 and the 60 capacitor C 60 all is connected DGND; The second crystal oscillator Y2 is connected No. 12 pins of MCU chip U9 with the 58 capacitor C 58 continuous those ends, the other end connects an end of the 82 resistance R 82; The other end of the 82 resistance R 82 connects No. 13 pins of MCU chip U9; The two ends of the 81 resistance R 81 connect the two ends of the second crystal oscillator Y2 respectively; One end connection+5V network of the 61 capacitor C 61, the other end connects AGND; No. 1 pin connection+5V network of reference voltage chip U10, No. 3 pin connects AGND, and No. 2 pin connects the VREF+ network; The positive pole of the 62 capacitor C 62 connects the VREF+ network, and negative pole connects AGND; The two ends of the 63 capacitor C 63 connect the two ends of the 62 capacitor C 62 respectively; The reset No. 3 pin connection+3.3V networks of chip U12, No. 1 pin connects DGND, and No. 2 pins connect No. 14 pins of MCU chip U9 and an end of the 59 capacitor C 59; The other end of the 59 capacitor C 59 connects DGND; One end of the 74 resistance R 74 connects No. 94 pins of MCU chip U9, and the other end connects DGND; One end of the 86 resistance R 86 connects No. 37 pins of MCU chip U9, and the other end connects DGND; The 64 capacitor C 64, the 65 capacitor C 65, the 66 capacitor C 66, the 67 capacitor C 67, the 68 capacitor C 68, the 69 capacitor C 69, the 70 capacitor C 70,71 parallel connections of the 71 capacitor C, end connection+3.3V network after the parallel connection, the other end connects DGND; No. 6 pins of MCU chip U9, No. 11 pins, No. 28 pins, No. 50 pins, No. 75 pins, No. 100 pins all connect+the 3.3V network, No. 21 pin connects the VREF+ network, No. 22 pin connects the VDDA pin, No. 19 pin connects AGND, and No. 10 pins, No. 20 pins, No. 27 pins, No. 49 pins, No. 74 pins, No. 99 pins connect DGND;

Described data acquisition circuit comprises current acquisition circuit and voltage collection circuit; The current acquisition circuit has four, and it goes into LA network, LB network, LC network, LN network that end connects rectification circuit respectively, and output connects the respective pins of MCU chip U9 in the MCU circuit respectively; The input of voltage collection circuit connects corresponding connectors respectively, and output then connects the respective pins of MCU chip U9 in the MCU circuit;

Described current acquisition circuit comprises the 25 resistance R 25, the 26 resistance R 26, the 27 resistance R 27, the 28 resistance R 28, the 29 resistance R 29, the 30 resistance R 30, the 31 resistance R 31, the 32 resistance R 32, the 33 resistance R 33, the 34 resistance R 34, the 35 resistance R 35, the 36 resistance R 36, the 37 resistance R 37, the 38 resistance R 38, the 39 resistance R 39, the 40 resistance R 40, the 41 resistance R 41, the 42 resistance R 42, the 43 resistance R 43, the 44 resistance R 44, the 45 resistance R 45, the 46 resistance R 46, the 47 resistance R 47, the 48 resistance R 48, the 49 resistance R 49, the 50 resistance R 50, the 51 resistance R 51, the 39 capacitor C 39, the 40 capacitor C 40, the 41 capacitor C 41, the 42 capacitor C 42, the 43 capacitor C 43, the 44 capacitor C 44, the 45 capacitor C 45, the 46 capacitor C 46, the 47 capacitor C 47, the 48 capacitor C 48, the 49 capacitor C 49, the 50 capacitor C 50, the first operational amplifier U5, the second operational amplifier U6, gating chip U4; The model of the first operational amplifier U5 and the second operational amplifier U6 is LM224, and the model of gating chip U4 is MC74HC4053;

A phase acquisition circuit in the current acquisition circuit: the 29 resistance R 29 1 ends connect the LA network in the rectification circuit, the other end connects No. 6 pins of the second operational amplifier U6, and the two ends of the 30 resistance R 30 connect No. 6 pins and No. 7 pins of the second operational amplifier U6 respectively; One end of the 25 resistance R 25 connects No. 14 pins of gating chip, and the other end connects No. 7 pins of the second operational amplifier U6; No. 4 pin connection+5V networks of the second operational amplifier U6, No. 6 pins connect No. 12 pins of gating chip, No. 5 and No. 2 pins connection AGND of the second operational amplifier U6; The 37 resistance R 37 1 ends connect No. 7 pins of the second operational amplifier U6, and the other end connects an end of the 33 resistance R 33 and an end of the 43 capacitor C 43; The other end of the 33 resistance R 33 connects No. 5 pins of the first operational amplifier U5; The other end of the 43 capacitor C 43 connects No. 7 pins of the second operational amplifier U5; One end of the 39 capacitor C 39 connects No. 5 pins of the first operational amplifier U5, and the other end connects AGND; No. 4 pin connection+5V networks of the first operational amplifier U5, No. 6, No. 7 pin links together; One end of the 31 resistance R 31 connects No. 7 pins of the first operational amplifier U5, and the other end connects the AAD network; The 40 capacitor C 40 is in parallel with the 34 resistance R 34, and the end after the parallel connection connects AGND, and the other end connects the AAD network; AAD connects No. 29 pins of MCU chip U9 in the MCU circuit; The circuit of above-mentioned form has 3, except A phase current Acquisition Circuit, also comprises B phase current Acquisition Circuit, C phase current Acquisition Circuit; A phase current Acquisition Circuit connects the LA network, and corresponding with it, other two circuit connect LB network, LC network respectively; A phase current Acquisition Circuit connects No. 12 pins of gating chip U4, and corresponding with it, other two circuit connect No. 2 pins and No. 5 pins of gating chip U4 respectively; A phase current Acquisition Circuit connects No. 14 pins of gating chip U4, and corresponding with it, other two circuit connect No. 15 pins of gating chip U4, No. 4 pins respectively; No. 6 pins of gating chip U4, No. 9 pins, No. 10 pins, No. 11 pins connect No. 1 pin of MCU chip U9 in the MCU circuit, No. 98 pins, No. 97 pins, No. 96 pins respectively;

N phase acquisition circuit in the current acquisition circuit: an end of the 42 resistance R 42 connects the LN network in the rectification circuit, the other end connects No. 13 pins of the second operational amplifier U6, and the two ends of the 43 resistance R 43 connect No. 13 pins and No. 14 pins of the second operational amplifier U6 respectively; No. 4 pin connection+5V networks of the second operational amplifier U6, No. 12 pins and No. 11 pins connect AGND; One end of the 51 resistance R 51 connects No. 14 pins of the second operational amplifier U6, and the other end connects an end of the 48 resistance R 48 and an end of the 50 capacitor C 50; The other end of the 48 resistance R 48 connects No. 12 pins of the first operational amplifier U5; The other end of the 50 capacitor C 50 connects No. 14 pins of the first operational amplifier U5; One end of the 46 capacitor C 46 connects No. 12 pins of the first operational amplifier U5, and the other end connects AGND; No. 4 pin connection+5V networks of the first operational amplifier U5, No. 13, No. 14 pin links together; One end of the 45 resistance R 45 connects No. 14 pins of the first operational amplifier U5, and the other end connects the NAD network; The 48 capacitor C 48 is in parallel with the 49 resistance R 49, and the end after the parallel connection connects AGND, and the other end connects the NAD network; No. 32 pins of MCU chip U9 in the NAD network connection MCU circuit;

Described voltage collection circuit comprises the 6th connector J6, the 52 resistance R 52, the 53 resistance R 53, the 54 resistance R 54, the 55 resistance R 55, the 56 resistance R 56, the 57 resistance R 57, the 58 resistance R 58, the 59 resistance R 59, the 60 resistance R 60, the 61 resistance R 61, the 62 resistance R 62, the 63 resistance R 63, the 64 resistance R 64, the 65 resistance R 65, the 66 resistance R 66, the 67 resistance R 67, the 68 resistance R 68, the 69 resistance R 69, the 70 resistance R 70, the 71 resistance R 71, the 123 resistance R 123, the 124 resistance R 124, the 125 resistance R 125, the 127 resistance R 127, the 128 resistance R 128, the 129 resistance R 129, the 130 resistance R 130, the 131 resistance R 131, the 133 resistance R 133, the 134 resistance R 134, the 135 resistance R 135, the 136 resistance R 136, the 137 resistance R 137, the 138 resistance R 138, the 139 resistance R 139, the 141 resistance R 141, the 51 capacitor C 51, the 52 capacitor C 52, the 53 capacitor C 53, the 54 capacitor C 54, the 92 capacitor C 92, the 93 capacitor C 93, the 94 capacitor C 94, the 95 capacitor C 95, the 96 capacitor C 96, the 97 capacitor C 97, the 98 capacitor C 98, the 99 capacitor C 99, the three operational amplifier U7; The model of the 3rd operational amplifier U7 is LM224;

A phase voltage Acquisition Circuit in the voltage collection circuit: an end of the 52 resistance R 52 connects AGND, and the other end connects No. 2 pins of the 3rd operational amplifier U7; One end of the 53 resistance R 53 connects No. 2 pins of the 3rd operational amplifier U7, and the other end connects No. 1 pin of the 3rd operational amplifier U7; The 57 resistance R 57 is connected with the 58 resistance R 58, the end connection+5V network after the series connection, and the other end connects No. 3 pins of the 3rd operational amplifier U7; No. 3 pins of the 3rd operational amplifier U7 connect the MA network, No. 4 pin connection+5V networks, and No. 11 pin connects AGND, and No. 1 pin connects an end of the 56 resistance R 56; The other end of the 56 resistance R 56 connects No. 33 pins of MCU chip in an end of the 51 capacitor C 51 and the MCU circuit, and the other end of the 51 capacitor C 51 connects AGND; One end of the 92 capacitor C 92 connects the 6th connector J6, the other end connects an end of the 123 resistance R 123, the other end of the 123 resistance R 123 connects an end of the 124 resistance R 124, the other end of the 124 resistance R 124 connects an end of the 125 resistance R 125, and the other end of the 125 resistance R 125 connects the MA network; The 93 capacitor C 93 is in parallel with the 127 resistance R 127, and the end after the parallel connection connects the MA network, and the other end connects AGND; Circuit with above-mentioned annexation has 4, except A phase voltage Acquisition Circuit, also comprises B phase voltage Acquisition Circuit, C phase voltage Acquisition Circuit, N phase voltage Acquisition Circuit; Foregoing circuit connects No. 33 pins of MCU chip in the MCU circuit, and corresponding with it, its excess-three circuit connects No. 34 pins of MCU chip in the MCU circuit, No. 35 pins, No. 36 pins respectively;

The man-machine interface circuit comprises liquid crystal display circuit, led circuit, key circuit, coding switch circuit; They link to each other with the MCU circuit respectively;

Described liquid crystal display circuit comprises LCD U14, the 72 capacitor C 72, the 76 capacitor C 76, the 77 capacitor C 77, the 78 capacitor C 78, the 79 capacitor C 79, the 80 capacitor C 80, the 81 capacitor C 81, the 82 capacitor C 82; The model of LCD U14 is KMC12232-A-00-SGA; No. 1 pin of LCD U14, No. 2 pins, No. 3 pins, No. 4 pins, No. 5 pins connect No. 64 pins of MCU chip U9 in the MCU circuit respectively, No. 63 pins, No. 62 pins, No. 61 pins, No. 60 pins, No. 7 pins of LCD U14 connect DGND, No. 8 pins of LCD U14, No. 14 pins, No. 15 pins, No. 16 pins, No. 17 pins, No. 18 pin connects the 82 capacitor C 82 respectively, the 77 capacitor C 77, the 78 capacitor C 78, the 79 capacitor C 79, the 80 capacitor C 80, the 81 capacitor C 81 end separately, these electric capacity other end separately all connects DGND; No. 9 pins of LCD U14 link to each other with No. 8 pins; The two ends of the 76 capacitor C 76 connect No. 10 pins and No. 11 pins of LCD U14 respectively; The two ends of the 72 capacitor C 72 connect No. 12 pins and No. 13 pins of LCD U14 respectively;

Described key circuit has 5, and each key circuit comprises the 92 resistance R 92, the 93 resistance R 93, the 94 resistance R 94, the 95 resistance R 95, the 96 resistance R 96, the first button S1, the second button S2, the 3rd button S3, the 4th button S4, the 5th button S5; One end connection+3.3V network of the 92 resistance R 92, the other end connect No. 71 pins of MCU chip U9 in the MCU circuit and the end of the first button S1; The other end of the first button S1 connects DGND; One end connection+3.3V network of the 93 resistance R 93, the other end connect No. 70 pins of MCU chip U9 in the MCU circuit and the end of button S2; The other end of the second button S2 connects DGND; One end connection+3.3V network of the 94 resistance R 94, the other end connect No. 66 pins of MCU chip U9 in the MCU circuit and the end of the 3rd button S3; The other end of the 3rd button S3 connects DGND; One end connection+3.3V network of the 95 resistance R 95, the other end connect No. 65 pins of MCU chip U9 in the MCU circuit and the end of the 4th button S4; The other end of the 4th button S4 connects DGND; The 96 resistance R 96 1 end connection+3.3V networks, the other end connect No. 54 pins of MCU chip U9 in the MCU circuit and the end of the 5th button S5; The other end of the 5th button S5 connects DGND;

Described led circuit has 3, and each led circuit comprises the 91 resistance R 91, the 97 resistance R 97, the 102 resistance R 102, the 3rd light-emitting diode DS3, the 4th light-emitting diode DS4, the 5th light-emitting diode DS5; One end of the 91 resistance R 91 connects No. 44 pins of MCU chip U9 in the MCU circuit, and the other end connects the anode of the 3rd light-emitting diode DS3; The negative electrode of the 3rd light-emitting diode DS3 connects DGND; One end of the 97 resistance R 97 connects No. 45 pins of MCU chip U9 in the MCU circuit, and the other end connects the anode of the 4th light-emitting diode DS4; The negative electrode of the 4th Light-Emitting Diode DS4 connects DGND; One end of the 102 resistance R 102 connects No. 46 pins of MCU chip U9 in the MCU circuit, and the other end connects the anode of the 5th Light-Emitting Diode DS5; The negative electrode of the 5th Light-Emitting Diode DS5 connects DGND;

Described coding switch circuit has 2, and each coding switch circuit comprises the 87 resistance R 87, the 88 resistance R 88, the 89 resistance R 89, the 90 resistance R 90, the 98 resistance R 98, the 99 resistance R 99, the 100 resistance R 100, the 101 resistance R 101, the first code switch U11, the second code switch U13; The 87 resistance R 87, the 88 resistance R 88, the 89 resistance R 89, the 90 resistance R 90 one termination+3.3V network separately, the other end connect No. 2 pins of the first code switch U11, No. 3 pins, No. 4 pins, No. 5 pins respectively; No. 1 pin of the first code switch U11, No. 6 pins connect DGND, and No. 2 pins of the first code switch U11, No. 3 pins, No. 4 pins, No. 5 pins connect No. 88 pins of MCU chip U9 in the MCU circuit, No. 86 pins, No. 85 pins, No. 84 pins respectively; The 98 resistance R 98, the 99 resistance R 99, the 100 resistance R 100, the 101 resistance R 101 one termination+3.3V network separately, the other end connect No. 2 pins of the second code switch U13, No. 3 pins, No. 4 pins, No. 5 pins respectively; No. 1 pin of the second code switch U13, No. 6 pins connect DGND, and No. 2 pins of the second code switch U13, No. 3 pins, No. 4 pins, No. 5 pins connect No. 83 pins of MCU chip U9 in the MCU circuit, No. 82 pins, No. 81 pins, No. 80 pins respectively;

Communication module comprises ethernet interface circuit and RS485 interface circuit; Ethernet interface circuit links to each other with the MCU circuit by the MII interface; The RS485 interface circuit connects the MCU circuit;

Described ethernet interface circuit comprises the first exclusion RN1, the second exclusion RN2, the 3rd exclusion RN3, the 4th exclusion RN4, the 5th exclusion RN5, the 6th exclusion RN6, the 84 resistance R 84, the 111 resistance R 111, the 112 resistance R 112, the 119 resistance R 119, the 121 resistance R 121, the 116 resistance R 116, the 117 resistance R 117, the 113 resistance R 113, the 108 resistance R 108, the 110 resistance R 110, the 109 resistance R 109, the 73 capacitor C 73, the 74 capacitor C 74, the 75 capacitor C 75, the 83 capacitor C 83, the 84 capacitor C 84, the 85 capacitor C 85, the 86 capacitor C 86, the 87 capacitor C 87, the 88 capacitor C 88, the 89 capacitor C 89, the 90 capacitor C 90, the 3rd crystal oscillator Y3, Ethernet PHY controller U15, RJ45 interface CN3; The model of Ethernet PHY controller U15 is DP83848I; The model of RJ45 interface CN3 can be selected HR911105A; The 73 capacitor C 73, the 74 capacitor C 74,75 parallel connections of the 75 capacitor C, the end connection+3.3V network after the parallel connection, the other end connects DGND; One end of the 111 resistance R 111 connects No. 7 pins of Ethernet PHY controller U15, and the other end connects an end of the 84 resistance R 84; The other end of the 84 resistance R 84 connects No. 53 pins of MCU chip U9 in the MCU circuit; The 112 resistance R 112 1 end connection+3.3V networks, the other end connect No. 7 pins of Ethernet PHY controller U15; No. 1 pin of the 6th exclusion RN6, No. 2 pins, No. 3 pins, No. 4 pins connect No. 13 pins of Ethernet PHY controller U15, No. 14 pins, No. 16 pins, No. 17 pins respectively, No. 5 pins of the 6th exclusion RN6, No. 6 pins, No. 7 pins, No. 8 pin connection+3.3V networks; The 116 resistance R 116 and the 117 resistance R 117 1 end connection+3.3V networks, the other end connects No. 20 pins of Ethernet PHY controller U15, No. 21 pins respectively; The 85 capacitor C 85, the 86 capacitor C 86, the 87 capacitor C 87,88 parallel connections of the 88 capacitor C, end after the parallel connection connects DGND, the other end connects RFB network, No. 18 pins, No. 23 pins, No. 37 pins of RFB network connection Ethernet PHY controller U15; One end of the 113 resistance R 113 connects DGND, and the other end connects No. 24 pins of Ethernet PHY controller U15; No. 5 pins of the 5th exclusion RN5, No. 6 pins, No. 7 pins, No. 8 pins and+3.3V network connection, No. 1 pin of the 5th exclusion RN5, No. 2 pins, No. 3 pins connect No. 28 pins of Ethernet PHY controller U15, No. 27 pins, No. 26 pins respectively; One end connection+3.3V network of the 109 resistance R 109, the other end connect No. 30 pins of Ethernet PHY controller U15; The 110 resistance R 110 1 ends connect No. 25 pins of MCU circuit MCU chip U9, and the other end connects No. 30 pins of Ethernet PHY controller U15; The 83 capacitor C 83 is connected DGND respectively with an end of the 84 capacitor C 84, and the other end connects the two ends of the 3rd crystal oscillator Y3 respectively; The end of the 3rd crystal oscillator Y3 connects No. 34 pins of Ethernet PHY controller U15, and the other end connects an end of the 108 resistance R 108; The other end of the 108 resistance R 108 connects No. 33 pins of Ethernet PHY controller U15; No. 22 pins of Ethernet PHY controller U15, No. 32 pins, No. 48 pin connection+3.3V networks; No. 15 pins of Ethernet PHY controller U15, No. 19 pins, No. 35 pins, No. 36 pins, No. 47 pins connect DGND; No. 29 pins of Ethernet PHY controller U15 are connected to No. 14 pins of MCU circuit MCU chip U9; No. 1 pin of Ethernet PHY controller, No. 5 pins, No. 6 pins, No. 45 pins connect the end of the 3rd exclusion RN3 respectively, and the other end of the 3rd exclusion RN3 connects No. 18 pins of MCU circuit MCU chip U9, No. 17 pins, No. 95 pins, No. 58 pins successively respectively; No. 2 pins of Ethernet PHY controller, No. 3 pins, No. 4 pins connect the end of the 4th exclusion RN4 respectively, and the other end of the 4th exclusion RN4 connects No. 48 pins of MCU circuit MCU chip U9, No. 51 pins, No. 52 pins successively respectively; No. 40 pins of Ethernet PHY controller, No. 41 pins, No. 42 pins, No. 46 pins connect the end of the first exclusion RN1 respectively, and the other end of the first exclusion RN1 connects No. 23 pins of MCU chip U9 in the MCU circuit, No. 47 pins, No. 26 pins, No. 59 pins successively respectively; No. 38 pins of Ethernet PHY controller U15, No. 39 pins, No. 43 pins, No. 44 pins connect the end of the second exclusion RN2 respectively, and the other end of the second exclusion RN2 is connected to No. 24 pins of MCU chip U9 in the controller circuitry, No. 55 pins, No. 56 pins, No. 57 pins successively respectively; No. 1 pin of RJ45 interface CN3, No. 2 pins, No. 3 pins, No. 6 pins, No. 10 pins, No. 11 pins connect No. 17 pins of Ethernet PHY controller U15, No. 16 pins, No. 14 pins, No. 13 pins, No. 28 pins, No. 26 pins respectively; No. 9 pins of RJ45 interface CN3, No. 12 pins connect the 121 resistance R 121, the 119 resistance R 119 end separately respectively, and an other end of these two resistance all connects+the 3.3V network; No. 8 pins of RJ45 interface CN3 connect AGND; No. 4 pins of RJ45 interface CN3, No. 5 pin connection+3.3V networks;

Described RS485 interface circuit comprises transceiver U16, common mode inhibition device T1, the 114 resistance R 114, the 115 resistance R 115,118 resistance R 118, the 120 resistance R 120, the 122 resistance R 122, the 91 capacitor C 91, the five connector J5; Transceiver U16 model is SP3485; The model of common mode inhibition device T1 is B82789C0513; One end connection+3.3V network of the 114 resistance R 114, the other end connects No. 6 pins of transceiver U16; The two ends of the 118 resistance R 118 connect No. 6 pins of transceiver U16, No. 7 pins respectively; One end of the 122 resistance R 122 connects DGND, and the other end connects No. 7 pins of transceiver U16; The two ends of the 91 capacitor C 91 connect DGND and+3.3V network respectively; No. 1 pin of transceiver U16, No. 2 pins, No. 3 pins, No. 4 pins connect No. 79 pins of MCU chip U9 in the MCU circuit, No. 43 pins, No. 43 pins, No. 78 pins respectively; No. 8 pins of transceiver U16, No. 5 pins connect respectively+3.3V network and DGND; No. 6 pins of transceiver U16 connect an end of resistance R 115, and the other end of the 115 resistance R 115 connects No. 3 pins of common mode inhibition device T1; No. 7 pins of transceiver U16 connect an end of the 120 resistance R 120, the other end of the 120 resistance R 120 connects No. 1 pin of common mode inhibition device T1; No. 2 pins of common mode inhibition device T1, No. 4 pins link to each other with the 5th connector J5 respectively;

Remote control module comprises executive circuit, state output circuit and feedback circuit; Executive circuit, state output circuit, feedback circuit are connected to the MCU circuit respectively;

Described executive circuit has 2, each executive circuit comprises the 75 resistance R 75, the 76 resistance R 76, the 77 resistance R 77, the 80 resistance R 80, the 83 resistance R 83, the 85 resistance R 85, the 126 resistance R 126, the 132 resistance R 132, the 4th optocoupler isolator U20, the 6th optocoupler isolator U22, the first light-emitting diode DS1, the second light-emitting diode DS2, the 15 diode D15, the 16 diode D16, first relay K 1, second relay K 2, the 8th connector J8, the tenth connector CN1, the tenth a connector CN2, the first triode Q4, the second triode Q5; The model of the 4th photoelectrical coupler U20, the 6th photoelectrical coupler U22 is TLP-181; In the executive circuit: No. 1 pin of the 4th optocoupler isolator U20 connects an end of the 126 resistance R 126, the other end connection+3.3V network of the 126 resistance R 126; No. 3 pins of the 4th optocoupler isolator U20 are connected to No. 39 pins that connect MCU chip U9 in the MCU circuit, No. 4 pin connection-24V networks of the 4th optocoupler isolator U20; No. 6 pins of the 4th optocoupler isolator U20 connect an end of the 77 resistance R 77, and the other end of the 77 resistance R 77 connects the base stage of the first triode Q4; One end connection+24V network of the 76 resistance R 76, the other end connects the base stage of the first triode Q4; The emitter of the first triode Q4 connects the negative electrode of the first light-emitting diode DS1, the collector electrode connection-24V network of the first triode Q4; The anode of the first light-emitting diode DS1 connects an end of the 75 resistance R 75; Other end connection+24V the network of the 75 resistance R 75; The 15 diode D15 is in parallel with the input of first relay K 1, and the negative electrode connection+24V network of the 15 diode D15, the anode of the 15 diode D15 connect the first triode Q4 emitter; The output of first relay K 1 links to each other with the tenth connector CN1; Another one in the executive circuit is identical with foregoing circuit; The 4th optocoupler isolator U20 No. 3 pins are connected to No. 39 pins that connect MCU chip U9 in the MCU circuit in the foregoing circuit, and corresponding with it, the respective pins of another one executive circuit is connected to No. 38 pins of MCU chip U9 in the MCU circuit;

Described state output circuit and state-feedback circuit comprise the 13 resistance R 13, the 17 resistance R 17, the 22 R22, the 140 resistance R 140, the 142 resistance R 142, the first optocoupler isolator U17, the second optocoupler isolator U18, the 3rd optocoupler isolator U19, the 4th optocoupler isolator U21, the 7th connector J7, the 9th connector J9; The model of the first optocoupler isolator U17, the second optocoupler isolator U18, the 3rd optocoupler isolator U19, the 4th optocoupler isolator U21 is TLP-181; The state output circuit has 3, in each state output circuit: an end connection+3.3V network of the 13 resistance R 13, the other end connects No. 1 pin of the first optocoupler isolator U17, No. 3 pins of the first optocoupler isolator U17 connect No. 40 pins of MCU chip U9 in the MCU circuit, No. 4 pin connection-24V networks of the first optocoupler isolator U17, No. 6 pins of the first optocoupler isolator U17 link to each other with connector J9; The circuit of above-mentioned annexation has 3; The first optocoupler isolator U17 No. 3 pins are connected to No. 40 pins of MCU chip U9 in the MCU circuit in the foregoing circuit, corresponding with it, the respective pins of two other state output circuit is connected to No. 41 pins of MCU chip U9 in the MCU circuit, No. 42 pins respectively; In four pins of the 9th connector J9, wherein three link to each other another one connection-24V network respectively with three state output circuits; State-feedback circuit: No. 1 pin of the 5th optocoupler isolator U21 connects an end of the 140 resistance R 140, the other end of the 140 resistance R 140 links to each other with the pin of the 7th connector J7, another pin of the 7th connector J7 connects No. 3 pins of the 5th optocoupler isolator U21, No. 6 pins of the 5th optocoupler isolator U21 are connected to an end of the 142 resistance R 142, other end connection+3.3V the network of the 142 resistance R 142, No. 6 pins of the 5th photoelectrical coupler U21 connect No. 87 pins of MCU chip U9 in the MCU circuit, and No. 4 pins of the 5th photoelectrical coupler U21 photoelectrical coupler connect DGND;

In the above-mentioned circuit for remotely controlling ,-24V network ,+the 24V network connects No. 1 pin and No. 2 pins of connector J8 respectively;

Described emulation interface circuit comprises the 103 resistance R 103, the 104 resistance R 104, the 105 resistance R 105, the 106 resistance R 106, the 107 resistance R 107, the 12 connector JP1; One end connection+3.3V networking of the 103 resistance R 103, the other end links to each other with No. 1 pin of the 12 connector JP1, one end connection+3.3V networking of the 104 resistance R 104, the other end links to each other with No. 3 pins of the 12 connector JP1, one end connection+3.3V networking of the 105 resistance R 105, the other end links to each other with No. 4 pins of the 12 connector JP1, one end connection+3.3V networking of the 106 resistance R 106, the other end links to each other with No. 5 pins of the 12 connector JP1, one end of the 107 resistance R 107 connects DGND, and the other end links to each other with No. 2 pins of the 12 connector JP1; No. 1 pin of the 12 connector JP1, No. 2 pins, No. 3 pins, No. 4 pins, No. 5 pins, No. 6 pins connect No. 89 pins of MCU chip U9 in the MCU circuit, No. 76 pins, No. 72 pins, No. 77 pins, No. 90 pins, No. 14 pins respectively; No. 7 pin connection+3.3V networks of the 12 connector JP1, No. 8 pins of the 12 connector JP1 connect DGND.