CN103259543A - Deep space communication quasi-cyclic LDPC code generator polynomial parallel generating device - Google Patents
Deep space communication quasi-cyclic LDPC code generator polynomial parallel generating device Download PDFInfo
- Publication number
- CN103259543A CN103259543A CN2013101322582A CN201310132258A CN103259543A CN 103259543 A CN103259543 A CN 103259543A CN 2013101322582 A CN2013101322582 A CN 2013101322582A CN 201310132258 A CN201310132258 A CN 201310132258A CN 103259543 A CN103259543 A CN 103259543A
- Authority
- CN
- China
- Prior art keywords
- generator polynomial
- generator
- address
- quasi
- equals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Error Detection And Correction (AREA)
Abstract
The invention provides a deep space communication quasi-cyclic LDPC code generator polynomial parallel generating device which is composed of a generator polynomial lookup table, an address generator and a data shifter. The address generator generates an original address beta and side-play mount delta, and further generates a reading address, beta + delta, of the generator polynomial lookup table. The generator polynomial lookup table outputs corresponding 2048 bit data according to the reading address. The data shifter shifts output by the generator polynomial lookup table according to code types so as to enable high-order position bits of the 2048 bit data output by the data shifter to be generator polynomials corresponding to the code types. The generating method is simple in process, easy to achieve, free of multiplication, and low in resource consumption. The deep space communication quasi-cyclic LDPC code generator polynomial parallel generating device is especially applied to application occasions where bit widths of quasi-cyclic LDPC code generator polynomials are not the same in length, can effectively reduce requirements for memorizers, and has the remarkable advantage of being low in cost.
Description
Technical field
The present invention relates to the deep space data communication field, particularly the parallel generation device of quasi-cyclic LDPC code generator polynomial in a kind of CCSDS deep space communication system.
Background technology
Low-density checksum (Low-Density Parity-Check, LDPC) sign indicating number is one of channel coding technology efficiently, and quasi-cyclic LDPC (Quasic-LDPC, QC-LDPC) sign indicating number is a kind of special LDPC sign indicating number.
For the generator matrix G of QC-LDPC sign indicating number, the left-half corresponding informance vector of G is a unit matrix; The corresponding verification vector of the right half part of G is by a * c b * b rank circular matrix G
I, j(0≤i＜a, the array that a≤j＜t) constitutes, wherein, c=t-a.The first trip of circular matrix is its generator polynomial, and it has characterized the whole circulation matrix fully.Hence one can see that, and whole G is characterized by the generator polynomial of all circular matrixes.
The general-purpose coding method of QC-LDPC sign indicating number is to utilize generator matrix G to encode, and use the generator polynomial of all circular matrixes.The parallel conventional method that produces them is: in advance the generator polynomial of all circular matrixes is stored in the look-up table, and the address that each generator polynomial is corresponding different, look-up table is exported corresponding generator polynomial according to reading the address.
CCSDS deep space communication system recommendation 9 types QC-LDPC sign indicating number, Fig. 1 has provided the various parameters of different sign indicating number class π correspondences, wherein, d=a * c.As shown in Figure 1, square formation exponent number b is divided into 32,64,128,256,512,1024 and 2,048 seven kinds, this means that the bit wide of generator polynomial does not wait.The parallel existing solution that produces generator polynomial is above-mentioned conventional method, and Fig. 2 is the formation schematic diagram of its look-up table.Fig. 2 mechanically is stored in all generator polynomials of all yards class in the look-up table, and its degree of depth is 2016, bit wide is 2048 bits, and total memory capacity is 4,128,768 bits.In Fig. 2, hatched example areas has identified the space of waste, and all the other zones are divided into 9 data subspaces, and the degree of depth of each data subspace is that d, bit wide are the b bits.Therefore, the valid data among Fig. 2 only are d
0* b
0+ d
1* b
1+ d
2* b
2+ d
3* b
3+ d
4* b
4+ d
5* b
5+ d
6* b
6+ d
7* b
7+ d
8* b
8=96 * 2048+96 * 512+96 * 128+192 * 1024+192 * 256+192 * 64+384 * 512+384 * 128+384 * 32=774,144 bits utilize the space only to account for the 774144/4128768=19% of total capacity.As seen, because the bit wide of generator polynomial does not wait, the parallel existing solution that produces generator polynomial can cause the significant wastage of memory space, has increased equipment cost.
Summary of the invention
At the big shortcoming of memory space in the existing implementation of quick generation CCSDS deep space communication system not isometric QC-LDPC sign indicating number generator polynomial, the invention provides a kind of parallel production method efficiently, effectively reduce the demand to memory.
As shown in Figure 3, the parallel generation device of not isometric QC-LDPC sign indicating number generator polynomial mainly is made up of 3 parts in the CCSDS deep space communication system: generator polynomial look-up table, address generator and data shift unit.Whole production process divided for 3 steps finished: the 1st step, address generator produces initial address β according to sign indicating number class π, and producing offset delta=(j-a) * a+i according to piece row i, piece row j and piece line number a, initial address β and offset delta sum β+δ are the address of reading of generator polynomial look-up table; In the 2nd step, the generator polynomial look-up table is exported corresponding 2048 Bit datas according to reading the address; In the 3rd step, the data shift unit is shifted according to the output of the generator polynomial look-up table of sign indicating number class π, the generator polynomial that the high b bit of 2048 Bit datas of data shift unit output is the correspondence code class.Above-mentioned production process is simple, is easy to realize, need not multiplying, resource consumption is few.
The parallel generation device of QC-LDPC sign indicating number generator polynomial provided by the invention is particularly suitable for the not isometric application scenario of bit wide, can effectively reduce storage requirement, has the low obvious advantage of cost.
Can be further understood by following detailed description and accompanying drawings about advantage of the present invention and method.
Description of drawings
Fig. 1 has gathered the various parameters of 9 kinds of QC-LDPC sign indicating number generator matrixes in the CCSDS deep space communication system;
Fig. 2 is the formation schematic diagram of generator polynomial look-up table in the prior art;
Fig. 3 is the functional block diagram of the parallel generation device of QC-LDPC sign indicating number generator polynomial in the CCSDS deep space communication system;
Fig. 4 is the formation schematic diagram of generator polynomial look-up table among the present invention;
Fig. 5 is the look-up table initial address of 9 kinds of QC-LDPC sign indicating number correspondences in the CCSDS deep space communication system and the data shift unit figure place that moves to left.
Embodiment
Below in conjunction with accompanying drawing preferred embodiment of the present invention is elaborated, thereby so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that protection scope of the present invention is made more explicit defining.
The QC-LDPC sign indicating number is the special LDPC sign indicating number of a class, and its generator matrix G and check matrix H all are the arrays that is made of circular matrix, has the characteristics of segmentation circulation, so be called as quasi-cyclic LDPC code.The first trip of circular matrix is the result of one of footline ring shift right, and all the other each provisional capitals are results of one of its lastrow ring shift right, and therefore, circular matrix is characterized by its first trip fully.Usually, the first trip of circular matrix is called as its generator polynomial.
For the QC-LDPC sign indicating number of CCSDS deep space communication system, the left-half corresponding informance vector of generator matrix G is a unit matrix; The corresponding verification vector of the right half part of G is by a * c b * b rank circular matrix G
I, j(0≤i＜a, a≤j＜t, c=t-a) array of Gou Chenging:
Capable and the b of the continuous b of G row are called as the capable and piece row of piece respectively.Make g
I, j(0≤i＜a, a≤j＜t) is circular matrix G
I, jGenerator polynomial.
CCSDS deep space communication system recommendation 9 types QC-LDPC sign indicating number, what the preceding a piece row of generator matrix G were corresponding is information vector, back c piece row correspondence be the verification vector.Fig. 1 has provided the various parameters of different sign indicating number class π correspondences, wherein, and d=a * c.In Fig. 1, square formation exponent number b has seven kinds: 32,64,128,256,512,1024 and 2048, this means that the bit wide of generator polynomial does not wait.
The general-purpose coding method of QC-LDPC sign indicating number is to utilize generator matrix G to encode, and use the generator polynomial of all circular matrixes.Fig. 3 has provided the parallel generation device that is applicable to all QC-LDPC sign indicating number generator polynomials in the CCSDS deep space communication system, and it mainly is made up of generator polynomial look-up table, address generator and three kinds of functional modules of data shift unit.
The generator polynomial of all QC-LDPC sign indicating numbers of generator polynomial look-up table efficient storage.Fig. 4 is the memory space schematic diagram of generator polynomial look-up table, and its degree of depth is 480, bit wide is 2048 bits, and total memory capacity is 983,040 bit, the address is incremented to 479 one by one by 0 from top to bottom, and the high order bit of each data cell is on a left side, and low-order bit is on the right side.Fig. 4 has provided the data subspace that dissimilar QC-LDPC sign indicating numbers take, and hatched example areas has then identified the space of waste.In each data subspace, store earlier a generator polynomial of generator matrix G a piece row from top to bottom, store a generator polynomial of G a+1 piece row more from top to bottom, by that analogy, until a the generator polynomial of storing G t-1 piece row from top to bottom.The degree of depth of each data subspace is that d, bit wide are the b bits, and therefore, the valid data among Fig. 4 are d
0* b
0+ d
1* b
1+ d
2* b
2+ d
3* b
3+ d
4* b
4+ d
5* b
5+ d
6* b
6+ d
7* b
7+ d
8* b
8=96 * 2048+96 * 512+96 * 128+192 * 1024+192 * 256+192 * 64+384 * 512+384 * 128+384 * 32=774,144 bits, the utilance of data space is up to 774144/983040=79%.Yet prior art need take the memory space of 4,128,768 bits, and utilance only is 19%.Memory required for the present invention only is the 983040/4128768=24% of prior art, can save the memory of 3,145,728 bits, has improved utilance widely.
Address generator produces the address when reading the generator polynomial look-up table.Address generator produces initial address β according to sign indicating number class π, and produces offset delta according to piece row i, piece row j and piece line number a, and initial address β and offset delta sum β+δ are the address of reading of generator polynomial look-up table.By the degree of depth of each storage subspace among Fig. 4 as can be known, when π=0,1,2,3,4,5,6,7 and 8 the time, initial address is respectively β=0,96,192,288,288,288,96,96 and 96, as shown in Figure 5.Offset delta depends on the memory mechanism of data subspace, and closely related with piece row i, piece row j and piece line number a, satisfies δ=(j-a) * a+i between them, wherein, and 0≤i＜a, a≤j＜t.Known by Fig. 1, a have only 8,16 and 32 3 kind may, they all are 2 power.Therefore, in the calculating formula δ of side-play amount=(j-a) * a+i, as a=8,16 and 32 the time, multiplying can be respectively finished by 3,4 and 5 bits that move to left of the operation result to j-a.Therefore, in engineering practice, calculate δ and do not relate to multiplying in essence.
The data shift unit is shifted according to the output of the generator polynomial look-up table of sign indicating number class π, the generator polynomial that the high b bit that makes the output data is the correspondence code class.As shown in Figure 5, when π=0,1,2 and 3 the time, the data shift unit need not input is shifted; When π=4, the data shift unit is to the input b that moves to left
3=1024 bits; When π=5, the data shift unit is to the input b that moves to left
3+ b
4=1280 bits; When π=6, the data shift unit is to the input b that moves to left
3+ b
4+ b
5=1344 bits; When π=7, the data shift unit is to the input b that moves to left
3+ b
4+ b
5+ b
6=1856 bits; When π=8, the data shift unit is to the input b that moves to left
3+ b
4+ b
5+ b
6+ b
7=1984 bits.
The invention provides the parallel production method of all QC-LDPC sign indicating number generator polynomials in a kind of CCSDS deep space communication system, it produces step and is described below:
The 1st step, address generator produces initial address β according to sign indicating number class π, when π=0,1,2,3,4,5,6,7 and 8 the time, initial address is respectively β=0,96,192,288,288,288,96,96 and 96, and producing offset delta=(j-a) * a+i according to piece row i, piece row j and piece line number a, initial address β and offset delta sum β+δ are the address of reading of generator polynomial look-up table;
In the 2nd step, the generator polynomial look-up table is exported corresponding 2048 Bit datas according to reading the address;
The 3rd step, the data shift unit is shifted according to the output of the generator polynomial look-up table of sign indicating number class π, when π=0,1,2,3,4,5,6,7 and 8 the time, the data shift unit is respectively to 2048 Bit datas, 0,0,0,0,1024,1280,1344,1856 and 1984 bits that move to left of input, the generator polynomial that the high b bit of 2048 Bit datas of data shift unit output is the correspondence code class.
Above-mentioned production process need not multiplying in essence, is easy to realize, and supports to read at random.The most important thing is that compared with prior art, the present invention can save a large amount of memories, greatly reduces equipment cost.
The above; it only is one of the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; any those of ordinary skill in the art are in the disclosed technical scope of the present invention; variation or the replacement that can expect without creative work all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range that claims were limited.
Claims (6)
1. the parallel generation device of quasi-cyclic LDPC code generator polynomial in the deep space communication, the generator matrix G of quasi-cyclic LDPC code is divided into the capable and t piece row of a piece, and the part generator matrix G of back c piece row correspondence is by a * c b * b rank circular matrix G
I, jThe array that constitutes, wherein, d=a * c, t=a+c, a, b, c, d, i, j and t are nonnegative integer, 0≤i＜a, a≤j＜t is in 9 types of quasi-cyclic LDPC codes of CCSDS deep space communication system recommendation, the c perseverance is 12, π equals 0 when the sign indicating number class, 1,2,3,4,5,6,7 and 8 o'clock, a equals 8 respectively, 8,8,16,16,16,32,32 and 32, t equal 20 respectively, 20,20,28,28,28,44,44 and 44, d equals 96 respectively, 96,96,192,192,192,384,384 and 384, b equals 2048 respectively, 512,128,1024,256,64,512,128 and 32, it is characterized in that described generation device comprises with lower member:
The generator polynomial look-up table is for the generator polynomial of all quasi-cyclic LDPC codes of efficient storage;
Address generator, the address when reading the generator polynomial look-up table;
The data shift unit is used for the output of generator polynomial look-up table is shifted the generator polynomial that the high b bit that makes the output data is the correspondence code class.
2. the parallel generation device of quasi-cyclic LDPC code generator polynomial in a kind of deep space communication according to claim 1, it is characterized in that, the degree of depth of described generator polynomial look-up table is 480, the address is incremented to 479 successively by 0 from top to bottom, bit wide is 2048 bits, high order bit is on a left side, low-order bit is on the right side, in this data space, the degree of depth of the data subspace that every kind of sign indicating number class generator polynomial takies is d, bit wide is the b bit, in each data subspace, store earlier a generator polynomial of generator matrix G a piece row from top to bottom, store a generator polynomial of G a+1 piece row more from top to bottom, by that analogy, until a the generator polynomial of storing G t-1 piece row from top to bottom.
3. the parallel generation device of quasi-cyclic LDPC code generator polynomial in a kind of deep space communication according to claim 1, it is characterized in that, described address generator produces initial address β according to sign indicating number class π, when π equals 0,1,2,3,4,5,6,7 and 8, initial address β is respectively 0,96,192,288,288,288,96,96 and 96, and producing offset delta=(j-a) * a+i according to piece row i, piece row j and piece line number a, β+δ is the address of reading of generator polynomial look-up table.
4. the parallel generation device of quasi-cyclic LDPC code generator polynomial in a kind of deep space communication according to claim 1, it is characterized in that, described address generator is in the process of calculating offset delta=(j-a) * a+i, when a equals 8,16 and 32, multiplying is finished by 3,4 and 5 bits that move to left of the operation result to j-a respectively, therefore, calculate δ and do not relate to multiplying in essence.
5. the parallel generation device of quasi-cyclic LDPC code generator polynomial in a kind of deep space communication according to claim 1, it is characterized in that, described data shift unit is shifted according to the output of the generator polynomial look-up table of sign indicating number class π, when π equals 0,1,2,3,4,5,6,7 and 8, the data shift unit is respectively to 2048 Bit datas, 0,0,0,0,1024,1280,1344,1856 and 1984 bits that move to left of input, the generator polynomial that the high b bit of 2048 Bit datas of data shift unit output is the correspondence code class.
6. the parallel production method of quasi-cyclic LDPC code generator polynomial in the deep space communication, the generator matrix G of quasi-cyclic LDPC code is divided into the capable and t piece row of a piece, and the part generator matrix G of back c piece row correspondence is by a * c b * b rank circular matrix G
I, jThe array that constitutes, wherein, d=a * c, t=a+c, a, b, c, d, i, j and t are nonnegative integer, 0≤i＜a, a≤j＜t is in 9 types of quasi-cyclic LDPC codes of CCSDS deep space communication system recommendation, the c perseverance is 12, π equals 0 when the sign indicating number class, 1,2,3,4,5,6,7 and 8 o'clock, a equals 8 respectively, 8,8,16,16,16,32,32 and 32, t equal 20 respectively, 20,20,28,28,28,44,44 and 44, d equals 96 respectively, 96,96,192,192,192,384,384 and 384, b equals 2048 respectively, 512,128,1024,256,64,512,128 and 32, it is characterized in that described production method may further comprise the steps:
The 1st step, address generator produces initial address β according to sign indicating number class π, when π equals 0,1,2,3,4,5,6,7 and 8, initial address β is respectively 0,96,192,288,288,288,96,96 and 96, and producing offset delta=(j-a) * a+i according to piece row i, piece row j and piece line number a, initial address β and offset delta sum β+δ are the address of reading of generator polynomial look-up table;
In the 2nd step, the generator polynomial look-up table is exported corresponding 2048 Bit datas according to reading the address;
The 3rd step, the data shift unit is shifted according to the output of the generator polynomial look-up table of sign indicating number class π, when π equals 0,1,2,3,4,5,6,7 and 8, the data shift unit is respectively to 2048 Bit datas, 0,0,0,0,1024,1280,1344,1856 and 1984 bits that move to left of input, the generator polynomial that the high b bit of 2048 Bit datas of data shift unit output is the correspondence code class.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013101322582A CN103259543A (en) | 2013-04-16 | 2013-04-16 | Deep space communication quasi-cyclic LDPC code generator polynomial parallel generating device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013101322582A CN103259543A (en) | 2013-04-16 | 2013-04-16 | Deep space communication quasi-cyclic LDPC code generator polynomial parallel generating device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103259543A true CN103259543A (en) | 2013-08-21 |
Family
ID=48963279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013101322582A Pending CN103259543A (en) | 2013-04-16 | 2013-04-16 | Deep space communication quasi-cyclic LDPC code generator polynomial parallel generating device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103259543A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8219868B1 (en) * | 2007-11-30 | 2012-07-10 | Marvell International Ltd. | Quasi-cyclic low-density parity-check (QC-LDPC) encoder |
| CN102684707A (en) * | 2012-05-21 | 2012-09-19 | 电子科技大学 | LDPC (Low Density Parity Check) encoder |
| CN102857324A (en) * | 2012-09-27 | 2013-01-02 | 苏州威士达信息科技有限公司 | Low density parity check (LDPC) serial coder in deep space communication and based on lookup table and coding method |
| WO2013019560A2 (en) * | 2011-07-29 | 2013-02-07 | Sandisk Technologies Inc. | Checksum using sums of permutation sub-matrices |
| CN102932004A (en) * | 2012-11-08 | 2013-02-13 | 苏州威士达信息科技有限公司 | Generating method of quality control (QC)-low density parity check (LDPC) check matrix based on longitudinal diagonal storage |
| CN103023515A (en) * | 2013-01-01 | 2013-04-03 | 苏州威士达信息科技有限公司 | Block column circulation based LDPC (low-density parity-check) encoder and block column circulation based LDPC encoding method in CMMB (China mobile multimedia broadcasting) |
-
2013
- 2013-04-16 CN CN2013101322582A patent/CN103259543A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8219868B1 (en) * | 2007-11-30 | 2012-07-10 | Marvell International Ltd. | Quasi-cyclic low-density parity-check (QC-LDPC) encoder |
| WO2013019560A2 (en) * | 2011-07-29 | 2013-02-07 | Sandisk Technologies Inc. | Checksum using sums of permutation sub-matrices |
| CN102684707A (en) * | 2012-05-21 | 2012-09-19 | 电子科技大学 | LDPC (Low Density Parity Check) encoder |
| CN102857324A (en) * | 2012-09-27 | 2013-01-02 | 苏州威士达信息科技有限公司 | Low density parity check (LDPC) serial coder in deep space communication and based on lookup table and coding method |
| CN102932004A (en) * | 2012-11-08 | 2013-02-13 | 苏州威士达信息科技有限公司 | Generating method of quality control (QC)-low density parity check (LDPC) check matrix based on longitudinal diagonal storage |
| CN103023515A (en) * | 2013-01-01 | 2013-04-03 | 苏州威士达信息科技有限公司 | Block column circulation based LDPC (low-density parity-check) encoder and block column circulation based LDPC encoding method in CMMB (China mobile multimedia broadcasting) |
Non-Patent Citations (2)
| Title |
|---|
| HUXING ZHANG 等: "Multi-rate QC-LDPC Encoder", 《IEEE CIRCUITS AND SYSTEMS INTERNATIONAL CONFERENCE ON TESTING AND DIAGNOSIS,2009.ICTD 2009》 * |
| 王博 等: "多码率并行LDPC编码器的设计与实现", 《杭州电子科技大学学报》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8627172B2 (en) | Error correction encoding apparatus, decoding apparatus, encoding method, decoding method, and programs thereof | |
| CN102857324B (en) | Low density parity check (LDPC) serial coder in deep space communication and based on lookup table and coding method | |
| CN103236850A (en) | Rotate left-based quasi-cyclic (QC) matrix serial multiplier in deep space communication | |
| CN101800627B (en) | Hardware implementation of multiple-code-rate-compatible high-speed low-density parity-check code encoder | |
| CN103259544A (en) | Quasi-cyclic LDPC serial encoder in DTMB of shared storage mechanism | |
| CN102868495B (en) | Lookup table based LDPC (low-density parity-check) serial encoder and encoding method in near-earth communication | |
| CN103259543A (en) | Deep space communication quasi-cyclic LDPC code generator polynomial parallel generating device | |
| CN113055027B (en) | Variable bit width LDPC encoding method, encoder, SSD and storage medium | |
| CN103269228B (en) | Share quasi-cyclic LDPC serial encoder in the CMMB of memory mechanism | |
| CN103269227A (en) | Quasi-cyclic LDPC serial coder based on cyclic left shift and in deep space communication | |
| CN107959502B (en) | LDPC coding method | |
| CN103268214A (en) | Quasi-cyclic matrix high-speed multiplier in deep space communication based on lookup table | |
| CN103236858A (en) | Rotate left-based quasi-cyclic low density parity check (LDPC) serial encoder in China mobile multimedia broadcasting (CMMB) | |
| CN102857237B (en) | Low-delay LDPC (low-density parity-check) parallel encoder and encoding method in terrestrial communication system | |
| CN103269226B (en) | Share quasi-cyclic LDPC serial encoder in the near-earth communication of memory mechanism | |
| CN107959500B (en) | Construction method of LDPC encoder | |
| CN107959501B (en) | LDPC encoder | |
| CN117040543B (en) | Error correction coding check matrix generation method, device and storage medium | |
| CN103236849B (en) | Based on quasi cyclic matrix serial multiplier in the DTMB of shared memory mechanism | |
| CN103269225B (en) | Share quasi-cyclic LDPC serial encoder in the deep space communication of memory mechanism | |
| CN108540138B (en) | CSRAA coding circuit and encoder | |
| CN103916135A (en) | Ring shift left QC-LDPC coder with fully parallel input in ground proximity communication | |
| CN103929196A (en) | Full parallel input QC-LDPC encoder based on ring shift left in WPAN | |
| CN103701473A (en) | Decoding method for LDPCs (low density parity check code) | |
| CN103929205A (en) | Full-parallel-input cyclic-left-shift QC-LDPC encoder in deep space communication |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130821 |