CN103248223B - Clock circuit and boost-voltage regulator - Google Patents
Clock circuit and boost-voltage regulator Download PDFInfo
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- CN103248223B CN103248223B CN201310157122.7A CN201310157122A CN103248223B CN 103248223 B CN103248223 B CN 103248223B CN 201310157122 A CN201310157122 A CN 201310157122A CN 103248223 B CN103248223 B CN 103248223B
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Abstract
The present invention proposes a kind of clock circuit and boost-voltage regulator, and clock circuit includes the first clock voltage conversion module, for response when clock input signal is that high level exports the first clock output signal that size is clock input signal twice；First phase inverter, input and the first clock voltage conversion module of the first phase inverter are connected, for by anti-phase for clock input signal output；And second clock voltage transformation module, second clock voltage transformation module is connected with the output of the first phase inverter, for response when clock input signal is that low level exports the second clock output signal that size is clock input signal twice, thus produce anti-phase two clock signal that size is clock input signal twice, when clock circuit can solve the problem of leakage current present in boost pressure controller for boost pressure controller, and solve the problem that boost pressure controller operating efficiency is not high under existing clock circuit effect.
Description
Technical field
The invention belongs to charge pumping technique field, particularly relate to a kind of clock circuit and boost-voltage regulator.
Background technology
Boost pressure controller (Boost regulator) is a kind of circuit, defeated more than the high direct current of input voltage for producing
Go out voltage.As shown in Fig. 1 circuit diagram, a kind of boost pressure controller is mainly by PMOS transistor M1, PMOS
Transistor M2 and PMOS transistor M3, nmos pass transistor M4, electric capacity CP and electric capacity CO are constituted,
PMOS transistor M1, PMOS transistor M3 are connected with the grid of nmos pass transistor M4 and access
Clock CK1, the grid incoming clock CK2 of PMOS transistor M2, the source electrode of PMOS transistor M1
It is connected with the drain electrode of PMOS transistor M2 and access input voltage VDD, PMOS transistor M1
The source electrode of drain electrode and PMOS transistor M2 is connected with one end of electric capacity CP respectively, PMOS transistor M3
Drain electrode be connected with the source electrode of PMOS transistor M2, the drain electrode of nmos pass transistor M4 and PMOS are brilliant
The drain electrode of body pipe M1 connects, and the source electrode of PMOS transistor M3 is connected with one end of electric capacity C0 and exports height
DC voltage OUT, the source electrode of nmos pass transistor M4 is connected with the other end of electric capacity C0 and connects ground.
When clock CK1, CK2 are low level (0), PMOS transistor M1 and PMOS transistor
M3 closes, and makes electric capacity CP charge to two ends after PMOS transistor M2 and nmos pass transistor M4 conducting
Voltage is VDD, when clock CK1, CK2 are high level (VDD), PMOS transistor M2 and
Nmos pass transistor M4 closes, PMOS transistor M1 and the conducting of PMOS transistor M3, PMOS
Transistor M1 and PMOS transistor M3 conducting moment, the electricity at input voltage VDD and electric capacity CP two ends
Pressure VDD is accumulated in the drain voltage of PMOS transistor M3, makes the drain voltage of PMOS transistor M3
Transient pulse is to 2VDD, and now the source voltage of PMOS transistor M2 is more than PMOS transistor M2
Threshold voltage | VTHP | and input voltage VDD sum, cause PMOS transistor M3 and PMOS brilliant
Leakage current is produced, until the source voltage of PMOS transistor M2 drop between body pipe M2
VDD+ | VTHP | stops, and final boost pressure controller output High Level DC Voltage OUT is VDD+ | VTHP |, as
Shown in Fig. 2.It is, therefore, desirable to provide a kind of produce two clock signals that size is 2VDD and two clocks
The contrary clock circuit of signal magnitude, is used for boost pressure controller, to solve leakage problem.
Additionally, in the boost pressure controller described in Fig. 1, only when clock CK1 and CK2 is high level,
Boost pressure controller can export High Level DC Voltage, causes the half the time wave of clock CK1 and clock CK2 work
Taking, the operating efficiency how improving boost pressure controller under the clock circuit effect providing is also a solution of being eager
Problem certainly.
Content of the invention
It is an object of the invention to provide a kind of clock circuit and boost-voltage regulator, defeated for clock to produce size
Enter anti-phase two clock signal of signal twice, when described clock circuit is used for boost pressure controller, can solve
The certainly problem of leakage current present in boost pressure controller, and solve to boost under existing clock circuit effect
The not high problem of adjuster operating efficiency.
For solving the problems referred to above, the invention provides a kind of clock circuit, comprising:
First clock voltage conversion module, for response when clock input signal is that high level exports size and is
First clock output signal of described clock input signal twice；
First phase inverter, input and the first clock voltage conversion module of described first phase inverter be connected,
For by anti-phase for described clock input signal output；And
The output of second clock voltage transformation module, described second clock voltage transformation module and the first phase inverter
End connects, for response when clock input signal is that to export size be described clock input signal two to low level
Second clock output signal again.
Further, in described clock circuit, each described clock voltage conversion module all include electric capacity,
Second phase inverter, the first PMOS transistor, the second PMOS transistor and the first nmos pass transistor,
In clock voltage conversion module each described, the input of described second phase inverter and one end of electric capacity
Be connected the input for described clock voltage conversion module, the output of described second phase inverter, first
The grid of the grid of PMOS transistor and the first nmos pass transistor is connected, the other end of described electric capacity,
The source electrode of the source electrode of the first PMOS transistor and the second PMOS transistor is connected, described 2nd PMOS
The feeder ear that the drain electrode of transistor is described clock voltage conversion module, the source of described first nmos pass transistor
Pole is grounded, the drain electrode of described first PMOS transistor, the grid of the second PMOS transistor and a NMOS
The drain electrode of transistor is connected the output for described clock voltage conversion module,
Wherein, the feeder ear of each described clock voltage conversion module is connected the power supply for described clock circuit
Hold and access input voltage.
Further, when described clock input signal is low level, described first clock voltage conversion module
In first PMOS transistor close and the second PMOS transistor and the first nmos pass transistor conducting, institute
Stating the electric capacity two ends in the first clock voltage conversion module and charging to input voltage size, described first clock is defeated
Going out signal is low level,
The second PMOS transistor in described second clock voltage transformation module and the first nmos pass transistor close
Closing and the first PMOS transistor conducting, described second clock output signal is the two of described clock input signal
Times；
When described clock input signal is high level, in described first clock voltage conversion module second
PMOS transistor and the first nmos pass transistor are closed and the first PMOS transistor conducting, when described first
Clock output signal is the twice of described clock input signal,
The first PMOS transistor in described second clock voltage transformation module is closed and the 2nd PMOS crystal
Pipe and the conducting of the first nmos pass transistor, the electric capacity two ends in described second clock voltage transformation module charge to
Input voltage size, described second clock output signal is low level.
Further, described first clock output signal is contrary with described second clock output signal.
In order to reach another aspect of the present invention, also provide a kind of boost-voltage regulator, comprising:
Described clock circuit；
Electric charge pump module, described electric charge pump module is connected with described clock circuit, is used for responding described clock electricity
Road output the first clock output signal and second clock output signal and export a High Level DC Voltage；
Comparison module, described comparison module is connected with electric charge pump module, for responding described High Level DC Voltage
Sampled signal and export a comparative result；
Control logic module, described control logic module is connected with comparison module, is used for responding and described compares knot
Really export a control signal；And
Oscillator, described oscillator is connected with control logic module and clock circuit, is used for responding described control
Signal and the work that controls described clock circuit；
Wherein, described electric charge pump module is connected with the feeder ear of clock circuit respectively with the feeder ear of oscillator.
Further, described electric charge pump module includes:
First electric charge pump and the second electric charge pump, described first electric charge pump and the second electric charge pump all include the 3rd PMOS
Transistor, the 4th PMOS transistor, the 5th PMOS transistor and the second nmos pass transistor, wherein,
The 3rd PMOS transistor in described first electric charge pump, the 5th PMOS transistor and the 2nd NMOS
The grid of transistor is connected the first input end as the first electric charge pump, the 4th in described first electric charge pump
The grid of PMOS transistor is as the second input of the first electric charge pump, and the first of described first electric charge pump is defeated
Enter end and the second input respectively with one of described first clock output signal and second clock output signal
Connect,
The 3rd PMOS transistor in described second electric charge pump, the 5th PMOS transistor and the 2nd NMOS
The grid of crystal is connected the first input end as the second electric charge pump, the 4th in described second electric charge pump
PMOS transistor as the second input of the second electric charge pump, the first input end of described second electric charge pump and
Second input exports with the first input end of described first electric charge pump and the first clock of the second input access
Signal and second clock output signal are contrary.
Further, when described clock input signal is low level or high level, in described boost pressure controller
First electric charge pump and the second electric charge pump alternately realize charging process or export described High Level DC Voltage.
Further, described electric charge pump module also includes the first electric capacity, the second electric capacity and the 3rd electric capacity,
The two ends of described first electric capacity are brilliant with the drain electrode of described 3rd PMOS transistor and the 4th PMOS respectively
The source electrode of body pipe connects, the source electrode of described 3rd PMOS transistor and the drain electrode phase of the 4th PMOS transistor
Connect and be connected to the feeder ear of described electric charge pump module, the drain electrode and the 4th of described 5th PMOS transistor
The source electrode of PMOS transistor connects, the drain electrode of described second nmos pass transistor and the 3rd PMOS transistor
Drain electrode connect, the described source electrode of the 5th PMOS transistor and one end of the 3rd electric capacity connect and described in exporting
High Level DC Voltage, the source electrode of described second nmos pass transistor and the other end of the 3rd electric capacity connect and connect ground,
The two ends of described second electric capacity are brilliant with the drain electrode of described 3rd PMOS transistor and the 4th PMOS respectively
The source electrode of body pipe connects, the source electrode of described 3rd PMOS transistor and the drain electrode phase of the 4th PMOS transistor
Connect and be connected to the feeder ear of described electric charge pump module, the drain electrode and the 4th of described 5th PMOS transistor
The source electrode of PMOS transistor connects, the drain electrode of described second nmos pass transistor and the 3rd PMOS transistor
Drain electrode connect, the described source electrode of the 5th PMOS transistor and one end of the 3rd electric capacity connect and described in exporting
High Level DC Voltage, the source electrode of described second nmos pass transistor and the other end of the 3rd electric capacity connect and connect ground.
Further, described comparison module includes:
Sampling resistor, is used for responding described High Level DC Voltage and producing sampled signal；And
Comparator, the inverting input of described comparator is connected with described sampled signal, described comparator same
Phase input and a reference voltage connect, and described comparator is for relatively more described sampled signal and reference voltage
Size and export control signal.
From above technical scheme, a kind of clock circuit disclosed by the invention includes the first clock voltage conversion
Module, for response when clock input signal is that to export size be described clock input signal twice to high level
The first clock output signal；First phase inverter, the input of described first phase inverter and the first clock voltage
Conversion module is connected, for by anti-phase for described clock input signal output；And second clock voltage transformation
Module, described second clock voltage transformation module is connected with the output of the first phase inverter, for response at that time
Clock input signal is that low level exports the second clock output letter that size is described clock input signal twice
Number, so the clock circuit that the present invention provides can export anti-phase two that size is clock input signal twice
Individual clock signal, clock circuit as will be described is used for existing boost pressure controller, can solve existing liter
Leakage problem present in pressure adjuster.
Additionally, no matter described clock input signal is for low level or high level, in described boost pressure controller
The first electric charge pump and the second electric charge pump alternately realize charging process or export described High Level DC Voltage, and include
The electric charge pump of described first electric charge pump and the second electric charge pump can export all the time and double the described of clock input signal
High Level DC Voltage.So, there is not boost-voltage regulator of the prior art in the described boost pressure controller of the present invention
Clock cycle waste, the problem that High Level DC Voltage is unstable and output voltage is not high, improve boost pressure controller
Operating efficiency.
Brief description
Fig. 1 is the structural representation of the boost pressure controller in an embodiment of prior art；
Fig. 2 is the High Level DC Voltage change schematic diagram of the boost pressure controller output shown in Fig. 1；
Fig. 3 is the clock circuit structural representation in the embodiment of the present invention one；
Fig. 4 be clock circuit in the embodiment of the present invention one receive clock input signal, output clock defeated
Go out the theoretical change schematic diagram of signal；
Fig. 5 is the circuit simulation oscillogram in the embodiment of the present invention one；
Fig. 6 is the boost-voltage regulator signal flow diagram in the embodiment of the present invention two；
Fig. 7 is the boost-voltage regulator functional block diagram shown in Fig. 6.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, right below in conjunction with the accompanying drawings
The detailed description of the invention of the present invention is described in detail.
Elaborate a lot of detail in the following description in order to fully understand the present invention.But the present invention
Can implement to be much different from alternate manner described here, those skilled in the art can without prejudice to
Doing similar popularization in the case of intension of the present invention, therefore the present invention is not limited by following public being embodied as.
Embodiment one
Seeing Fig. 3, a kind of clock circuit providing the present invention is described in detail.Described clock circuit 100
Including the first clock voltage conversion module the 101st, second clock voltage transformation module 102 and the first phase inverter
INV1.The input of described first clock voltage conversion module 101 receives clock input signal CK, works as clock
When input signal CK is high level, it is described clock that shown first clock voltage conversion module 101 exports size
First clock output signal CKH1 of input signal CK twice.The input of described first phase inverter INV1
Being connected with the first clock voltage conversion module 101, described first phase inverter INV1 can be by defeated for described clock
Enter the anti-phase output of signal CK.Described second clock voltage transformation module 102 is defeated with the first phase inverter INV1's
Go out end to connect, when described clock input signal CK is low level, described second clock voltage transformation module
The 102 clock output signal CK receiving the first anti-phase output of phase inverter INV1, i.e. now described second clock
The clock signal that voltage transformation module receives is high level, then the output of described second clock voltage transformation module
Size is second clock output signal CKH2 of described clock input signal CK twice.
Owing to depositing between described first clock voltage conversion module 101 and second clock voltage change module 102
At described first phase inverter INV1, the clock output signal of described first clock voltage conversion module 101 output
CKH1 is inevitable with the clock output signal CKH2 that described second clock voltage transformation module 102 exports contrary.
Therefore, described clock circuit 100 can produce two sizes and be respectively described clock input signal CK twice
The size of clock signal and described first clock output signal CKH1 and second clock output signal CKH2 is complete
Complete contrary.
Concrete, described first clock voltage conversion module 101 include electric capacity C0, the second phase inverter INV2,
First PMOS transistor MP1, the second PMOS transistor MP2 and the first nmos pass transistor MN1,
And the input of described second phase inverter INV2 is connected with one end of electric capacity C0 as described first clock electricity
The input of pressure conversion module, the output of described second phase inverter INV2, the first PMOS transistor MP1
Grid and the grid of the first nmos pass transistor MN1 be connected, the other end of described electric capacity C0, first
The source electrode of the source electrode of PMOS transistor MP1 and the second PMOS transistor MP2 is connected, and described second
The feeder ear that the drain electrode of PMOS transistor is described first clock voltage conversion module, a described NMOS
The source ground of transistor MN1, drain electrode, the 2nd PMOS of described first PMOS transistor MP1 are brilliant
The drain electrode of the grid of body pipe MP2 and the first nmos pass transistor MN1 is connected as described first clock electricity
The output of pressure conversion module 101, and export described first clock output signal CKH1.
Described second clock voltage transformation module 102 also include electric capacity C0, the second phase inverter INV2, first
PMOS transistor MP1, the second PMOS transistor MP2 and the first nmos pass transistor MN1, described
The interconnected relationship of each device of second clock voltage transformation module 102 and described first clock voltage conversion
The interconnected relationship of each device in module 101 is identical, and difference is: described second clock voltage
The input of the second phase inverter INV2 in conversion module 102 is connected as described with one end of electric capacity C0
The input of second clock voltage transformation module, and first in described second clock voltage transformation module 102
The drain electrode of PMOS transistor MP1, the grid of the second PMOS transistor MP2 and a NMOS crystal
The drain electrode of pipe MN1 is connected the output as described second clock voltage transformation module 101, and exports
Two clock output signal CKH2.
Described first clock voltage conversion module is connected with the feeder ear of second clock voltage transformation module conduct
The feeder ear of described clock circuit and access input voltage VDD.
Seeing Fig. 4 and Fig. 5, clock output signal CKH1, CKH2 of described clock circuit are according to when described
The change of clock input signal CK and different operation principles is as follows:
When described clock input signal CK is low level (0), described first clock voltage conversion module 101
In first PMOS transistor MP1 close, second in described first clock voltage conversion module 101
PMOS transistor MP2 and the first nmos pass transistor MN1 conducting, and described first clock voltage change
The grid of the second PMOS transistor MP2 in die change block 101 is connect by the first nmos pass transistor MN1
Ground, now, the clock output signal CKH1 of described first clock voltage conversion module 101 output is low electricity
Flat, by the second PMOS transistor MP2 in described first clock voltage conversion module 101 to electric capacity
C0 charges, until the voltage at electric capacity two ends is input voltage VDD, wherein, and described first clock voltage conversion
Clock signal CKM at the source electrode of the second PMOS transistor MP2 in module 101 and clock input letter
Number CK is consistent, and described clock input signal CK is in described first clock voltage conversion module 101
Clock signal CKN after second phase inverter INV2 is contrary with described clock input signal CK；
When described clock input signal CK is low level, in described second clock voltage transformation module 102
Second PMOS transistor MP2 and the first nmos pass transistor MN1 close, and described second clock voltage becomes
The first PMOS transistor MP1 conducting in die change block 102, then, described second clock voltage transformation mould
The output high level of the first phase inverter INV1 described in the voltage VDD superposition at the electric capacity C0 two ends in block 102
Voltage VDD so that the clock output signal CKH2 of described second clock voltage transformation module 102 output is
The twice of described clock input signal CK, is 2VDD, and wherein, described clock input signal CK passes through
After described first phase inverter INV1 is anti-phase, be positioned in described second clock voltage transformation module 102 second
Clock signal CKM at the source electrode of PMOS transistor MP2 ', contrary with clock input signal CK, institute
State clock input signal CK sequentially pass through after described first phase inverter INV1, the second phase inverter INV2 when
Clock signal CKN ', consistent with described clock input signal CK；
When described clock input signal CK is high level (VDD), described first clock voltage conversion mould
The second PMOS transistor MP2 in block 101 and the first nmos pass transistor MN1 close, and described first
First PMOS transistor MP1 conducting of clock voltage conversion module 101, now, described first clock electricity
The height of clock input signal CK described in the voltage VDD superposition at the electric capacity C0 two ends in pressure conversion module 101
Level voltage VDD so that the clock output signal CKH1 of described first clock voltage conversion module 101 output
It for the twice of described clock input signal CK, is 2VDD, wherein, described first clock voltage conversion mould
Clock signal CKM in block 101 and clock signal CKN are with the change of described clock input signal CK
Journey is constant；
When described clock input signal CK is high level, in described second clock voltage transformation module 102
First PMOS transistor MP1 is closed, the 2nd PMOS in described second clock voltage transformation module 102
Transistor MP2 and the first nmos pass transistor MN1 conducting, and described second clock voltage transformation module
The grid of the second PMOS transistor MP2 in 102 is grounded by the first nmos pass transistor MN1, this
When, the clock output signal CKH2 of described second clock voltage transformation module 102 output is low level, logical
The second PMOS transistor MP2 crossed in described second clock voltage transformation module 102 is charged to electric capacity C0,
Until the voltage at electric capacity two ends is input voltage VDD, wherein, described second clock voltage transformation module 102
In clock signal CKM ' and clock signal CKN ' with described clock input signal CK change procedure not
Become.
As can be seen here, the circuit simulation oscillogram shown in Fig. 5 is consistent with the notional result shown in Fig. 4, so
The clock circuit that the present invention provides can export anti-phase two the clock letter that size is clock input signal twice
Number.Clock circuit as will be described is used for existing boost pressure controller, can solve existing boost pressure controller
Present in leakage problem.
Embodiment two
Seeing Fig. 6 and Fig. 7, a kind of boost-voltage regulator providing the present invention is described in detail.Described boosting
Voltage-stablizer includes that the 300th, clock circuit of the present invention 100th, electric charge pump module the 200th, comparison module controls
Logic module 400 and oscillator 500.
The feeder ear of described electric charge pump module 200 is connected to the feeder ear of described clock circuit 100 and accesses defeated
Entering voltage VDD to start working to start, described electric charge pump module 200 is connected with described clock circuit 100,
The first clock output signal CKH1, the second clock output signal of the output of described clock circuit 100 can be received
CKH2, and output one High Level DC Voltage OUT.
Concrete, described electric charge pump mould 200 includes the first electric charge pump 201 and the second electric charge pump 202, described the
One electric charge pump 201 and the second electric charge pump 202 all include that the 3rd PMOS transistor T11, the 4th PMOS are brilliant
Body pipe T12, the 5th PMOS transistor T14 and the second nmos pass transistor T13.Wherein, described first
The 3rd PMOS transistor T11 in electric charge pump 201, the 5th PMOS transistor T14 and the 2nd NMOS
The grid of transistor T13 is connected and the first input end CPN1 as the first electric charge pump 201, and described first
The grid of the 4th PMOS transistor T12 in electric charge pump 201 is as the second input of the first electric charge pump 201
End CPP1.The 3rd PMOS transistor T11 in described second electric charge pump 201, the 5th PMOS transistor
The grid of T14 and the 2nd NMOS crystal T13 is connected the first input end as the second electric charge pump 202
CPN2, the 4th PMOS transistor T12 in described second electric charge pump 202 is as the second electric charge pump 202
Second input CPP2.
Further, described electric charge pump module also includes the first electric capacity CE1, the second electric capacity CE2 and the 3rd electricity
Hold CE3.The two ends of described first electric capacity CE1 respectively with the drain electrode of described 3rd PMOS transistor T11 and
The source electrode of the 4th PMOS transistor T12 connects, the source electrode and the 4th of described 3rd PMOS transistor T11
The drain electrode of PMOS transistor T12 is connected and is connected to the feeder ear of described electric charge pump module 200, described
The drain electrode of the 5th PMOS transistor T14 is connected with the source electrode of the 4th PMOS transistor T12, and described second
The drain electrode of nmos pass transistor T13 is connected with the drain electrode of the 3rd PMOS transistor T11, described 5th PMOS
One end of the source electrode of transistor T14 and the 3rd electric capacity CE3 connects and defeated as described electric charge pump module 200
Go out the described High Level DC Voltage OUT of end output, the source electrode of described second nmos pass transistor T13 and the 3rd electric capacity
The other end of CE3 connects and connects ground GND.
The drain electrode and the 4th with described 3rd PMOS transistor T11 respectively of the two ends of described second electric capacity CE2
The source electrode of PMOS transistor T12 connects, the source electrode of described 3rd PMOS transistor T11 and the 4th PMOS
The drain electrode of transistor T12 is connected and is connected to the feeder ear of described electric charge pump module 200, and the described 5th
The drain electrode of PMOS transistor T14 is connected with the source electrode of the 4th PMOS transistor T12, and the 2nd NMOS is brilliant
The drain electrode of body pipe T13 is connected with the drain electrode of the 3rd PMOS transistor T11, the 5th PMOS transistor T14
Source electrode and one end of the 3rd electric capacity CE3 be connected to the output of described electric charge pump module 200, described second
The other end of the source electrode of nmos pass transistor T13 and the 3rd electric capacity CE3 connects and connects ground GND.
When first input end and second input of described first electric charge pump 201 receive described clock circuit respectively
First clock output signal CKH1 of 100 outputs and during second clock output signal CKH2, then described the
The first input end of two electric charge pumps 202 and the second input receive the of described clock circuit 100 output respectively
Two clock output signal CKH2 and the first clock output signal CKH1；When described first electric charge pump 201
First input end and the second input receive the second clock output signal of described clock circuit 100 output respectively
During CKH2 and the first clock output signal CKH1, then the first input end of described second electric charge pump 202 and
Second input receives the first clock output signal CKH1 and second of described clock circuit 100 output respectively
Clock output signal CKH2.
Described comparison module 300 includes a sampling resistor 301 and comparator 302, described employing resistance 301 by
First resistance R1 and the second resistance R2 is constituted, and one end of described first resistance R1 receives described high direct current
Pressure OUT, the other end of described first resistance R1 is connected with one end of described second resistance R2 and exports one
Sampled signal, the other end ground connection of described second resistance R2, the inverting input of described comparator 302 and institute
Stating sampled signal to connect, the in-phase input end of described comparator 302 and reference voltage V REF connect.Institute
The output stating comparison module 300 with electric charge pump module 200 is connected, when described electric charge pump module 200 starts
When working and export described High Level DC Voltage OUT, described sampling resistor 301 responds described High Level DC Voltage
OUT and produce described sampled signal, when described sampled signal more than reference voltage V REF when, described comparison
The comparative result of device 302 output is 0, when described sampled signal is not more than reference voltage V REF, and described ratio
It is 1 compared with the comparative result of device 302 output.
Described control logic module 400 is connected with described comparison module 300, when described control logic module 400
When the comparative result receiving is 0, output makes the out-of-work control signal of described oscillator 500, works as institute
Stating the control comparative result that receives of logic module 400 when being 1, output makes described oscillator 500 continue to
The control signal of work.Further, described control logic module 400 can also receive Enable Pin ENB,
When described Enable Pin ENB enables, control Enable Pin ENB of described control logic module 400 output '
Enable, make described first electric charge pump and the second electric charge pump enable；When described Enable Pin ENB does not enables, institute
State control Enable Pin ENB of control logic module 400 output ' also do not enable, then described first electric charge pump and the
Two electric charge pumps do not enable.
The feeder ear of described oscillator 500 is connected to the feeder ear of described clock circuit 100 and accesses input electricity
Pressure VDD starts working to start, described oscillator 500 and control logic module 400 and clock circuit 100
Connecting, when the control signal that described oscillator 500 receives is stop signal, described oscillator 500 stops
Only work, thus control described clock circuit 100 and also quit work, until described comparison module 300 receives
The sampled signal of High Level DC Voltage OUT be not more than reference voltage V REF, described oscillator 500 is again
Control clock circuit is started working；When the control signal that described oscillator 500 receives is working signal,
Described oscillator 500 works, thus it is in running order to control described clock circuit 100.At the present embodiment
In, the comparative result of described comparator 302 output also can be 0, then output makes described oscillator 500 still continue
The control signal of continuous work；The comparative result of described comparator 302 output also can be 1, then output makes described
The out-of-work control signal of oscillator 500.
In side circuit, described input power VDD is divided into two groups of power supplys to reduce noise, one group of startup
Electric charge pump module, one group starts clock circuit, oscillator and control logic module simultaneously.In the present embodiment,
Only do principle to illustrate, but be not used in the input current limiting each module in the present invention.
Therefore, first input end and the second input such as described first electric charge pump 201 receive described respectively
One clock output signal CKH1 and second clock output signal CKH2, and described second electric charge pump 202
First input end and the second input receive described second clock output signal CKH2 respectively and the first clock is defeated
When going out signal CKH1, then when described clock input signal CK is low level, described first clock output
Signal CKH1 is low level, and described second clock output signal CKH2 is described clock input signal CK
Twice, then described first electric charge pump 201 realizes charging process, and described second electric charge pump 202 exports institute
State High Level DC Voltage, when described clock input signal CK is high level, described first clock output signal
CKH1 is the twice of described clock input signal CK, and described second clock output signal CKH2 is low level,
Then described first electric charge pump 201 exports described High Level DC Voltage, and described second electric charge pump 202 realizes charging
Process；
First input end and the second input such as described first electric charge pump 201 receive described second clock respectively
Output signal CKH2 and the first clock output signal CKH1, and the first of described second electric charge pump 202 is defeated
Enter end and the second input receives described first clock output signal CKH1 and second clock output signal respectively
During CKH2, then when described clock input signal CK is low level, described first clock output signal CKH1
For the twice of described clock input signal CK, described second clock output signal CKH2 is low level, then
Described first electric charge pump 201 exports described High Level DC Voltage, and described second electric charge pump 202 realizes charging
Journey, when described clock input signal CK is high level, described first clock output signal CKH1 is low
Level, described second clock output signal CKH2 is the twice of described clock input signal CK, then described
First electric charge pump 201 realizes charging process, and described second electric charge pump 202 exports described High Level DC Voltage.
Visible, no matter described clock input signal CK is for low level or high level, described boost pressure controller
In the first electric charge pump 201 and the second electric charge pump 202 alternately realize charging process or export described high direct current
Pressure OUT, and include that the electric charge pump 200 of described first electric charge pump 201 and the second electric charge pump 202 all the time can be defeated
Go out to double the described High Level DC Voltage OUT of clock input signal.So, the described boosting regulation of the present invention
There is not boost-voltage regulator clock cycle of the prior art waste in device, High Level DC Voltage is unstable and output is electric
Press not high problem, improve the operating efficiency of boost pressure controller.
In this specification, each embodiment uses the mode gone forward one by one to describe, and what each embodiment stressed is
With the difference of other embodiments, between each embodiment, identical similar portion sees mutually.For
For system disclosed in embodiment, owing to corresponding to the method disclosed in Example, so the comparison describing is simple
Single, related part sees method part and illustrates.
Professional further appreciates that, each example describing in conjunction with the embodiments described herein
Unit and algorithm steps, with electronic hardware, computer software or the two be implemented in combination in can be
Clearly demonstrate the interchangeability of hardware and software, retouch in general manner according to function in the above description
Composition and the step of each example are stated.These functions perform with hardware or software mode actually, depend on
The application-specific of technical scheme and design constraint.Each can specifically should be used for by professional and technical personnel
Use different methods to realize described function, but this realize it is not considered that beyond the scope of this invention.
Obviously, those skilled in the art can carry out various change and modification without deviating from the present invention to invention
Spirit and scope.So, if the present invention these modification and modification belong to the claims in the present invention and
Within the scope of equivalent technologies, then the present invention is also intended to change and including modification include these.
Claims (8)
1. a clock circuit, it is characterised in that include:
First clock voltage conversion module, for response when clock input signal is that high level exports size and is
First clock output signal of described clock input signal twice；
First phase inverter, input and the first clock voltage conversion module of described first phase inverter be connected,
For by anti-phase for described clock input signal output；And
The output of second clock voltage transformation module, described second clock voltage transformation module and the first phase inverter
End connects, for response when clock input signal is that to export size be described clock input signal two to low level
Second clock output signal again；
Each described clock voltage conversion module all include electric capacity, the second phase inverter, the first PMOS transistor,
Second PMOS transistor and the first nmos pass transistor,
In clock voltage conversion module each described, the input of described second phase inverter and one end of electric capacity
Be connected the input for described clock voltage conversion module, the output of described second phase inverter, first
The grid of the grid of PMOS transistor and the first nmos pass transistor is connected, the other end of described electric capacity,
The source electrode of the source electrode of the first PMOS transistor and the second PMOS transistor is connected, described 2nd PMOS
The feeder ear that the drain electrode of transistor is described clock voltage conversion module, the source of described first nmos pass transistor
Pole is grounded, the drain electrode of described first PMOS transistor, the grid of the second PMOS transistor and a NMOS
The drain electrode of transistor is connected the output for described clock voltage conversion module,
Wherein, the feeder ear of each described clock voltage conversion module is connected the power supply for described clock circuit
Hold and access input voltage.
2. clock circuit according to claim 1, it is characterised in that
When described clock input signal is low level, in described first clock voltage conversion module first
PMOS transistor is closed and the second PMOS transistor and the conducting of the first nmos pass transistor, when described first
Electric capacity two ends in clock voltage transformation module charge to input voltage size, and described first clock output signal is
Low level,
The second PMOS transistor in described second clock voltage transformation module and the first nmos pass transistor close
Closing and the first PMOS transistor conducting, described second clock output signal is the two of described clock input signal
Times；
When described clock input signal is high level, in described first clock voltage conversion module second
PMOS transistor and the first nmos pass transistor are closed and the first PMOS transistor conducting, when described first
Clock output signal is the twice of described clock input signal,
The first PMOS transistor in described second clock voltage transformation module is closed and the 2nd PMOS crystal
Pipe and the conducting of the first nmos pass transistor, the electric capacity two ends in described second clock voltage transformation module charge to
Input voltage size, described second clock output signal is low level.
3. clock circuit according to claim 1, it is characterised in that described first clock output signal
Contrary with described second clock output signal.
4. a boost-voltage regulator, it is characterised in that include:
Clock circuit as described in claims 1 to 3 any one；
Electric charge pump module, described electric charge pump module is connected with described clock circuit, is used for responding described clock electricity
Road output the first clock output signal and second clock output signal and export a High Level DC Voltage；
Comparison module, described comparison module is connected with electric charge pump module, for responding described High Level DC Voltage
Sampled signal and export a comparative result；
Control logic module, described control logic module is connected with comparison module, is used for responding and described compares knot
Really export a control signal；And
Oscillator, described oscillator is connected with control logic module and clock circuit, is used for responding described control
Signal and the work that controls described clock circuit；
Wherein, described electric charge pump module is connected with the feeder ear of clock circuit respectively with the feeder ear of oscillator.
5. boost-voltage regulator according to claim 4, it is characterised in that described electric charge pump module includes:
First electric charge pump and the second electric charge pump, described first electric charge pump and the second electric charge pump all include the 3rd PMOS
Transistor, the 4th PMOS transistor, the 5th PMOS transistor and the second nmos pass transistor, wherein,
The 3rd PMOS transistor in described first electric charge pump, the 5th PMOS transistor and the 2nd NMOS
The grid of transistor is connected the first input end as the first electric charge pump, the 4th in described first electric charge pump
The grid of PMOS transistor is as the second input of the first electric charge pump, and the first of described first electric charge pump is defeated
Enter end and the second input respectively with one of described first clock output signal and second clock output signal
Connect,
The 3rd PMOS transistor in described second electric charge pump, the 5th PMOS transistor and the 2nd NMOS
The grid of crystal is connected the first input end as the second electric charge pump, the 4th in described second electric charge pump
PMOS transistor as the second input of the second electric charge pump, the first input end of described second electric charge pump and
Second input exports with the first input end of described first electric charge pump and the first clock of the second input access
Signal and second clock output signal are contrary.
6. described boost-voltage regulator according to claim 5, it is characterised in that described clock input signal is
When low level or high level, the first electric charge pump and the second electric charge pump in described boost pressure controller replace realization and fill
Electric process or export described High Level DC Voltage.
7. boost-voltage regulator according to claim 6, it is characterised in that
Described electric charge pump module also includes the first electric capacity, the second electric capacity and the 3rd electric capacity；
In the first electric charge pump, the leakage with described 3rd PMOS transistor respectively of the two ends of described first electric capacity
The source electrode of pole and the 4th PMOS transistor connects, the source electrode of described 3rd PMOS transistor and the 4th PMOS
The drain electrode of transistor is connected and is connected to the feeder ear of described electric charge pump module, described 5th PMOS crystal
The drain electrode of pipe is connected with the source electrode of the 4th PMOS transistor, the drain electrode of described second nmos pass transistor and the
The drain electrode of three PMOS transistor connects, the source electrode of described 5th PMOS transistor and one end of the 3rd electric capacity
Connect and export described High Level DC Voltage, another of the source electrode of described second nmos pass transistor and the 3rd electric capacity
End connects and connects ground；
In the second electric charge pump, the leakage with described 3rd PMOS transistor respectively of the two ends of described second electric capacity
The source electrode of pole and the 4th PMOS transistor connects, the source electrode of described 3rd PMOS transistor and the 4th PMOS
The drain electrode of transistor is connected and is connected to the feeder ear of described electric charge pump module, described 5th PMOS crystal
The drain electrode of pipe is connected with the source electrode of the 4th PMOS transistor, the drain electrode of described second nmos pass transistor and the
The drain electrode of three PMOS transistor connects, the source electrode of described 5th PMOS transistor and one end of the 3rd electric capacity
Connect and export described High Level DC Voltage, another of the source electrode of described second nmos pass transistor and the 3rd electric capacity
End connects and connects ground.
8. described boost-voltage regulator according to claim 5, it is characterised in that described comparison module includes:
Sampling resistor, is used for responding described High Level DC Voltage and producing sampled signal；And
Comparator, the inverting input of described comparator is connected with described sampled signal, described comparator same
Phase input and a reference voltage connect, and described comparator is for relatively more described sampled signal and reference voltage
Size and export control signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310157122.7A CN103248223B (en) | 2013-04-28 | 2013-04-28 | Clock circuit and boost-voltage regulator |
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| CN201310157122.7A CN103248223B (en) | 2013-04-28 | 2013-04-28 | Clock circuit and boost-voltage regulator |
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| CN103248223B true CN103248223B (en) | 2016-11-02 |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104883052B (en) * | 2015-06-07 | 2017-11-14 | 上海华虹宏力半导体制造有限公司 | Lift condenser network and charge pump |
| CN105790574B (en) * | 2016-05-11 | 2018-03-30 | 上海华虹宏力半导体制造有限公司 | A kind of voltage multiplying circuit |
| CN106787691B (en) * | 2017-01-06 | 2019-08-27 | 上海华虹宏力半导体制造有限公司 | Charge pump circuit, charge pump system and memory |
| US10672453B2 (en) * | 2017-12-22 | 2020-06-02 | Nanya Technology Corporation | Voltage system providing pump voltage for memory device and method for operating the same |
| CN109074112B (en) * | 2018-08-02 | 2021-02-09 | 深圳市汇顶科技股份有限公司 | Voltage stabilizer, control circuit of voltage stabilizer, and control method of voltage stabilizer |
| US11508719B2 (en) * | 2019-05-13 | 2022-11-22 | Ememory Technology Inc. | Electrostatic discharge circuit |
| CN115437449B (en) * | 2021-06-02 | 2024-01-26 | 合肥格易集成电路有限公司 | Clock booster circuit, on-chip high voltage generation circuit, and electronic device |
| CN114167936B (en) * | 2021-12-03 | 2022-11-22 | 中国科学院半导体研究所 | CMOS charge pump pumping device with wide working voltage range |
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| CN103248223A (en) | 2013-08-14 |
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