CN103238208B - Silicon and SiGe nano thread structure - Google Patents
Silicon and SiGe nano thread structure Download PDFInfo
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- CN103238208B CN103238208B CN201180058034.0A CN201180058034A CN103238208B CN 103238208 B CN103238208 B CN 103238208B CN 201180058034 A CN201180058034 A CN 201180058034A CN 103238208 B CN103238208 B CN 103238208B
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Abstract
Describe the method forming microelectronic structure.The embodiment of these methods includes forming nano-wire devices, and this nano-wire devices includes: substrate, and substrate includes the source/drain structures being positioned near sept；And the nanowire channel structure between sept, wherein nanowire channel structure is being vertically stacked one above another.
Description
Background
Along with Size of Microelectronic Devices rose the node of 15nm, keep mobility to improve and short channel controls device system
Make and propose challenge.The short channel improved is provided to control for manufacturing the nano wire of device.Such as, SiGe (SixGe1-x) nanometer
Wire channel structure (wherein x ＜ 0.5) provides the mobility under considerable Eg to improve, and this is applicable to utilize high voltage to operate
Many traditional products.Additionally, SiGe (SixGe1-x) nanowire channel (wherein x ＞ 0.5) provides the migration of improvement under relatively low Eg
Rate (is applicable to the low-voltage product in such as mobile/handheld field).
Accompanying drawing is sketched
Although description using particularly point out and require independently claims of some embodiment as ending, but each reality
The advantage executing example can be better understood, in the accompanying drawings from the following description of the accompanying drawings of embodiments:
Fig. 1 a-1n illustrates the method forming structure according to each embodiment.
Fig. 2 a-2i illustrates the method forming structure according to each embodiment.
Fig. 3 a-3g illustrates the method forming structure according to each embodiment.
Fig. 4 a-4m illustrates the method forming structure according to each embodiment.
Fig. 5 a-5d illustrates the method forming structure according to each embodiment.
Fig. 6 illustrates the system according to each embodiment.
Describe in detail
In detailed further below to the embodiment of the present invention, the accompanying drawing illustrating the specific embodiment that can put into practice is made
Go out reference.Fully describe these embodiments in detail, so that these embodiments are put into practice by those skilled in the art.Manage
Solving, each embodiment is despite different, but is not necessarily mutually exclusive.Such as, the spy described here in conjunction with an embodiment
Determine feature, structure or characteristic and can be implemented without departing from their spirit and scope in other embodiments.In addition, it is to be understood that can repair
The position of each key element in the most each open embodiment or configuration are without deviating from their spirit and scope.Therefore, below detailed
Thin description does not have a limiting meaning, and the scope of each embodiment only by the appended claims suitably explained together with these
The four corner of the equivalent of claims issue defines.In the accompanying drawings, identical reference runs through some accompanying drawing earth's surfaces
Show same or analogous function.
Describe method and the dependency structure forming and utilizing the such as microelectronic structure of nano-wire devices structure etc.This
A little method and structures comprise the steps that and form the nano-wire devices comprising substrate, and this substrate includes source/drain structures, this source/drain
Electrode structure is included in the nano wire between source/drain structures, and wherein this nanowire channel structure is on vertical stratum over each other
Folded.Here each embodiment included along with device size rose this node of 15nm time allow mobility improve and short channel control
System.These embodiments further improve the insulation of raceway groove and substrate, alleviate the electric capacity relevant to sept gap clearance with
And by vertical configuration extension (scaling) of nano wire.
Fig. 1 a-1n illustrates the embodiment forming microelectronic structure (such as forming nano-wire devices structure).Fig. 1 a illustrates one
Substrate 100.In one embodiment, substrate 100 can include bulk silicon substrate 100.In other embodiments, substrate 100 can wrap
Include silicon in insulator substrates (SOI) 100, but may also comprise any kind of suitable backing material.In one embodiment, first
SiGe 102 material can be grown on the substrate 100 by epitaxial growth.In one embodiment, the first silicon materials 104 epitaxial growth exists
On first SiGe 102 of extension.Second germanium-silicon layer 102 ' may be formed on the first silicon layer 102, and the second silicon layer 104 ' can shape
Become on the second SiGe 102 '.In another embodiment, epitaxial silicon germanium layer 102/ epitaxial silicon alternately on the substrate 100 is formed
The number of layer 104 can change according to concrete application.In another embodiment, layer order can be overturned, i.e. formed on the substrate 100
Epitaxial silicon 104 and the alternating layer of epitaxial sige 102.
In one embodiment, can use traditional Butut/etching technique (Fig. 1 b) that the extension of SiGe/Si/SiGe/Si is folded
Layer 120 is patterned.Such as, laminated construction 120 can be etched in groove etching process, such as, isolate (STI) at shallow trench
During technique, to form fin structure 107 in wherein groove 101 may be formed at substrate 100.The each fin structure 107 formed can
Being spaced apart by oxide 103, oxide 103 may be formed in groove 101.
In one embodiment, fin structure 107 can include that grid surround the double channel part of (GAA) nano-wire devices completely.Device
The number of plies that raceway groove number in part will depend in fin structure 107.Fin structure 107 can include nano thread structure.Sept 106 can
It is formed on fin structure 107 and across fin structure 107, and (Fig. 1 c) can be normally located otherwise relative to fin structure 107.Real one
Executing in example, sept 106 may be included in any material selectable during fin structure 107 materials processing.
In one embodiment, within/between gate material 108 may be formed at sept 106, and may be formed at fin structure
107 all portion between sept 106.In one embodiment, gate material may be formed at fin structure 107
Portion, and sept 106 is formed at the either side of grid.In some cases, grid 108 can include polysilicon, and can include
Sacrificial gate structure 108.In one embodiment, a part of fin structure 107 can be gone divided by exposing source/drain regions from substrate 100
109 (Fig. 1 d).In one embodiment, a part for fin structure 107 can be etched away so that source/drain regions by dry etching process
109 expose.In one embodiment, etchable source/drain regions 109 so that its terminate in substrate 100 or bottom circuit (102 or
104) on.Available selective incision wet corrosion or dry etching process are most advanced and sophisticated to remove grid 108 district according to concrete device requirement
(tip) additional materials in overlay region.
In one embodiment, silicon or silicon Germanium source drain structure 110 may utilize growth technology in source/drain regions
Grow (Fig. 1 e) in 109, and the fin structure 107 part between sept 106 can be coupled to.In one embodiment, extension
Source/drain structures 110 could be for the n doped silicon of nmos device, or the p doped silicon/SiGe for PMOS device,
This depends on the type of device of concrete application.Can by injecting, by plasma doping, adulterated by solid source or known in the industry
Other method doping is incorporated in epitaxy technique.
Tip and source/drain can be designed by doping being combined with the epitaxial layer of different dopant species and concentration
Knot.Such as, can be at source/drain SiGe when utilizing silicon Germanium source/drain electrode and add and strain in the silicon raceway groove of PMOS device
First grow silicon etch stop layer/tip 112 before epitaxial structure 110 growth, thus avoid in follow-up SiGe etch process
Source/drain regions 110 is made etching (Fig. 1 f).In other words, PMOS tip material needs follow-up SiGe etch process
There is resistance.
Interlayer dielectric (ILD) can be formed at lining on source/drain structures 110 and grid 108, sept 106
On the end 100 (not shown).In one embodiment, the top sacrificing polycrystalline grid 108 can be opened by chemically mechanical polishing (CMP)
Open.Then sacrificial gate electrode material 108 is removed (Fig. 1 g) between spacer material 106.Fig. 1 h illustrates between sept 106
Inner side figure, wherein fin structure 107 is arranged between two septs (only illustrating in figure).In one embodiment, may be used
Selectively silicon layer 104,104 ' is gone divided by opening clearance 111(Fig. 1 i between SiGe raceway groove 102,102 ' from fin structure 107).
In one embodiment, optionally by wet corrosion, silicon layer 104,104 ' is etched, this wet corrosion optionally remove silicon 104,
104 ' do not etch SiGe nano thread structure 102,102 ' simultaneously.The most hydrophilic available hydroxide chemical agent (includes hydrogen-oxygen
Change ammonium and potassium hydroxide) etc etching chemistry medicament be etched selectively to silicon.
In another embodiment, selectively germanium-silicon layer 102,102 ' is gone divided by silicon from fin structure 107 with from sidewall
Opening clearance 113 (Fig. 1 j) between channel layer 104,104 '.In one embodiment, SiGe can be etched selectively to by wet corrosion
102,102 ', this wet corrosion is optionally removed SiGe and is not etched silicon nanowires raceway groove 104,104 ' simultaneously.Available such as lemon
The etching chemistry medicament of lemon acid/nitric acid/HF chemical agent and citric acid/nitric acid/HF etc is etched selectively to SiGe.Cause
This, can remove silicon layer from fin structure 107, or be gone divided by the ditch between sept 106 from fin structure 107 by germanium-silicon layer
Silicon channel nanowire 104,104 ' structure is formed in road district.In one embodiment, silicon and SiGe channel material may be present in same
On wafer, in same tube core or on same circuit, such as the NMOS Si in inverter structure and PMOS SiGe.At same circuit
In have in the embodiment of NMOS Si and PMOS SiGe, can mutually select Si channel thickness (SiGe intermediate layer) and SiGe raceway groove
Thickness (Si intermediate layer) is to improve circuit performance and/or circuit minimum.In one embodiment, etch process can be passed through
Change the number of lead wires on the different components in same circuit to improve circuit performance and/or circuit minimum.
Gate dielectric material 115 can be formed so that it surrounds the channel region between sept 106.In one embodiment,
Gate dielectric material 115 can include high k gate material, and its medium dielectric constant microwave medium can include the value higher than about 4.Implement one
In example, the silicon nanowire structure 104,104 ' that gate dielectric material 115 can surround between sept 106 completely is conformally formed
(Fig. 1 k).In another embodiment, gate material 115 can surround the SiGe nano thread structure between sept 106 completely
102, (not shown) 102 ' is formed.
Then gate material 117 may be formed at around gate dielectric material 115 (Fig. 1 l).Gate material 117 can
Including the metal gate electrode material of the alloy of such as simple metal and Ti, W, Ta, Al, including the nitride of such as TaN, TiN, also wrap
Include the alloy with rare earth or the noble metal of such as Pt of such as Er, Dy.Gap 113 between silicon nanowire structure 104,104 '
Available gate material 117 is filled.In another embodiment, the gap 111 between SiGe nano thread structure 102,102 ' can be used
Gate material 117 fills (not shown).In one embodiment, can perform the most further standard CMOS processing with
Manufacture the cmos device according to embodiment described herein.
In one embodiment, NMOS and/or PMOS device can be formed.Fig. 1 m illustrates that the nmos device that can be formed (illustrates one
Individual silicon raceway groove), wherein groove contact 119 coupled to source drain structure 110, and this source drain structure 110 is in some cases
Can be the n+ of silicon doping, this depends on concrete application.Silicon epitaxy tip 112 can be that n-adulterates also in some cases
May be provided between source drain structure 110 and substrate 100.Gate material 117 can surround silicon nanowires raceway groove 104.
Fig. 1 n illustrates PMOS device (illustrating a silicon raceway groove 104), and wherein groove contact 119 coupled to source drain structure
110, this source drain structure 110 can be the p+ of germanium doped silicon in some cases, and this depends on concrete application.At some
Under situation can be the silicon epitaxy of p-doping most advanced and sophisticated/only erosion portion 120 may be provided between source drain structure 110 and substrate 100.
Gate material 117 can surround silicon raceway groove 104, and this silicon raceway groove 104 can include the silicon raceway groove 104 of strain in some cases.
In some cases, utilize the device of SiGe channel structure (those structures drawn in such as Fig. 1 i) due to SiGe
Characteristic comprises high carrier mobility and has advantage.In one embodiment, grid surround the technique of SiGe channel device completely can
It is similar to grid and surrounds silicon channel device technique completely, except epitaxial layers stack 120 may be contrary, namely initially by silicon materials
104 are formed on substrate and form SiGe on silicon.Owing to silicon lower floor will be selectively removed to SiGe, therefore source/drain
Pole can include that the only erosion portion below SiGe, and sacrificial gate electrode material may also comprise SiGe to avoid substrate etch.
The embodiments herein allows to manufacture self aligned grid and surrounds (GAA) silicon and SiGe trench transistor structure and device completely
Part.Owing to short-channel effect (SCE) reduces, nanowire channel device shows relatively low subthreshold leakage.GAA SiGe height migrates
The realization of rate channel device such as inhibits SCE effect.(GAA) the device maximizing electrostatic gate control to raceway groove.
In one embodiment, the device according to embodiments herein manufacture can be provided with the insulated substrate of enhancing.See figure
2a, arranges bottom nanowire channel 202 on the substrate 200 and can include having the short by three of inferior sub-fin leakage in some cases
Grid.A kind of scheme may be included in and forms device (Fig. 2 b-2c), wherein source/drain on silicon-on-insulator (SOI) substrate 201
Structure 210 and nano thread structure 204 are arranged on the insulating material 203 of such as oxide material 203 etc rather than set
Put on bulk silicon substrate 200 (as shown in Figure 2 a).By using SOI substrate 201, (example can be similar at nano wire fin structure
Nano wire fin structure 107 as in Fig. 1 b) SiGe etching after and formed gate material (be similar in such as Fig. 1 l
Gate material 117) before by etching bottom oxide limit bottom nano wire 204 geometry.
Such as, Fig. 2 d illustrate etching electrolyte to form a nano wire and three grid structures, and Fig. 2 e illustrates erosion
Carve electrolyte to form the device comprising two nano wires.In another embodiment, can pass through after trench etch in fin 207 side
Form fin sept 211 on wall and obtain the insulated substrate (Fig. 2 f) of improvement.Then the second trench etch 214 can be performed to expose
Fin district 216, bottom, and silicon part (Fig. 2 g) in fin district, oxidable bottom 216.Therefore, the bottom nano wire of device may be disposed at
To improve insulated substrate on oxide.In another embodiment, fin sept 211 can be formed at after trench etch and filling
On fin 207 sidewall (Fig. 2 h).The silicon portion, the end 216 of fin 207 can be oxidized to improve after STI indentation/oxide is filled
Insulated substrate (Fig. 2 i).Therefore, the bottom nano wire of device may be disposed on oxide to improve insulated substrate.
In one embodiment, can exist in sept 306 by the removal of the silicon area of nano wire lamination 307 is stayed
Gap 311 (Fig. 3 a).After the grid adding such as metal gate structure (being similar to the grid structure 117 of such as Fig. 1 l),
Gap 311 can form the parasitic district of very high capacitance between the grid being subsequently formed and source drain structure 310.In an embodiment
In, can be by utilizing epitaxial oxide 302 rather than silicon (may needing or change perhaps without the orientation on silicon substrate 300)
Potential parasitic district (Fig. 3 b) is avoided as initial lamination.In one embodiment, can be formed on extension oxide material 302
The alternating layer of epitaxial semiconductor material 304, this epitaxial oxide material 302 may be formed on substrate 300.
Such as, Gd2O3Can epitaxial growth on (111) silicon, then at Gd2O3Top on grow SiGe to build on substrate
Vertical one multilayer laminated, this substrate can be etched into fin structure 307, is formed as SiGe line after this fin structure 307.Real at another
Executing in example, it is multilayer laminated to be formed that ceria can be grown on (111) silicon (or being alternatively grown on (100) silicon).Pass through
Oxide/semiconductor/oxide stack, exists the oxide material not etching, partly etch or be fully etched fin structure 307
302, the selection (being shown respectively in Fig. 3 c-3e) of 302 '.The selection (Fig. 3 c) not etched solves capacitance problem, but its cost is
More inferior confinement (confinement)；The selection (Fig. 3 d) of part etching improves confinement property but its cost is a certain journey
The parasitic capacitance of degree.
In another embodiment, before source drain epitaxial growth, available second sept 312 fills position in sept
Gap 311 (as shown in Figure 3 a) near fin structure, this second sept 312 includes the source/drain from sept 306
Interval composition material 312 that 310 sides start or low-k materials 312 (Fig. 3 f).Such as, such as, but not limited to SiON, SiN, SiC,
The material of SiOBN and low k oxide can include the second sept 312 material.In one embodiment, can in etching lamination 307
Remove all of silicon, so that replacement gate etching (removal of sacrificial gate electrode material) only hits oxide.In another embodiment
In, only a part silicon is removed, so that replacement gate etching is actually corroded to silicon.In another embodiment, can (sink at grid
Before Ji) start to fill gap 311 (Fig. 3 g) from gate electrode side with interval composition material 312 or low-k materials 312.Embodiment includes
Perform being fully etched or part etching (being illustrated as being fully etched) of lamination 307.
In another embodiment, gap 311 can be filled to go from lamination 307 by the anisotropy utilizing silicon to etch
Except the etching making silicon during step minimizes.Such as, (110) wafer of the raceway groove with edge<111>can be used.This structure will tool
There is slow erosion (111) plane towards source/drain structures 310, thus limit incision.Here the wet corrosion selected also must than Si more
Etch SiGe lentamente, thus after all silicon removed between SiGe nano wire, reserve the SiGe nano wire of part etching.
Therefore, anisotropic etching can be used to minimize the lateral etch in sept 306, wherein silicon is had by etching chemistry medicament
High selectivity and SiGe is not had selectivity.
In one embodiment, available nano wire realizes vertical configuration extension.In one embodiment, SiGe or silicon can be from linings
The end, is epitaxially grown in groove, then can use such as oxidation or etch process that fin structure is divided into a plurality of nano wire, its
In all nano wires can vertically be layered in over each other.In one embodiment, sliver can be aoxidized, wherein source/drain
Polar region starts with SiGe (or Si and oxide) layer.Oxide 404 alternately and nitride layer can be formed on silicon substrate 401
402 (more layer can be used to form more wire) (Fig. 4 a).Can be to oxide and nitride layer Butut and etching with shape
Becoming groove 405 and back 406, wherein groove 405 makes the silicon materials of substrate 401 expose (Fig. 4 b).SiGe (or silicon) 407 can be at ditch
Groove 405 and rear portion are epitaxially grown, and can polished (Fig. 4 c).Hard mask 408 can be formed on SiGe (or silicon) 407, and can
To its Butut and etching so that (Fig. 4 d) is exposed in the side of fin 410.In one embodiment, can be by removing nitride and oxide
The part that do not covered by hard mask in alternating layer and form fin structure.
Fin 410 can be oxidized to define nano wire (Fig. 4 e).The oxidized portion of removable fin 410 to form nano wire 412,
This nano wire 412 may act as the channel structure of device and can be formed generally across total.In one embodiment, first receive
Rice noodle 412 can be vertically disposed at the second nano wire 412 ' top.In another embodiment, line can only be defined at channel region
(Fig. 4 g-4j).Second mask material 413, such as SiC, may be formed at around fin structure 410.Second mask material 413 is to oxidation
Thing and nitride can have selectivity.Fin structure 410 can include oxide/nitride film alternately, during this is with such as Fig. 4 d
Those are similar to.Groove 414 can be opened to be defined in gate regions near fin structure 410, can subsequently form gate electrode herein
Material and a portion fin structure 410 can expose (Fig. 4 h).Can perform to aoxidize to define nano wire (Fig. 4 i), and can pass through
The oxidized portion removing fin structure defines these lines (Fig. 4 j) further.Therefore, these lines are formed on gate regions/groove
In 414 rather than in source/drain regions.
For making the photoetching of Butut nano wire consider to become easy, spacer process can be used.Here, can by etching around
The nitride of Si or SiGe fin 410 exposes the sidepiece of Si or SiGe fin 410, and (and top can be covered by the hard mask 421 of such as SiC
Lid), and form sept 420(Fig. 4 k by the combination of isotropic deposition and anisotropic etching).Then use between being somebody's turn to do
Parting 420 is used as the mask of etching so that the sidewall of fin 410 exposes.Then sept 420 can be removed.
In another embodiment, fin is divided into a plurality of line as shown in Fig. 4 l by anisotropy wet corrosion.First can use wet
Oxide etching is fallen by erosion.Then, Si or SiGe anisotropy wet corrosion can be used to etch SiGe or Si that fin 410 exposes.By
Etch-rate dependency in crystallographic direction, can form nano wire.In one embodiment, after two kinds of etchings are performed, can be by
Nano wire is formed as hexagon.Si or SiGe fin can form (Fig. 4 m) after removing oxide.
The vertical extension of nano wire can be realized.Owing to nanowire size can be limited to about 7nm by phon scattering, this can limit
Make the long expansion of this kind of device.A kind of scheme is vertically to construct device, and wherein N-channel or P-channel are positioned at bottom
In line, another raceway groove is positioned at top line.In one embodiment, N+ substrate can be used for Vss.In another embodiment, top and
Bottom contact can be misalignment.In another embodiment, can be formed there is the line of the left and right wing.Fig. 5 a be shown through for
The inverter that the N+ substrate 500 of Vss and grid 501 complete.Note this needs: high contact 512 (TCN), receive in order to connect N and P
Rice noodle raceway groove 514；Short top TCN510, in order to be coupled in the one in N and P nanowire channel 514；And substrate insert 508/
Bottom TCN, it coupled to the one in N and P nanowire channel 514 and coupled to substrate 500.Fig. 5 b illustrates out-of-alignment top
510 and bottom 508TCN.Fig. 5 c illustrates N and the P nano wire containing left wing and right flank nano thread structure 514.Fig. 5 d illustrates that wiring has
Left wing and the inverter of right flank nano thread structure 514.
The nano wire offer with GAA is better than GAA non-nano line structure and fin and the improvement of three grid structures.Make apparatus
The lateral nano wire having replacement metal gate (RMG), grid encirclement completely to process is from having the plane of RMG to the fin with RMG
Route map logic extend.Grid surround (GAA) nano thread structure completely and give with GAA non-nano line structure and fin Comparatively speaking
The potentiality that the short channel improved controls.The bottom line insulation improved in the silicon or SiGe nano thread structure of substrate can be according to this
Literary composition embodiment is reached.
When minimum nanowire size is limited in ＞～7nm due to phon scattering, density can be allowed to extend.Silicon and silicon
The lateral nano thread structure of both germanium can in conjunction with replacement metal gate framework and to from the line of these modification in construction (towards three grids
Structural Development) produce compatible manufacturing technology.Can realize being extended by the vertical configuration of nano wire.Here allow to use nano wire
Circuit is constructed in transistor layer itself.
Fig. 6 illustrates the computer system according to an embodiment.In certain embodiments, system 600 include processor 610,
Storage component part 620, Memory Controller 630, graphics controller 640, input and export (I/O) controller 650, display
652, keyboard 654, pointing device 656, ancillary equipment 658, all these parts are the most coupled to each other by bus 660.
Processor 610 can be general processor or special IC (ASIC).I/O controller 650 can include for wired or nothing
The communication module of line communication.Memory devices 620 can be dynamic random access memory (DRAM) device, static random-access
Memorizer (SRAM) device, flush memory device or the combination of these storage component parts.Therefore, in certain embodiments, in system 600
Storage component part 620 not necessarily include DRAM device.
It is one or more that one or more parts shown in system 600 can include in each embodiment comprised herein
Nano-wire devices.Such as, processor 610 or at least some of or these parts of storage component part 620 or I/O controller 650
Combination may be included in integrated circuit package, this integrated circuit package includes at least one embodiment of structure described herein.
These parts perform they traditional functions known in the industry.Especially, by processor 710 term of execution, memorizer
Equipment 620 can be used for providing the length of the executable instruction to the method forming the structure according to some embodiments in some cases
Phase stores, and can be used to store in short time the method for forming the structure according to these embodiments in other embodiments can
Perform instruction.It addition, instruction can be stored or be otherwise associated with system can the machine accessible medium of communicative couplings,
Machine accessible medium e.g. compact disk read only memory (CD-ROM), digital versatile disc (DVD), floppy disk, carrier wave and/or
Other signal propagated.In one embodiment, memory devices 620 can to processor 610 provide executable instruction for
Perform.
System 600 can include computer (such as desktop computer, laptop computer, handheld computer, server, Web appliance,
Router etc.), Wireless Telecom Equipment (such as cell phone, wireless phone, pager, personal digital assistant etc.), calculate office
The ancillary equipment (such as printer, scanner, monitor etc.) of connection, amusement equipment (such as television set, radio, stereo, magnetic
Band and compact disk player, video cassette videocorder, field camera, digital camera, MP3 (motion picture expert group, sound
Frequently layer 3) player, video-game, wrist-watch etc.), like this.
Although description above has some particular step and material that can be used in embodiment, but skill in this area
Art personnel are it will be appreciated that many correction and replacement can be made.Therefore, all these corrections, change, substitute and add and all should be recognized
For being to fall in the spirit and scope that embodiment is defined by the appended claims.In addition, it is to be understood that such as transistor device
Various microelectronic structures are known in the art.Therefore, accompanying drawing given here only illustrates relevant to the practice of embodiment
Divide exemplary microelectronic structures.Therefore, embodiment is not limited to structure described herein.
Claims (37)
1. the method forming device, including:
Substrate is formed epitaxial sige；
Described epitaxial sige is formed epitaxial silicon；
The epitaxial silicon being arranged on described epitaxial sige is patterned to form fin structure, and described Butut includes etching described epitaxial silicon
With described epitaxial sige；
Described fin structure is formed altered sacrificial gate electrode；
The adjacent sidewalls of described altered sacrificial gate electrode and on described fin structure formed sept；
A part for described fin structure, then shape on described source/drain regions are removed in source/drain regions from described substrate
Becoming source/drain structures, wherein said source/drain regions is positioned near described sept；
Described altered sacrificial gate electrode is removed between described sept；And
The one described epitaxial silicon and epitaxial sige is removed from the fin structure between described sept.
2. the method for claim 1, it is characterised in that described structure includes that grid surround of nano-wire devices completely
Point.
3. the method for claim 1, it is characterised in that be additionally included on epitaxial silicon and form adding alternately of epitaxial sige
Layer.
4. the method for claim 1, it is characterised in that from described fin structure remove described epitaxial silicon with formed by
The SiGe nano thread structure that gap is spaced apart.
5. the method for claim 1, it is characterised in that remove described SiGe from described fin structure and pass through gap to be formed
The silicon nanowire structure being spaced apart.
6. method as claimed in claim 4, it is characterised in that gate-dielectric is formed on described SiGe nano thread structure
Around all sides.
7. method as claimed in claim 5, it is characterised in that gate-dielectric is formed on the institute of described silicon nanowire structure
Have around side.
8. method as claimed in claim 6, it is characterised in that gate material is formed on described SiGe nano thread structure week
Enclose.
9. method as claimed in claim 7, it is characterised in that gate material is formed on described silicon nanowire structure week
Enclose.
10. method as claimed in claim 8, it is characterised in that described gate material is formed on described SiGe nano wire
Structure periphery.
11. methods as claimed in claim 9, it is characterised in that described gate material includes metal.
12. methods as claimed in claim 10, it is characterised in that described gate material includes metal.
13. methods as claimed in claim 9, it is characterised in that groove contact coupled to described source/drain structures, and
Described source/drain structures includes the silicon that n+ adulterates.
14. methods as claimed in claim 13, it is characterised in that silicon epitaxy tip is disposed in described source/drain structures
And between described substrate.
15. methods as claimed in claim 9, it is characterised in that described device includes that NMOS grid surround channel device completely
A part.
16. methods as claimed in claim 9, it is characterised in that groove contact coupled to described source/drain structures, described
Source/drain structures includes p+ SiGe.
17. methods as claimed in claim 16, it is characterised in that silicon epitaxy tip is disposed in described source/drain structures
And between described substrate.
18. methods as claimed in claim 17, it is characterised in that described device includes that PMOS grid surround channel device completely
A part, and described silicon nanowires include strain silicon nanowires.
19. 1 kinds of methods forming nano-wire devices, including:
Form the alternating layer of epitaxial silicon on epitaxial sige on soi substrates；
Described alternating layer is patterned to form fin structure, described Butut include etching epitaxial silicon on described epitaxial sige alternately
Layer；
Described fin structure is formed altered sacrificial gate electrode；
The adjacent sidewalls of described altered sacrificial gate electrode and on described fin structure formed sept；
A part for described fin structure, then shape on described source/drain regions are removed in source/drain regions from described substrate
Becoming source/drain structures, wherein said source/drain regions is positioned near described sept；
Described altered sacrificial gate electrode is removed between described sept；And
The one described epitaxial silicon and described epitaxial sige is removed from the fin structure between described sept.
20. methods as claimed in claim 19, it is characterised in that the bottom nanowire geometry shape of described fin structure is to pass through
The etching of the bottom oxide part of described SOI substrate is limited by control.
21. methods as claimed in claim 20, it is characterised in that described bottom oxide is etched to form a nano wire
With three grid structures.
22. methods as claimed in claim 20, it is characterised in that described bottom oxide is etched to form two nanometers
Line.
23. 1 kinds of nano-wire devices structures, including:
Being vertically disposed at the nanowire channel structure on the gate regions of cmos device, described nanowire channel structure includes silicon
One in nano wire and SiGe nano wire, wherein said nanowire channel structure include being vertically disposed at the second nano wire it
On the first nano wire；
Gate electrode, the part of wherein said gate electrode is on described nanowire channel structure；
Sidewall spacer, the part of wherein said sidewall spacer laterally adjacent to described gate electrode in described nanowire channel
Part on structure；And
Source/drain structures, is epitaxially grown the either side in described nanowire channel structure, wherein said source/drain junctions
The part of structure is laterally adjacent to the described part of described sidewall spacer, and the described part of described sidewall spacer is the most neighbouring
The part on described nanowire channel structure of described gate electrode.
24. structures as claimed in claim 23, it is characterised in that described nanowire channel structure is substantially provided in whole device
In part structure.
25. 1 kinds of nano-wire devices, including:
Substrate；
Arranging nanowire channel structure over the substrate, wherein said nanowire channel structure is on vertical stratum over each other
Folded；
Gate electrode, the part of wherein said gate electrode is on described nanowire channel structure；
Sidewall spacer, the part of wherein said sidewall spacer laterally adjacent to described gate electrode in described nanowire channel
Part on structure；And
Source/drain structures, is epitaxially grown the either side in described nanowire channel structure, wherein said source/drain junctions
The part of structure is laterally adjacent to the described part of described sidewall spacer, and the described part of described sidewall spacer is the most neighbouring
The part on described nanowire channel structure of described gate electrode.
26. nano-wire devices as claimed in claim 25, it is characterised in that described nanowire channel structure includes passing through gap
The epitaxial silicon nanowire channel structure being spaced apart.
27. nano-wire devices as claimed in claim 25, it is characterised in that described nanowire channel structure includes passing through gap
The epitaxial sige nanowire channel structure being spaced apart.
28. nano-wire devices as claimed in claim 25, it is characterised in that described nanowire channel structure includes surrounding completely
The gate dielectric material of described nanowire channel structure and surround the metal gates of described nanowire channel structure.
29. nano-wire devices as claimed in claim 28, it is characterised in that described gate dielectric material includes high k grid
Dielectric substance.
30. nano-wire devices as claimed in claim 25, it is characterised in that described nanowire channel structure include epitaxial silicon and
One in epitaxial sige.
31. nano-wire devices as claimed in claim 25, it is characterised in that described source/drain structures includes epitaxial sige.
32. nano-wire devices as claimed in claim 25, it is characterised in that described substrate includes SOI substrate, and bottom is received
Rice noodle channel structure is arranged on the oxide portions of described SOI substrate.
33. nano-wire devices as claimed in claim 25, it is characterised in that described substrate includes SOI substrate, and bottom is received
Rice noodle channel structure is arranged on the oxide portions of described SOI substrate.
34. nano-wire devices as claimed in claim 25, it is characterised in that described device includes nmos device, wherein groove
Contact coupled to described source/drain structures, and described source/drain structures includes the silicon that n+ adulterates, and silicon epitaxy tip quilt
It is arranged between described source/drain structures and described substrate.
35. nano-wire devices as claimed in claim 25, it is characterised in that described device includes PMOS device, wherein groove
Contact coupled to described source/drain structures, and described source/drain structures includes the SiGe that p+ adulterates, and silicon epitaxy is most advanced and sophisticated
It is arranged between described source/drain structures and described substrate.
36. nano-wire devices as claimed in claim 25, it is characterised in that outside described nanowire channel structure includes being arranged on
Prolong the epitaxial sige nanowire channel on oxide nano thread channel structure.
37. nano-wire devices as claimed in claim 36, it is characterised in that described epitaxial oxide nano wire is partly lost
Carve.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111293250.5A CN114242764A (en) | 2010-12-01 | 2011-11-23 | Method of forming a device and method of forming a nanowire device |
| CN202111293126.9A CN114242763A (en) | 2010-12-01 | 2011-11-23 | Method of forming nanowire devices |
| CN201610421227.2A CN105923602A (en) | 2010-12-01 | 2011-11-23 | Silicon and silicon germanium nanowire structures |
| CN201811307141.2A CN109607475B (en) | 2010-12-01 | 2011-11-23 | Silicon and silicon germanium nanowire structures |
| CN201611050993.9A CN106449514A (en) | 2010-12-01 | 2011-11-23 | Silicon and silicon germanium nanowire structures |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/958,179 | 2010-12-01 | ||
| US12/958,179 US8753942B2 (en) | 2010-12-01 | 2010-12-01 | Silicon and silicon germanium nanowire structures |
| PCT/US2011/062059 WO2012074872A2 (en) | 2010-12-01 | 2011-11-23 | Silicon and silicon germanium nanowire structures |
Related Child Applications (5)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610421227.2A Division CN105923602A (en) | 2010-12-01 | 2011-11-23 | Silicon and silicon germanium nanowire structures |
| CN202111293126.9A Division CN114242763A (en) | 2010-12-01 | 2011-11-23 | Method of forming nanowire devices |
| CN201611050993.9A Division CN106449514A (en) | 2010-12-01 | 2011-11-23 | Silicon and silicon germanium nanowire structures |
| CN202111293250.5A Division CN114242764A (en) | 2010-12-01 | 2011-11-23 | Method of forming a device and method of forming a nanowire device |
| CN201811307141.2A Division CN109607475B (en) | 2010-12-01 | 2011-11-23 | Silicon and silicon germanium nanowire structures |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103238208A CN103238208A (en) | 2013-08-07 |
| CN103238208B true CN103238208B (en) | 2016-11-30 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855390A (en) * | 2005-03-24 | 2006-11-01 | 三星电子株式会社 | Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same |
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855390A (en) * | 2005-03-24 | 2006-11-01 | 三星电子株式会社 | Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same |
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Effective date of registration: 20200911 Address after: Tokyo, Japan Patentee after: Sony Corp. Address before: California, USA Patentee before: INTEL Corp. |